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Banc de test NanoFIP, Specification Generale
Important
- Page 10: it seems that the LEDs and jumpers are directly on the
Wishbone interface.
- This is not possible as they are driven by the FPGA too
- Even if the direct I/O from the NanoFIP is meant, I don't see these back in the schematics (page 4 schematics: there is a test connector, but there is no ground or Vcc to be able to make a plugin card for it).
- In fact there no LEDs in the schematics.
- NM (rev STG-A-005): this schematic is effectively wrong. Jumpers are used for NanoFip configuration only. Some LED can be added if necessary : currently, just 2 LED are implemented (power supply and Fip activity).
- Page 10: the loopback is shown, but it is not clear if this is
implemented on the actual card (e.g. the RS-485 comes from the FPGA
and not from the NanoFIP).
- NM (rev STG-A-005): i redrew this schematic... the loopback aims at copying FIP signal on a separate RS485 driver (I understood it as a CERN requirement). A FIP acquisition is also possible without using the FIP driver component
- The speed of the WorldFIP interface is not defined.
- NM (rev STG-A-005): I added the 3 available speeds (31.25 kbps, 1 Mbps, 2.5 Mbps )
- I guess we'll test at the highest speed now, but it should be clear what should be done to make slower speeds.
Minor
- It is not defined what WorldFIP master will be used to test, nor
what software is used there. How would one implement things like
send frame, check data at a cycle rate of 10 ms.
- Will this be part of the software specification?
-
NM : "WorldFIP master" --> do you mean WorldFip bus arbitrer?
If the nanoFip works "like" the microFip, once the device
configured and started (nanoFip), it manages its own
connectivity to FIP (sending/receiving variables , messages,
refreshment...). The FPGA should be able to access the FIP data
via the nanoFip WISHBONE interface (please confirm this point).
- EB : Indeed, it is the WorldFIP bus arbiter I meant. The question is about the total test system: what Bus Arbiter (a card inside a PC, I assume, or is there some USB card) will have to send variables to our NanoFIP, will request them and verify the values etc. So the question is, how your software will do verifications and drive this card?
- Page 2: Glossaire. VHDL stands for "Very High Speed Integrated
Circuit Hardware Description Language".
- NM (rev STG-A-005): correction ok
- Page 9: it's not needed (or really possible, I think as the power
planes will transfer the heat effectively) to have independent
temperature regulation.
- NM : for the moment, i let this point unchanged. If you need only one temperature command, I would be able to treat that with the FPGA firmware
Carte de test NanoFIP, Specifications techniques detaillees
Important
- Page 11: Calculation of dissipation needed for 60 degrees increase
is not clear. This may be very dependent on the size and layers of
the PCB, cooling by airflow and so. Anyway currently with 1W there
is no margin. Suggest to increase much higher to leave a margin.
Suggest some prototyping with a small PCB (how can just 1W heat up
such a large board by 60 degrees, anyway?)
- NM : i added dissipation for different resistor values. I will receive in few days some samples in order to do some tests. There is no airflow cooling but, as mentionned in the document, thermal dissipation modeling through PCB/tracks/planes is not an easy thing. Tests and debug phase will be useful to find the accurate resistor value
- Page 13: the used FPGA is not the same as the NanoFIP. But it has
the same number of pins.
- having the same FPGA helps in ordering, connectivity, etc.
- see recommendation No.7 in 1016-01-1 00-PRJ-B-005 -Document QR.xls
- NM : for debugging issue, i prefer to have all pins directly accessible. Pricewise, A3P125 is 50% cheaper and ordering issue will stay reasonnable with only 10 cards to build.
- Page 16: assumes that 9 Volt arrives at input. But it will be much
lower
- See page 6, Banc de Test - spec generale: "compte tenu des pertes" will have 9V before 50 meters of cable (and much less at input of card).
- Page 24: Good idea to have the address settable by jumper. But "les
sorties doivent etre en tri-state afin de ne pas generer de court
circuit si un jumper est positionnee". The device cannot know if a
jumper is inserted and therefore outputs can blow up. If you
implement the outputs to behave like open collector, it always
works. Suggestions: "va et vient switch" that switches between the
jumper settings or FPGA output.
- NM : i don't think there is a risk of destruction. The FPGA output will be in LOW or in Z state (HIGH state will be forbidden) and each jumper sets a line to LOW state : the LOW state is the dominant state. On the other hand, the FPGA can read the SUBS value : if value is 0xFF, then no jumper is connected else, at least one jumper is set.
Minor or observations
- Page 6: output "recopie FIP" wasn't asked for (not in spec generale), but may come in handy anyway.
- The total current of both supplies (3V3, 1V5) to the NanoFIP is measured, but not seperately. As there are no inputs on the ADC left, this is probably good enough (4 ADC inputs: Temp 2x, I NanoFIP, I Fieldrive).
- Page 27: "I2C EEPROM: configuration par defaut de la carte".
- It is not clear what configuration is in there. The FPGA (VHDL) configuration itself is stored in the Actel's own internal FLASH memory.
-
NM : the EEPROM is only used for user data. For example, FIP
configurable parameters (SUBS, SLONE, P3_LGTH ...), card
version, card ID, default PWM value ... All these data could be
loaded at power-up and then the NanoFip test card could be used
in a standalone way. Spec not yet written, all idea are welcome
- EB: OK, a very good idea indeed. Saves you from recompiling and generating new Actel files.
Schema Carte Adaptation
- Define the maximum Vin. It's specified now as 9V, but much more may be needed if the cable is long or too resistive.
Schema Carte Principale
Important
* The Jtag lines on main FPGA not connected properly (tms, tdi, tdo).
* Page 12 of main schematics: GCLK and GCLRN are inverted.
- NM (rev SCH-A-003): correction ok
* Move one of GCLK or GCLRN to another pin: the used pins cannot be used at the same time as a global signal.
-
Recommend to synthesise and place the current code and verify pin allocations.
-
NM (rev SCH-A-003): correction ok
* It is simpler to put one JTAG connector per fpga.
- NM (rev SCH-A-003): ok
* Not the same FPGA is used as the NanoFIP .
-
having the same FPGA helps in ordering, connectivity, etc.
-
see recommendation No.7 in 1016-01-1 00-PRJ-B-005 -Document QR.xls
* Increase the intensity rate from 1A to 3A for the nanofip 3V3 and 1V5 power supplies. The reason is that under radiation the current consumption may increase by a factor 3, while the device still will function.
- NM (rev SCH-A-003): NanoFip supply can hold up to 1A (warning: i think that with 1.5W dissipation, the NanoFip junctions approach the hazardous limit of 120°C)
* Need to adapt the range of the ADC of the current measurements as the current may be a factor three higher than typical.
- NM (rev SCH-A-003): correction ok - current sense resistor changed
* Suggest to add another ADC to measure the supply voltages (additional check to see that nothing changed there under radiation or that current limiting is active). Spare inputs may come in handy too.
** EB : Will you follow this suggestion?
-
NM : another ADC has been added in order to do the voltage measurement (1V5 and 3V3 nanofip supply, 5V fieldrive supply and 9V).
- The latchup protection circuit should take into account that under
radiation the current may be a factor three highter than typical.
- NM (rev SCH-A-003): correction ok - protection active at 1.2A current consumption
- How to configure the used speed? The fielddrive filter is designed
for 1Mb/s. I think it should be designed for the 2.5Mb/s rate. Could
it be configurable like on the FIPADUC/FIPDIAG?
- NM : FIP speed is hardware-defined. The bill of material allows to choose the speed among 31.25k, 1M or 2M5
- Page 2: Does the diode bridge protection correspond to any of the
examples in the fieldrive documentation?
- NM : compatible with all speeds and bus impedances
- Page 2: Level conversion from the FielDrive outputs to the NanoFIP.
Replace this by resistor dividers instead of the 7407s. This is
radiation tolerant and will be the way it used in real applications.
- NM (rev SCH-A-003): correction ok
- Page 2: the WorldFIP connector is connected differently than FIPDIAG
(pins 1 and 3 are now used, while they were unconnected).
- NM (rev SCH-A-003): this connection is a generic one adapted to different FIP configurations. I removed it for a cleaner schematic (only pins 6 and 7 connected in CERN config)
- Page 2: Originally it was asked to be able to use other drivers than
the FielDrive. Nothing is foreseen for this, no possibility even to
make a plug-in card. See if this is possible by adding some
connector.
- NM : that's the purpose of the rs485 driver on page 10. FIP signals arrive on FPGA that mix RxD and TxD to recopy the FIP network ( 485 drivers actually used in transmission only)
- Page 13: the multiplexers can be replaced by four banks of jumpers
(of which per bit only 1 of 4 is inserted). Removes problem if
radiation (although low) may upset these multiplexers.
- NM (rev SCH-A-003): correction ok
- Page 14: remove the RST input from the oscillator. It should always
be running.
- NM (rev SCH-A-003): correction ok
- There no LEDs in the schematics despite that they are described in
the specification.
- NM (rev SCH-A-003): only 2 LED -> power supply and Fip activity. Tell me if you want more LED
- The NanoFIP has no CYC_I Wishbone input. This was not specified in
the NanoFIP spec, but during the review we found that we likely will
need this signal. Connect this new pin to the main FPGA (pin
location will be communicated soon).
-
NM : please, keep me inform about that
- EB : CYC_I: connect to pin C2 please.
-
NM : please, keep me inform about that
- The latchup protection circuit should take into account that under
radiation the current may be a factor three highter than typical.
Minor or observations
- Level conversion between FielDrive and NanoFIP. Now with IC. Could
it work with a resistor as divider?
- NM (rev SCH-A-003): correction ok
- Would like a switch on slone and rate.
- NM : configuration by jumper added
- Page 5: JP4 header symbol: make it look like the physical one (2
rows of 5 pins).
- NM : correction OK (even if i guess there is no relation between the logical and the physical shape of a component ...)
- Page 11: typo: aorties -> sorties.
- Page 11: not clear whe all the pull-downs are needed.
- Page 14: why are there seperate clocks for the two FPGAs (FPGA: 24
MHz and NanoFIP: 40 MHz).
- Indeed the Wishbone bus can be asynchronous to the 40MHz, so this tests this nicely. But foresee to route the 40MHz clock to the FPGA too with a jumper or resistor (in case of problems and we like to run or test all synchronously).
- NM : i've done calculation with a 12MHz-multiple oscillator. Indeed, i put a dual implementation allowing the use of 1 or 2 oscillators
- There is no parts list showing order numbers and package types.
- _NM : see document "1016-10-1.00-FAB-A-xxx - Nomenclature NFTC.xls"
- Erik van der Bij, Nicolas Monge - 6 April 2010