added by Evangelia Gousiou on 2011-05-11 17:11:25.033278
20 NFTC boards pre-validated at HLP have been received and are now being
21-03-2011: V2 prototype validated
added by Evangelia Gousiou on 2011-03-21 18:18:17.386473
Two V2 test boards were received by HLP on Tuesday 15th March.
HLP validated them and shipped one board to CERN; it was received on
Friday March 18th.
At CERN the test board has been tested in memory loopback mode, 124
bytes, 5ms macrocycle and has performed more than 42.800.000 sucessful
cycles during the weekend 19-20 March.
It is considered therefore validated and the green light to the
production of the remaining 18 boards is already given!
08-03-2011: 20 test boards ordered
added by Erik van der Bij on 2011-03-15 10:47:53.413058
Twenty NanoFIP test boards are ordered. These boards will be an improved
version of the prototype that is working since July 2010. This version
has more test points and can also be used to test the foreseen JTAG
programming extension of the NanoFIP. We expect the new boards by the
end of March so that they will be ready for the tests under radiation in
28-09-2010: Production and consumption of variables working
added by Erik van der Bij on 2010-09-30 12:17:26.491440
The production and consumption of variables is working and has been
tested for over two days. The data is not yet checked continuously,
we're waiting for an extension of the firmware of the NanoFIP test board
that allows the NanoFIP to resend the data it has received.
30-08-2010: Presence and id variables read
added by Javier Serrano on 2010-09-01 18:40:22.152768
added by Erik van der Bij on 2010-07-22 16:29:55.377492
The test board and the software has been validated. It is now ready to
accept the first version of the NanoFIP code to start testing the
01-07-2010: steady progress
added by Erik van der Bij on 2010-07-01 11:50:00.957716
The assembly of the boards started and the firmware development is
progressing. A Draft software
is available with screenshots that give a good impression of the
10-06-2010: PCB layout OK. Prototype building starts.
added by Erik van der Bij on 2010-06-22 11:20:43.564295
The PCB layout has been verified and is OK. The PCB boards and all
components are ordered and will arrive end of June at the company. As
next step the firmware will be written. For this a version of the
firmware specification has been written and has been verified by CERN.
25-05-2010: New PCB layout received
added by Erik van der Bij on 2010-05-27 17:06:35.241187
We received a new layout that should include changes requested after the
PCB layout review. It will be verified before launching the production
of the prototypes.
12-05-2010: PCB layout review held
added by Erik van der Bij on 2010-05-12 17:01:45.664800
The PCB layout review has held. It revealed several issues that will
make the design more robust and that will improve its documentation. As
there are major corrections to be done, another review will be needed
before the PCB may be produced.
26-03-2010: Schematics review held
added by Erik van der Bij on 2010-03-26 18:05:15.551630
The review revealed several issues that will make the
design more robust and that will improve its documentation. The type of
issues found are typical for designs of this complexity. The changes
will be implemented before the PCB layout will start.
22-03-2010: Schematics ready for review
added by Erik van der Bij on 2010-03-22 16:37:18.724834
The schematics and documentation are ready for the review that will be
held on 26 March.