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nanoFIP - Gateware
Commit caddc235 authored by egousiou's avatar egousiou
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headers changed; dualClkRAM renamed to dualclkram_512x8.vhd; wf_bits_to_txd unit removed 

git-svn-id: http://svn.ohwr.org/cern-fip/trunk/hdl/design@232 7f0067c9-7624-46c7-bd39-3fb5400c0213
parent a1350268
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DualClkRAM.vhd → dualram_512x8.vhd
View file @ caddc235
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- --
-- DualClkRAM --
-- --
-- |
-- dualram_512x8 |
-- |
---------------------------------------------------------------------------------------------------
-- File DualClkRAM.vhd
--
-- Description Instantiation of a template ProAsic3 RAM4K9 memory component with
-- o word width : 8 bits and
-- o depth : 512 bytes.
--
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
-- Date 15/12/2010
-- Version v0.02
-- Depends on ProASIC3 lib
----------------
-- Last changes
-- 08/2010 v0.01 EG pepeline not used! data appears in output 1 clock cycle after the
-- address is given (otherwise it was 2 clock cycles later) slack
-- checked and is ok! code cleaned-up and commented
-- 15/12/2010 v0.02 EG comments for BLKA, BLKB; cleaning-up
--
-- File dualram_512x8.vhd |
-- |
-- Description Instantiation of a template ProAsic3 RAM4K9 memory component with |
-- o word width: 8 bits and |
-- o depth : 512 bytes. |
-- |
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 15/12/2010 |
-- Version v0.02 |
-- Depends on ProASIC3 lib |
---------------- |
-- Last changes |
-- 08/2010 v0.01 EG pepeline not used! data appears in output 1 clock cycle after the |
-- address is given (otherwise it was 2 clock cycles later) slack |
-- checked and is ok! code cleaned-up and commented |
-- 15/12/2010 v0.02 EG comments for BLKA, BLKB; cleaning-up |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
......@@ -59,11 +58,10 @@ use PROASIC3.all;
--=================================================================================================
-- Entity declaration for DualClkRAM
-- Entity declaration for dualram_512x8
--=================================================================================================
entity DualClkRAM is
port(
entity dualram_512x8 is port(
-- INPUTS
-- Inputs concerning port A
CLKA : in std_logic; -- clock A for synchronous read/ write operations
......@@ -86,15 +84,14 @@ entity DualClkRAM is
DOUTA : out std_logic_vector (7 downto 0); -- data out A
-- Output concerning port B
DOUTB : out std_logic_vector (7 downto 0) -- data out B
);
end DualClkRAM;
DOUTB : out std_logic_vector (7 downto 0));-- data out B
end dualram_512x8;
--=================================================================================================
-- architecture declaration
--=================================================================================================
architecture RAM4K9 of DualClkRAM is
architecture RAM4K9 of dualram_512x8 is
---------------------------------------------------------------------------------------------------
-- General information concerning RAM4K9: a fully synchronous, true dual-port RAM with an optional
......@@ -142,10 +139,10 @@ architecture RAM4K9 of DualClkRAM is
WENA, WENB,
CLKA, CLKB,
RESET : in std_logic := 'U';
----------------------------------------------------
DOUTA8, DOUTA7, DOUTA6, DOUTA5, DOUTA4, DOUTA3, DOUTA2, DOUTA1, DOUTA0,
DOUTB8, DOUTB7, DOUTB6, DOUTB5, DOUTB4, DOUTB3, DOUTB2, DOUTB1, DOUTB0 : out std_logic
);
DOUTB8, DOUTB7, DOUTB6, DOUTB5, DOUTB4, DOUTB3, DOUTB2, DOUTB1, DOUTB0 : out std_logic);
----------------------------------------------------
end component;
---------------------------------------------------------------------------------------------------
......@@ -172,8 +169,8 @@ architecture RAM4K9 of DualClkRAM is
begin
power_supply_signal : VCC port map (Y => POWER);
ground_signal : GND port map (Y => GROUND);
power_supply_signal : VCC port map(Y => POWER);
ground_signal : GND port map(Y => GROUND);
---------------------------------------------------------------------------------------------------
-- Instantiation of the component RAM4K9.
......@@ -186,7 +183,7 @@ begin
-- o WMODEA, WMODEB : GND (in write mode the output retains the data from the previous read)
A9D8DualClkRAM_R0C0 : RAM4K9
port map (
port map(
-- INPUTS
-- inputs concerning port A
-- data in A (1 byte, (7 downto 0))
......
nanofip.vhd
View file @ caddc235
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- --
-- nanoFIP --
-- --
-- |
-- nanoFIP |
-- |
---------------------------------------------------------------------------------------------------
-- File nanofip.vhd
--
-- Description The nanoFIP is an FPGA component implementing the WorldFIP protocol that can be
-- used in field devices. The nanoFIP is designed to be radiation tolerant by using different
-- single event upset mitigation techniques such as Triple Module Redundancy and several reset
-- possibilities. The nanoFIP design is to be implemented in an Actel ProASIC3 Flash family FPGA
-- that is preserving its configuration and has high tolerance to total dose radiation effects.
-- The device is used in conjunction with a FIELDRIVE chip and FIELDTR insulating transformer,
-- both available from the company ALSTOM.
--
-- In the WorldFIP protocol, the master of the bus, Bus Arbitrer (BA) initiates all the activity
-- in the bus. The BA is broadcasting ID_DAT frames, requesting for a particular variable, to all
-- the stations connected to the same network segment. Figure 1 shows the structure of an ID_DAT
-- frame:
-- ___________ ______ _______ ______ ___________ _______
-- |____FSS____|_Ctrl_||__Var__|_SUBS_||____FCS____|__FES__|
--
-- Figure 1 : ID_DAT frame structure
--
-- nanoFIP is handling the following set of variables addressed by:
-- o ID_DAT Var_Subs = 14_xy: for the presence variable
-- o ID_DAT Var_Subs = 10_xy: for the identification variable
-- o ID_DAT Var_Subs = 05_xy: for the consumed variable of any length up to 124 bytes
-- o ID_DAT Var_Subs = 91_..: for the broadcast consumed variable of any length up to 124 bytes
-- o ID_DAT Var_Subs = 06_xy: for the produced variable of a user-settable length (P3_LGTH)
-- o ID_DAT Var_Subs = E0_..: for the broadcast consumed reset variable
--
-- After a 14xy or a 10xy or a 06xy ID_DAT, if nanoFIP's address (SUBS) is xy, it will respond
-- with a "produced" RP_DAT frame, containing the variable requested. Figure 2 shows the structure
-- of a RP_DAT frame:
-- ___________ ______ ____________________ ___________ _______
-- |____FSS____|_Ctrl_||_____...Data..._____||____FCS____|__FES__|
--
-- Figure 2 : RP_DAT frame structure
--
-- After a 05xy ID_DAT, if nanoFIP's address (SUBS) is xy, or after a broadcast ID_DAT 91..h or
-- E0..h, nanoFIP will "consume" the incoming RP_DAT frame.
--
-- Regarding the interface with the user, nanoFIP provides:
-- o variable data transfer over an integrated memory accessible with an 8-bit WISHBONE
-- System-On-Chip interconnection
-- o possibility of stand-alone mode with a 16 bits input bus and 16 bits output bus, without
-- the need to transfer data to or from the memory
-- o separate data valid outputs for each variable (consumed and produced)
--
-- nanoFIP provides several reset possibilities:
-- o External reset input pin, RSTIN, activated by the user logic
-- o External reset input pin, RST_I, activated by the user, that resets only the WISHBONE logic
-- o Addressed reset by the reset broadcast consumed variable (E0..h),
-- validated by station address as data
-- o External Power On Reset input pin, RSTPON
--
-- nanoFIP also provides resets to the user and to the FIELDRIVE:
-- o Reset output available to external logic (RSTON) by the reset broadcast consumed variable
-- (E0..h), validated by station address as data
-- o FIELDRIVE reset output (FD_RSTN) by the reset broadcast consumed variable (E0..h),
-- validated by station address as data
--
-- nanoFIP's main building blocks are (Figure 3):
--
-- o WF_reset_unit : for the treatment of the reset input signals & the generation
-- of the reset outputs
--
-- o WF_consumption : for the processing, storage & validation of consumed RP_DAT frames
--
-- o WF_fd_receiver : for the deserialization of the FIELDRIVE input and the formation
-- of ID_DAT or consumed RP_DAT bytes of data
--
-- o WF_production : for the retreival of bytes for produced RP_DAT frames
--
-- o WF_fd_transmitter : for the serialization of produced RP_DAT frames
--
-- o WF_engine_control : for the processing of the ID_DAT frames and the coordination of the
-- WF_consumption, WF_fd_receiver, WF_production & WF_fd_transmitter units
--
-- o WF_model_constr_dec : for the decoding of the WorldFIP settings M_ID and C_ID and the
-- generation of the S_ID
--
-- o WF_wb_controller : for the handling of the "User Interface WISHBONE Slave" control
-- signals.
--
-- _____________ ____________________________________________________
-- | | | WF_WB_controller |
-- | | |____________________________________________________|
-- | | _____________ _____________
-- | | | | ______________ | |
-- | WF_reset | | | | | | |
-- | _unit | | WF_ | | | | WF_ |
-- | | | consumption | | | | production |
-- | | | | | | | |
-- | | | | | | | |
-- | | |_____________| | WF_ | |_____________|
-- |_____________| _____________ |engine_control| _____________
-- | | | | | |
-- _____________ | | | | | |
-- | | | | | | | |
-- | | | WF_FD_ | | | | WF_FD_ |
-- | WF_model_ | | receiver | | | | transmitter |
-- | constr_dec | | | | | | |
-- | | | | | | | |
-- |_____________| |_____________| |______________| |_____________|
--
-- Figure 3: nanoFIP block diagram
--
-- The design is based on the nanoFIP functional specification document, available at:
-- http://www.ohwr.org/projects/cern-fip/documents
-- Complete information about this project at: http://www.ohwr.org/projects/cern-fip
--
--
-- Authors Erik Van der Bij (Erik.Van.der.Bij@cern.ch)
-- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
-- Date 20/01/2011
-- Version v0.05
-- Depends on WF_reset_unit
-- WF_model_constr_dec
-- WF_tx_rx_osc
-- WF_consumption
-- WF_production
-- WF_engine_control
-- WF_wb_controller
----------------
-- Last changes
-- 30/06/2009 v0.010 EB First version
-- 06/07/2009 v0.011 EB Dummy blocks
-- 07/07/2009 v0.011 EB Comments
-- 15/09/2009 v0.v2 PA
-- 09/12/2010 v0.v3 EG Logic removed (new unit inputs_synchronizer added)
-- 7/01/2011 v0.04 EG major restructuring; only 7 units on top level
-- 20/01/2011 v0.05 EG new unit WF_wb_controller(removes the or gate from top level)
-- File : nanofip.vhd |
-- |
-- Description: nanoFIP is an FPGA component acting as a client node/ agent in the communication |
-- over WorldFIP fieldbus. nanoFIP is designed to be radiation tolerant by using different |
-- Single Event Upset mitigation techniques such as Triple Module Redundancy, fail-safe state |
-- machines and several reset possibilities. The nanoFIP design is to be implemented in an Actel |
-- ProASIC3 Flash family FPGA (130nm CMOS technology) that offers an inherent resistance to |
-- radiation: it is immune to Single Event Latchups for the LHC environment, it has high tolerance|
-- to Total Ionizing Dose effects and its configuration memory is not disturbed by SEUs. |
-- Another feature that nanoFIP offers is the possibility to reprogram the user logic through |
-- JTAG interface; WorldFIP frames are translated to the equivalent JTAG signals that drive and |
-- control the user logic TAP controller. |
-- nanoFIP is used in conjunction with a FIELDRIVE chip and FIELDTR insulating transformer, |
-- both available from the company ALSTOM. |
-- |
-- __________________________________________________________________ |
-- | | |
-- | Field devices, Radioactive environment | Radiation free zone |
-- | _____________ _____________ _____________ | _______________ |
-- | | | | | | | | | | |
-- | | user logic | | user logic | | user logic | | | | |
-- | |_____________| |_____________| |_____________| | | | |
-- | ______|______ ______|______ ______|______ | | | |
-- | | | | | | | | | BUS ARBITRER | |
-- | | nanoFIP | | nanoFIP | . . . | nanoFIP | | | | |
-- | |_____________| |_____________| |_____________| | | | |
-- | _____|_____ _____|_____ _____|_____ | | | |
-- | |_FIELDRIVE_| |_FIELDRIVE_| |_FIELDRIVE_| | | | |
-- | _____|_____ _____|_____ _____|_____ | | | |
-- | |__FIELDTR__| |__FIELDTR__| |__FIELDTR__| | |_______________| |
-- | | | | | | |
-- |________|_____________________|________________________|__________| | |
-- | | | | |
-- _______^_____________________^________________________^________________________^____________ |
-- 0____________________________________WorldFIP FIELDBUS______________________________________O |
-- |
-- Figure 1: Fieldbus layout |
-- |
-- In the WorldFIP protocol, the access to the bus is controlled by a central Bus Arbitrer (BA) |
-- that grants bus access to the different agents following the sequence in a pre-configured |
-- table. The BA is broadcasting ID_DAT frames to all the agents connected to the same network |
-- segment requesting for a particular variable. Figure 2 shows the structure of an ID_DAT frame: |
-- ___________ ______ _______ ______ ___________ _______ |
-- |____FSS____|_CTRL_||__Var__|_SUBS_||____FCS____|__FES__| |
-- |
-- Figure 2 : ID_DAT frame structure |
-- |
-- nanoFIP agents can handle the following set of variables: |
-- o ID_DAT Var_Subs = 14_xy: for the presence variable |
-- o ID_DAT Var_Subs = 10_xy: for the identification variable |
-- o ID_DAT Var_Subs = 05_xy: for the consumed variable of any length up to 124 bytes |
-- o ID_DAT Var_Subs = aa_xy: for the JTAG consumed variable of any length up to 124 bytes |
-- o ID_DAT Var_Subs = 91_..: for the broadcast consumed variable of any length up to 124 bytes |
-- o ID_DAT Var_Subs = 06_xy: for the produced variable of a user-settable length (P3_LGTH) |
-- o ID_DAT Var_Subs = ab_xy: for the JTAG produced variable of a predefined length of 1 byte |
-- o ID_DAT Var_Subs = E0_..: for the broadcast consumed reset variable |
-- |
-- After a 14_xy, a 10_xy, a 06_xy or a ab_xy ID_DAT, if nanoFIP's address (SUBS) is xy, it will |
-- respond with a "produced" RP_DAT frame, containing the variable requested. Figure 3 shows the |
-- structure of a RP_DAT frame: |
-- ___________ ______ ____________________ ___________ _______ |
-- |____FSS____|_CTRL_||_____...Data..._____||____FCS____|__FES__| |
-- |
-- Figure 3 : RP_DAT frame structure |
-- |
-- After a 05_xy or an aa_xy ID_DAT, if nanoFIP's address (SUBS) is xy, |
-- or after a broadcast ID_DAT 91..h or E0..h, nanoFIP will "consume" the incoming RP_DAT frame. |
-- |
-- Regarding the interface with the user logic, nanoFIP provides: |
-- o data transfer over an integrated memory accessible with an 8-bit WISHBONE System-On-Chip |
-- interconnection |
-- o possibility of stand-alone mode with a 16 bits input bus and 16 bits output bus, without |
-- the need to transfer data to or from the memory |
-- o separate data valid outputs for each variable (consumed and produced) |
-- o JTAG master controller interfacing with the Test Access Port of the user FPGA. |
-- |
-- nanoFIP provides several reset possibilities: |
-- o External reset input pin, RSTIN, activated by the user logic |
-- o External reset input pin, RST_I, activated by the user, that resets only the WISHBONE logic |
-- o Addressed reset by the reset broadcast consumed variable (E0..h), |
-- validated by station address as data |
-- o External Power On Reset input pin, RSTPON |
-- |
-- nanoFIP also provides resets to the user and to the FIELDRIVE: |
-- o Reset output available to external logic (RSTON) by the reset broadcast consumed variable |
-- (E0..h), validated by station address as data |
-- o FIELDRIVE reset output (FD_RSTN) by the reset broadcast consumed variable (E0..h), |
-- validated by station address as data |
-- |
-- nanoFIP's main building blocks are (Figure 4): |
-- |
-- o WF_reset_unit : for the treatment of the reset input signals & the generation |
-- of the reset outputs |
-- |
-- o WF_fd_receiver : for the deserialization of the FIELDRIVE input and the formation |
-- of ID_DAT or consumed RP_DAT bytes of data |
-- |
-- o WF_consumption : for the processing, storage & validation of consumed RP_DAT frames |
-- |
-- o WF_fd_transmitter : for the serialization of produced RP_DAT frames |
-- |
-- o WF_production : for the retreival of bytes for produced RP_DAT frames |
-- |
-- o WF_engine_control : for the processing of the ID_DAT frames and the coordination of the |
-- WF_consumption, WF_fd_receiver, WF_production&WF_fd_transmitter units |
-- |
-- o WF_model_constr_dec : for the decoding of the WorldFIP settings M_ID and C_ID and the |
-- generation of the S_ID |
-- |
-- o WF_wb_controller : for the handling of the "User Interface WISHBONE Slave" control |
-- signals |
-- |
-- o WF_jtag_controller : for driving the user-logic TAP controller upon reception of JTAG |
-- variables. |
-- |
-- _____________ ____________________________________________________ |
-- | | | WF_WB_controller | |
-- | WF_reset | |____________________________________________________| |
-- | _unit | _____________ _____________ |
-- | | | | ______________ | | |
-- |_____________| | | | | | | |
-- | WF_ | | | | WF_ | |
-- _____________ | consumption | | | | production | |
-- | | | | | | | | |
-- | WF_JTAG | | | | | | | |
-- | _controller | |_____________| | WF_ | |_____________| |
-- | | _____________ |engine_control| _____________ |
-- |_____________| | | | | | | |
-- | | | | | | |
-- _____________ | | | | | | |
-- | | | WF_FD_ | | | | WF_FD_ | |
-- | WF_model_ | | receiver | | | | transmitter | |
-- | constr_dec | | | | | | | |
-- | | | | | | | | |
-- |_____________| |_____________| |______________| |_____________| |
-- |
-- Figure 4: nanoFIP block diagram |
-- |
-- The design is based on the nanoFIP functional specification document, available at: |
-- http://www.ohwr.org/projects/cern-fip/documents |
-- Complete information about this project at: http://www.ohwr.org/projects/cern-fip |
-- |
-- |
-- Authors Erik Van der Bij (Erik.Van.der.Bij@cern.ch) |
-- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 10/2011 |
-- Version v0.06 |
-- Depends on WF_reset_unit |
-- WF_model_constr_dec |
-- WF_tx_rx_osc |
-- WF_consumption |
-- WF_production |
-- WF_engine_control |
-- WF_wb_controller |
-- WF_jtag_controller |
---------------- |
-- Last changes |
-- 30/06/2009 v0.010 EB First version |
-- 06/07/2009 v0.011 EB Dummy blocks |
-- 07/07/2009 v0.011 EB Comments |
-- 15/09/2009 v0.v2 PA |
-- 09/12/2010 v0.v3 EG Logic removed (new unit inputs_synchronizer added) |
-- 7/01/2011 v0.04 EG major restructuring; only 7 units on top level |
-- 20/01/2011 v0.05 EG new unit WF_wb_controller(removes the or gate from top level) |
-- 06/2011 v0.06 EG jtag_controller unit added |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
......@@ -174,9 +210,7 @@ use work.WF_PACKAGE.all; -- definitions of types, constants, entities
-- Entity declaration for nanoFIP
--=================================================================================================
entity nanofip is
port (
entity nanofip is port(
--INPUTS
......@@ -235,7 +269,7 @@ entity nanofip is
-- User Interface, JTAG Controller
jc_tdo_i : in std_logic;
jc_tdo_i : in std_logic; -- JTAG target Test Data Out
......@@ -278,15 +312,12 @@ entity nanofip is
ack_o : out std_logic; -- WISHBONE acknowledge
TP39 : out std_logic;
-- User Interface, JTAG Controller
jc_tms_o : out std_logic;
jc_tdi_o : out std_logic;
jc_tck_o : out std_logic
);
jc_tms_o : out std_logic; -- JTAG target Test Mode Select
jc_tdi_o : out std_logic; -- JTAG target Test Data In
jc_tck_o : out std_logic); -- JTAG target Test Clock
end entity nanofip;
......@@ -297,43 +328,34 @@ end entity nanofip;
architecture struc of nanofip is
---------------------------------------------------------------------------------------------------
-- Synplify Triple Module Redundancy --
---------------------------------------------------------------------------------------------------
attribute syn_radhardlevel : string; --
attribute syn_radhardlevel of struc : architecture is "tmr"; --
---------------------------------------------------------------------------------------------------
-- WF_reset_unit iutputs
signal s_nfip_intern_rst, s_wb_rst : std_logic;
signal s_nfip_intern_rst, s_wb_rst : std_logic;
-- WF_consumption outputs
signal s_var1_rdy, s_var2_rdy, s_var3_rdy : std_logic;
signal s_assert_RSTON_p, s_reset_nFIP_and_FD_p, s_nfip_status_r_tler : std_logic;
signal s_jc_start_p : std_logic;
signal s_jc_mem_data : std_logic_vector (7 downto 0);
signal s_var1_rdy, s_var2_rdy, s_var3_rdy : std_logic;
signal s_assert_RSTON_p, s_reset_nFIP_and_FD_p : std_logic;
signal s_nfip_status_r_tler : std_logic;
signal s_jc_start_p : std_logic;
signal s_jc_mem_data : std_logic_vector (7 downto 0);
-- WF_fd_receiver outputs
signal s_rx_fss_received_p, s_rx_fss_crc_fes_ok_p, s_rx_crc_wrong_p : std_logic;
signal s_rx_byte_ready_p : std_logic;
signal s_rx_byte : std_logic_vector (7 downto 0);
signal s_rx_fss_received_p, s_rx_fss_crc_fes_ok_p : std_logic;
signal s_rx_crc_wrong_p, s_rx_byte_ready_p : std_logic;
signal s_rx_byte : std_logic_vector (7 downto 0);
-- WF_production outputs
signal s_byte_to_tx : std_logic_vector (7 downto 0);
signal s_byte_to_tx : std_logic_vector (7 downto 0);
-- WF_fd_transmitter outputs
signal s_tx_last_byte_p, s_tx_completed_p : std_logic;
signal s_tx_last_byte_p, s_tx_completed_p : std_logic;
-- WF_engine_control outputs
signal s_tx_start_p, s_tx_request_byte_p, s_byte_request_accepted_p : std_logic;
signal s_cons_bytes_excess, s_rx_rst : std_logic;
signal s_var : t_var;
signal s_prod_data_lgth, s_prod_cons_byte_index : std_logic_vector (7 downto 0);
signal s_tx_start_p, s_tx_request_byte_p : std_logic;
signal s_byte_request_accepted_p, s_cons_bytes_excess, s_rx_rst : std_logic;
signal s_var : t_var;
signal s_prod_data_lgth, s_prod_byte_index, s_cons_byte_index : std_logic_vector (7 downto 0);
-- WF_model_constr_dec outputs
signal s_model_id_dec, s_constr_id_dec : std_logic_vector (7 downto 0);
signal s_model_id_dec, s_constr_id_dec : std_logic_vector (7 downto 0);
-- WF_wb_controller outputs
signal s_wb_ack_prod : std_logic;
signal s_wb_ack_prod : std_logic;
-- WF_model_constr_dec outputs
signal s_jc_mem_adr_rd : std_logic_vector (8 downto 0);
signal s_jc_tdo_byte : std_logic_vector (7 downto 0);
signal s_jc_mem_adr_rd : std_logic_vector (8 downto 0);
signal s_jc_tdo_byte : std_logic_vector (7 downto 0);
--=================================================================================================
......@@ -347,7 +369,7 @@ begin
---------------------------------------------------------------------------------------------------
reset_unit : WF_reset_unit
port map (
port map(
uclk_i => uclk_i,
wb_clk_i => wclk_i,
rstin_a_i => rstin_i,
......@@ -370,7 +392,7 @@ begin
---------------------------------------------------------------------------------------------------
Consumption: WF_consumption
port map (
port map(
uclk_i => uclk_i,
slone_i => slone_i,
nfip_rst_i => s_nfip_intern_rst,
......@@ -383,7 +405,7 @@ begin
wb_adr_i => adr_i (8 downto 0),
cons_bytes_excess_i => s_cons_bytes_excess,
var_i => s_var,
byte_index_i => s_prod_cons_byte_index,
byte_index_i => s_cons_byte_index,
jc_mem_adr_rd_i => s_jc_mem_adr_rd,
-------------------------------------------------------------
var1_rdy_o => s_var1_rdy,
......@@ -403,7 +425,7 @@ begin
---------------------------------------------------------------------------------------------------
FIELDRIVE_Receiver: WF_fd_receiver
port map (
port map(
uclk_i => uclk_i,
rate_i => rate_i,
fd_rxd_a_i => fd_rxd_i,
......@@ -424,7 +446,7 @@ begin
---------------------------------------------------------------------------------------------------
Production: WF_production
port map (
port map(
uclk_i => uclk_i,
slone_i => slone_i,
nostat_i => nostat_i,
......@@ -441,7 +463,7 @@ begin
fd_wdgn_a_i => fd_wdgn_i,
var_i => s_var,
data_lgth_i => s_prod_data_lgth,
byte_index_i => s_prod_cons_byte_index,
byte_index_i => s_prod_byte_index,
byte_request_accept_p_i => s_byte_request_accepted_p,
nfip_status_r_tler_p_i => s_nfip_status_r_tler,
nfip_status_r_fcser_p_i => s_rx_crc_wrong_p,
......@@ -466,7 +488,7 @@ begin
---------------------------------------------------------------------------------------------------
FIELDRIVE_Transmitter: WF_fd_transmitter
port map (
port map(
uclk_i => uclk_i,
rate_i => rate_i,
nfip_rst_i => s_nfip_intern_rst,
......@@ -489,7 +511,7 @@ begin
---------------------------------------------------------------------------------------------------
JTAG_controller: WF_jtag_controller
port map (
port map(
uclk_i => uclk_i,
nfip_rst_i => s_nfip_intern_rst,
jc_mem_data_i => s_jc_mem_data,
......@@ -503,14 +525,14 @@ begin
jc_mem_adr_rd_o => s_jc_mem_adr_rd);
-----------------------------------------------------------------
TP39 <= s_jc_tdo_byte(0);
---------------------------------------------------------------------------------------------------
-- WF_engine_control --
---------------------------------------------------------------------------------------------------
engine_control : WF_engine_control
port map (
port map(
uclk_i => uclk_i,
nfip_rst_i => s_nfip_intern_rst,
tx_byte_request_p_i => s_tx_request_byte_p,
......@@ -530,7 +552,8 @@ begin
tx_start_p_o => s_tx_start_p,
tx_byte_request_accept_p_o => s_byte_request_accepted_p,
tx_last_data_byte_p_o => s_tx_last_byte_p,
prod_cons_byte_index_o => s_prod_cons_byte_index,
prod_byte_index_o => s_prod_byte_index,
cons_byte_index_o => s_cons_byte_index,
prod_data_lgth_o => s_prod_data_lgth,
cons_bytes_excess_o => s_cons_bytes_excess,
rx_rst_o => s_rx_rst);
......@@ -547,13 +570,13 @@ begin
---------------------------------------------------------------------------------------------------
model_constr_decoder : WF_model_constr_decoder
port map (
port map(
uclk_i => uclk_i,
nfip_rst_i => s_nfip_intern_rst,
model_id_i => m_id_i,
constr_id_i => c_id_i,
-------------------------------------------------------------
select_id_o => s_id_o,
s_id_o => s_id_o,
model_id_dec_o => s_model_id_dec,
constr_id_dec_o => s_constr_id_dec);
-------------------------------------------------------------
......@@ -565,7 +588,7 @@ begin
---------------------------------------------------------------------------------------------------
WISHBONE_controller: WF_wb_controller
port map (
port map(
wb_clk_i => wclk_i,
wb_rst_i => s_wb_rst,
wb_stb_i => stb_i,
......
wf_cons_bytes_processor.vhd
View file @ caddc235
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
......@@ -10,58 +10,58 @@
-- WF_cons_bytes_processor |
-- |
---------------------------------------------------------------------------------------------------
-- File WF_cons_bytes_processor.vhd
--
-- Description The unit is consuming the RP_DAT data bytes that are arriving from the
-- WF_fd_receiver, according to the following:
--
-- o If the variable identifier of the preceded ID_DAT was a var_1 or a var_2:
--
-- o If the operation is in memory mode : the unit is registering the
-- application-data bytes along with the PDU_TYPE, Length and MPS bytes in the
-- Consumed memories
--
-- o If the operation is in stand-alone mode: the unit is transferring the 2 appli-
-- cation-data bytes to the "nanoFIP User Interface, NON_WISHBONE" data bus DAT_O
--
-- o If the consumed variable had been a var_rst, the 2 application-data bytes are
-- identified and sent to the WF_reset_unit.
--
-- Note: The validity of the consumed bytes (stored in the memory or transfered to DATO
-- or transfered to the WF_reset_unit) is indicated by the "nanoFIP User Interface,
-- NON_WISHBONE" signals VAR1_RDY/ VAR2_RDY or the nanoFIP internal signals
-- rst_nFIP_and_FD_p/ assert_RSTON_p, which are treated in the WF_cons_outcome unit and
-- are assessed after the end of the reception of a complete frame.
--
--
-- Reminder:
--
-- Consumed RP_DAT frame structure :
-- ___________ ______ _______ ________ __________________ _______ ___________ _______
-- |____FSS____|_Ctrl_||__PDU__|__LGTH__|__..ApplicData..__|__MPS__||____FCS____|__FES__|
--
-- |--------&LGTH bytes-------|
-- |---------write to Consumed memory----------|
-- |-----to DAT_O-----|
-- |---to Reset Unit--|
--
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
-- Date 15/12/2010
-- Version v0.03
-- Depends on WF_reset_unit
-- WF_fd_receiver
-- WF_engine_control
----------------
-- Last changes
-- 11/09/2009 v0.01 EB First version
-- 09/2010 v0.02 EG Treatment of reset variable added; Bytes_Transfer_To_DATO unit
-- creation for simplification; Signals renamed;
-- Ctrl, PDU_TYPE, Length bytes registered;
-- Code cleaned-up & commented.
-- 15/12/2010 v0.03 EG Unit renamed from WF_cons_bytes_from_rx to WF_cons_bytes_processor
-- byte_ready_p comes from the rx_deserializer (no need to pass from
-- the engine) Code cleaned-up & commented (more!)
-- File WF_cons_bytes_processor.vhd |
-- |
-- Description The unit is consuming the RP_DAT data bytes that are arriving from the |
-- WF_fd_receiver, according to the following: |
-- |
-- o If the variable identifier of the preceded ID_DAT was a var_1 or a var_2: |
-- |
-- o If the operation is in memory mode : the unit is registering the |
-- application-data bytes along with the PDU_TYPE, LGTH and MPS bytes in the |
-- Consumed memories |
-- |
-- o If the operation is in stand-alone mode: the unit is transferring the 2 appli-|
-- cation-data bytes to the "nanoFIP User Interface, NON_WISHBONE" data bus DAT_O|
-- |
-- o If the consumed variable had been a var_rst, the 2 application-data bytes are |
-- identified and sent to the WF_reset_unit. |
-- |
-- Note: The validity of the consumed bytes (stored in the memory or transfered to |
-- DATO or transfered to the WF_reset_unit) is indicated by the "nanoFIP User |
-- Interface, NON_WISHBONE" signals VAR1_RDY/ VAR2_RDY or the nanoFIP internal signals
-- rst_nFIP_and_FD_p/ assert_RSTON_p, which are treated in the WF_cons_outcome unit |
-- and are assessed after the end of the reception of a complete frame. |
-- |
-- |
-- Reminder: |
-- |
-- Consumed RP_DAT frame structure : |
-- ___________ ______ _______ ________ __________________ _______ ___________ _______ |
-- |____FSS____|_CTRL_||__PDU__|__LGTH__|__..ApplicData..__|__MPS__||____FCS____|__FES__| |
-- |
-- |--------&LGTH bytes-------| |
-- |---------write to Consumed memory----------| |
-- |-----to DAT_O-----| |
-- |---to Reset Unit--| |
-- |
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 15/12/2010 |
-- Version v0.03 |
-- Depends on WF_reset_unit |
-- WF_fd_receiver |
-- WF_engine_control |
---------------- |
-- Last changes |
-- 11/09/2009 v0.01 EB First version |
-- 09/2010 v0.02 EG Treatment of reset variable added; Bytes_Transfer_To_DATO unit |
-- creation for simplification; Signals renamed; |
-- CTRL, PDU_TYPE, LGTH bytes registered; |
-- Code cleaned-up & commented. |
-- 15/12/2010 v0.03 EG Unit renamed from WF_cons_bytes_from_rx to WF_cons_bytes_processor |
-- byte_ready_p comes from the rx_deserializer (no need to pass from |
-- the engine) Code cleaned-up & commented (more!) |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
......@@ -95,9 +95,7 @@ use work.WF_PACKAGE.all; -- definitions of types, constants, entities
--=================================================================================================
-- Entity declaration for WF_cons_bytes_processor
--=================================================================================================
entity WF_cons_bytes_processor is
port (
entity WF_cons_bytes_processor is port(
-- INPUTS
-- nanoFIP User Interface, General signals
uclk_i : in std_logic; -- 40 MHz clock
......@@ -134,12 +132,12 @@ port (
jc_mem_data_o : out std_logic_vector (7 downto 0);
-- Signals to the WF_cons_outcome unit
cons_ctrl_byte_o : out std_logic_vector (7 downto 0); -- received RP_DAT Control byte
cons_lgth_byte_o : out std_logic_vector (7 downto 0); -- received RP_DAT Length byte
cons_ctrl_byte_o : out std_logic_vector (7 downto 0); -- received RP_DAT CTRL byte
cons_lgth_byte_o : out std_logic_vector (7 downto 0); -- received RP_DAT LGTH byte
cons_pdu_byte_o : out std_logic_vector (7 downto 0); -- received RP_DAT PDY_TYPE byte
cons_var_rst_byte_1_o : out std_logic_vector (7 downto 0); -- received var_rst RP_DAT, 1st data byte
cons_var_rst_byte_2_o : out std_logic_vector (7 downto 0) -- received var_rst RP_DAT, 2nd data byte
);
cons_var_rst_byte_2_o : out std_logic_vector (7 downto 0)); -- received var_rst RP_DAT, 2nd data byte
end entity WF_cons_bytes_processor;
......@@ -148,15 +146,20 @@ end entity WF_cons_bytes_processor;
--=================================================================================================
architecture rtl of WF_cons_bytes_processor is
-- addressing the memory
signal s_base_adr : unsigned (8 downto 0);
signal s_adr : std_logic_vector (8 downto 0);
signal s_slone_data_out : std_logic_vector (15 downto 0);
signal s_mem_data_out : std_logic_vector (7 downto 0);
-- bus/ memories write enable
signal s_slone_wr_en_p : std_logic_vector (1 downto 0);
signal s_mem_wr_en_p : std_logic;
signal s_jc_mem_wr_en_p : std_logic;
-- data bytes
signal s_slone_data_out : std_logic_vector (15 downto 0);
signal s_mem_data_out : std_logic_vector (7 downto 0);
-- Length byte
signal s_cons_lgth_byte : std_logic_vector (7 downto 0);
--=================================================================================================
-- architecture begin
--=================================================================================================
......@@ -171,13 +174,8 @@ begin
-- Port A is connected to the WISHBONE interface for the readings from the user and
-- Port B is used by the nanoFIP for the writings into the memory.
Consumption_RAM : WF_DualClkRAM_clka_rd_clkb_wr
generic map (
g_ram_data_lgth => 8, -- 8 bits: length of data word
g_ram_addr_lgth => 9) -- 2^9: depth of consumed RAM
-- first 2 bits : identification of memory block
-- remaining 7 : address of a byte inside the blck
port map (
Consumption_RAM : WF_dualram_512x8_clka_rd_clkb_wr
port map(
clk_porta_i => wb_clk_i, -- WISHBONE clock
addr_porta_i => wb_adr_i, -- address of byte to be read
clk_portb_i => uclk_i, -- 40 MHz clock
......@@ -192,19 +190,14 @@ begin
---------------------------------------------------------------------------------------------------
-- JTAG Consumed RAM --
-- Storage (by this unit) & retreival (by the JTAG_controller unit) of consumed bytes --
-- Storage (by this unit) & retreival (by the JTAG_controller unit) of consumed bytes --
---------------------------------------------------------------------------------------------------
-- Instantiation of a Dual Port Consumed RAM (for both the consumed and consumed broadcast vars).
-- Port A is connected to the WISHBONE interface for the readings from the user and
-- Port B is used by the nanoFIP for the writings into the memory.
-- Instantiation of a Dual Port Consumed RAM for the storage of jc_var1 variables.
-- nanoFIP's user clock uclk is connected to both ports of the memory; the writing of the consumed
-- data and the reading of them (by the wf_jtag_controller) takes place internally inside nanoFIP.
Consumption_JTAG_RAM : WF_DualClkRAM_clka_rd_clkb_wr
generic map (
g_ram_data_lgth => 8, -- 8 bits: length of data word
g_ram_addr_lgth => 9) -- 2^9: depth of consumed RAM
-- first 2 bits : identification of memory block
-- remaining 7 : address of a byte inside the blck
port map (
Consumption_JTAG_RAM : WF_dualram_512x8_clka_rd_clkb_wr
port map(
clk_porta_i => uclk_i, -- user clock
addr_porta_i => jc_mem_adr_rd_i, -- address of byte to be read
clk_portb_i => uclk_i, -- 40 MHz clock
......@@ -252,8 +245,7 @@ begin
-- In stand-alone mode the 16 bits DAT_O fills up with the s_slone_data_out.
-- In memory mode,the lsb of DAT_O contains the output of the reading of the consumed memory
data_o <= s_slone_data_out when slone_i = '1'
else "00000000" & s_mem_data_out;
data_o <= s_slone_data_out when slone_i = '1' else "00000000" & s_mem_data_out;
......@@ -263,23 +255,23 @@ begin
-- Combinatorial process Bytes_Processing: Data bytes are consumed according to the
-- variable type (var_1, var_2, var_rst) they belong to.
-- In memory and in stand-alone mode, bytes are consumed even if any of the Control, PDU_TYPE,
-- Length, CRC or FES bytes of the consumed RP_DAT frame are incorrect.
-- In memory and in stand-alone mode, bytes are consumed even if any of the CTRL, PDU_TYPE,
-- LGTH, CRC or FES bytes of the consumed RP_DAT frame are incorrect.
-- It is the VAR_RDY signal that signals the user for the validity of the consumed data.
-- In memory mode the treatment of a var_1 is identical to the one of a var_2; it is only the base
-- address of the memory that differs. The incoming bytes (byte_i) after the CTRL byte and
-- before the CRC bytes, are written in the memory one by one as they arrive, on the moments
-- indicated by the byte_ready_p_i pulses.
-- indicated by the byte_ready_p_i pulses.
-- To distinguish the CTRL and the CRC bytes from the rest, the signals byte_index_i and LGTH
-- (s_cons_lgth_byte) are used:
-- (s_cons_lgth_byte) are used:
-- o the Control byte arrives when byte_index_i = 0
-- o the CTRL byte arrives when byte_index_i = 0
-- o the CRC bytes arrive &LGTH bytes after the LGTH byte.
-- Note: the byte_index_i signal coming from the wf_engine_control is counting each byte after the
-- FSS and before the FES.
-- FSS and before the FES.
-- the Length byte (s_cons_lgth_byte) is received when byte_index_i is equal to 3 and
-- the LGTH byte (s_cons_lgth_byte) is received when byte_index_i is equal to 3 and
-- indicates the amount of bytes in the frame after the CTRL, PDU_TYPE and itself and
-- before the CRC.
-- In stand-alone mode, in total two bytes of data have to be transferred to the DAT_O bus. The
......@@ -292,7 +284,7 @@ begin
s_adr <= std_logic_vector (unsigned(byte_index_i)+s_base_adr - 1); -- memory address of
-- the byte to be written
-- (-1 bc the Ctrl
-- (-1 bc the CTRL
-- byte is not written)
Bytes_Processing: process (var_i,byte_index_i,slone_i, byte_i, byte_ready_p_i,s_cons_lgth_byte)
......@@ -321,9 +313,9 @@ begin
if (unsigned(byte_index_i)> 0 and unsigned(byte_index_i)< 127) then -- memory limits
if byte_index_i > c_LGTH_BYTE_INDEX then -- after the reception
-- of the Length byte
-- of the LGTH byte
if unsigned(byte_index_i) <= unsigned(s_cons_lgth_byte) + 2 then -- less or eq
s_mem_wr_en_p <= byte_ready_p_i; -- &Length amount of
s_mem_wr_en_p <= byte_ready_p_i; -- &LGTH amount of
-- bytes are written
--(to avoid writing CRC!)
else
......@@ -331,16 +323,17 @@ begin
end if;
else -- before the reception
s_mem_wr_en_p <= byte_ready_p_i; -- of the Length byte
s_mem_wr_en_p <= byte_ready_p_i; -- of the LGTH byte
end if; -- all the bytes (after
-- Control) are written
-- CTRL) are written
else
s_mem_wr_en_p <= '0';
end if;
-- -- -- -- -- -- -- -- -- -- -- --
-- in stand-alone mode
elsif slone_i = '1' then
else -- slone_i = '1' then
s_mem_wr_en_p <= '0';
......@@ -438,9 +431,9 @@ begin
if (unsigned(byte_index_i)> 0 and unsigned(byte_index_i)< 127) then -- memory limits
if byte_index_i > c_LGTH_BYTE_INDEX then -- after the reception
-- of the Length byte
-- of the LGTH byte
if unsigned(byte_index_i) <= unsigned(s_cons_lgth_byte) + 2 then -- less or eq
s_jc_mem_wr_en_p <= byte_ready_p_i; -- &Length amount of
s_jc_mem_wr_en_p <= byte_ready_p_i; -- &LGTH amount of
-- bytes are written
--(to avoid writing CRC!)
else
......@@ -448,9 +441,9 @@ begin
end if;
else -- before the reception
s_jc_mem_wr_en_p <= byte_ready_p_i; -- of the Length byte
s_jc_mem_wr_en_p <= byte_ready_p_i; -- of the LGTH byte
end if; -- all the bytes (after
-- Control) are written
-- CTRL) are written
else
s_jc_mem_wr_en_p <= '0';
end if;
......@@ -459,6 +452,7 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when others =>
s_base_adr <= (others => '0');
s_mem_wr_en_p <= '0';
s_jc_mem_wr_en_p <= '0';
......@@ -473,14 +467,14 @@ end process;
---------------------------------------------------------------------------------------------------
-- Control, PDU_TYPE, Length bytes --
-- CTRL, PDU_TYPE, LGTH bytes --
---------------------------------------------------------------------------------------------------
-- Synchronous process Register_Ctrl_PDU_LGTH_bytes: Storage of the Control, PDU_TYPE
-- and Length bytes of an incoming RP_DAT frame. The bytes are sent to the WF_cons_outcome
-- Synchronous process Register_CTRL_PDU_LGTH_bytes: Storage of the CTRL, PDU_TYPE
-- and LGTH bytes of an incoming RP_DAT frame. The bytes are sent to the WF_cons_outcome
-- unit that validates them and accordingly activates the VAR1_RDY (for a var_1),
-- VAR2_RDY (for a var_2), assert_rston_p & rst_nfip_and_fd_p (for a var_rst).
Register_Ctrl_PDU_LGTH_bytes: process (uclk_i)
Register_CTRL_PDU_LGTH_bytes: process (uclk_i)
begin
if rising_edge (uclk_i) then
......@@ -488,6 +482,7 @@ end process;
cons_ctrl_byte_o <= (others => '0');
cons_pdu_byte_o <= (others => '0');
s_cons_lgth_byte <= (others => '0');
else
if (var_i = var_1) or (var_i = var_2) or (var_i = var_rst) or (var_i = var_jc1)then -- only for consumed vars
......@@ -514,6 +509,7 @@ end process;
-- -- -- -- -- -- -- -- -- -- -- --
cons_lgth_byte_o <= s_cons_lgth_byte;
end architecture rtl;
--=================================================================================================
-- architecture end
......
wf_cons_outcome.vhd
View file @ caddc235
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- --
-- WF_cons_outcome --
-- --
-- |
-- WF_cons_outcome |
-- |
---------------------------------------------------------------------------------------------------
-- File WF_cons_outcome.vhd
--
-- Description The unit starts by validating a consumed RP_DAT frame with respect to the
-- correctness of:
-- o the Control, PDU_TYPE and Length bytes; the bytes are received from the
-- WF_consumption unit.
-- o the CRC, FSS & FES bytes; the rx_fss_crc_fes_ok_p_i pulse from the
-- WF_fd_receiver unit groups these checks.
--
-- Then, according to the consumed variable that has been received (var_1, var_2,
-- var_rst) it generates the signals:
-- o "nanoFIP User Interface, NON_WISHBONE" output signals VAR1_RDY and VAR2_RDY.
-- o "nanoFIP User Interface, NON_WISHBONE" output signal r_tler_o, also used by
-- the WF_status_bytes_generator unit (nanoFIP status byte, bit 4).
-- o rst_nFIP_and_FD_p and assert_RSTON_p, that are inputs to the WF_reset_unit.
--
--
-- Note: The Length byte is considered "correct" if it is coherent with the actual
-- number of bytes received in the frame and also respects the frame limits.
--
-- Reminder:
--
-- Consumed RP_DAT frame structure :
-- ___________ ______ _______ ______ _________________________ _______ ___________ _______
-- |____FSS____|_Ctrl_||__PDU__|_LGTH_|_____..Applic-Data.._____|__MPS__||____FCS____|__FES__|
--
-- |-----------&LGTH bytes-----------|
-- >0 and <128
--
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
-- Date 22/02/2011
-- Version v0.05
-- Depends on WF_reset_unit
-- WF_engine_control
-- WF_fd_receiver
-- WF_consumption
----------------
-- Last changes
-- 10/2010 v0.01 EG First version
-- 11/2010 v0.02 EG Treatment of reset vars added to the unit
-- Correction on var1_rdy, var2_rdy for slone
-- 12/2010 v0.03 EG Finally no broadcast in slone, cleanning-up+commenting
-- 01/2010 v0.04 EG Unit WF_var_rdy_generator separated in WF_cons_outcome
-- (for var1_rdy,var2_rdy+var_rst outcome) & WF_prod_permit (for var3)
-- 02/2010 v0.05 EG Added here functionality of wf_cons_frame_validator
-- Bug on var1_rdy, var2_rdy generation corrected (the s_varX_received
-- was always set to 1!)
-- Added check of Ctrl byte for rtler
-- Added cons_bytes_excess_i for tracking of too long RP_DATs
-- File WF_cons_outcome.vhd |
-- |
-- Description The unit starts by validating a consumed RP_DAT frame with respect to the |
-- correctness of: |
-- o the CTRL, PDU_TYPE and LGTH bytes; these bytes are received from the |
-- WF_consumption unit. |
-- o the CRC, FSS & FES bytes; the rx_fss_crc_fes_ok_p_i pulse from the |
-- WF_fd_receiver unit groups these checks. |
-- |
-- Then, according to the consumed variable that has been received (var_1, var_2, |
-- var_rst, var_jc1) it generates the signals: |
-- o "nanoFIP User Interface, NON_WISHBONE" output signals VAR1_RDY and VAR2_RDY. |
-- o "nanoFIP User Interface, NON_WISHBONE" output signal r_tler_o, also used by |
-- the WF_status_bytes_generator unit (nanoFIP status byte, bit 4). |
-- o rst_nFIP_and_FD_p and assert_RSTON_p, that are inputs to the WF_reset_unit. |
-- o jc_start_p that triggers the start-up of thr WF_jtag_controller unit. |
-- |
-- |
-- Reminder: |
-- |
-- Consumed RP_DAT frame structure : |
-- ___________ ______ _______ ______ _________________________ _______ ___________ _______ |
-- |____FSS____|_CTRL_||__PDU__|_LGTH_|_____..Applic-Data.._____|__MPS__||____FCS____|__FES__| |
-- |
-- |-----------&LGTH bytes-----------| |
-- |---------- >0 and <128 ----------| |
-- |--------------------------&byte_index_i bytes--------------------------------| |
-- |
-- The LGTH byte is considered correct if it is coherent with the actual number of |
-- bytes received in the frame and also respects the frame limits. |
-- |
-- |
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 06/2011 |
-- Version v0.06 |
-- Depends on WF_reset_unit |
-- WF_engine_control |
-- WF_fd_receiver |
-- WF_consumption |
---------------- |
-- Last changes |
-- 10/2010 v0.01 EG First version |
-- 11/2010 v0.02 EG Treatment of reset vars added to the unit |
-- Correction on var1_rdy, var2_rdy for slone |
-- 12/2010 v0.03 EG Finally no broadcast in slone, cleanning-up+commenting |
-- 01/2011 v0.04 EG Unit WF_var_rdy_generator separated in WF_cons_outcome |
-- (for var1_rdy,var2_rdy+var_rst outcome) & WF_prod_permit (for var3) |
-- 02/2011 v0.05 EG Added here functionality of wf_cons_frame_validator |
-- Bug on var1_rdy, var2_rdy generation corrected (the s_varX_received |
-- was always set to 1!) |
-- Added check of CTRL byte for rtler |
-- Added cons_bytes_excess_i for tracking of too long RP_DATs |
-- 06/2011 v0.06 EG added var_jc1 treatment |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
......@@ -94,9 +98,7 @@ use work.WF_PACKAGE.all; -- definitions of types, constants, entities
-- Entity declaration for WF_cons_outcome
--=================================================================================================
entity WF_cons_outcome is
port (
entity WF_cons_outcome is port(
-- INPUTS
-- nanoFIP User Interface, General signals
uclk_i : in std_logic; -- 40 MHz clock
......@@ -116,8 +118,8 @@ entity WF_cons_outcome is
-- pulse upon FES detection
-- Signals from the WF_consumption unit
cons_ctrl_byte_i : in std_logic_vector (7 downto 0); -- received RP_DAT Control byte
cons_lgth_byte_i : in std_logic_vector (7 downto 0); -- received RP_DAT Length byte
cons_ctrl_byte_i : in std_logic_vector (7 downto 0); -- received RP_DAT CTRL byte
cons_lgth_byte_i : in std_logic_vector (7 downto 0); -- received RP_DAT LGTH byte
cons_pdu_byte_i : in std_logic_vector (7 downto 0); -- received RP_DAT PDU_TYPE byte
cons_var_rst_byte_1_i : in std_logic_vector (7 downto 0); -- received var_rst RP_DAT, 1st data-byte
cons_var_rst_byte_2_i : in std_logic_vector (7 downto 0); -- received var_rst RP_DAT, 2nd data-byte
......@@ -134,10 +136,10 @@ entity WF_cons_outcome is
var2_rdy_o : out std_logic; -- signals new data is received and can safely be read
-- Signal to the WF_jtag_controller unit
jc_start_p_o : out std_logic;
jc_start_p_o : out std_logic; -- pulse upon the end of a new correct jc_var1
-- Signal to the WF_status_bytes_gen unit
nfip_status_r_tler_p_o : out std_logic; -- received PDU_TYPE or Length error
nfip_status_r_tler_p_o : out std_logic; -- received PDU_TYPE or LGTH error
-- nanoFIP status byte bit 4
-- Signals to the WF_reset_unit
......@@ -145,10 +147,9 @@ entity WF_cons_outcome is
-- containing the station's address has been
-- correctly received
rst_nfip_and_fd_p_o : out std_logic -- indicates that a var_rst with its 1st data-byte
rst_nfip_and_fd_p_o : out std_logic);-- indicates that a var_rst with its 1st data-byte
-- containing the station's address has been
-- correctly received
);
end entity WF_cons_outcome;
......@@ -160,6 +161,7 @@ architecture rtl of WF_cons_outcome is
signal s_cons_frame_ok_p : std_logic;
signal s_rst_nfip_and_fd, s_assert_rston : std_logic;
--=================================================================================================
-- architecture begin
--=================================================================================================
......@@ -167,20 +169,25 @@ begin
---------------------------------------------------------------------------------------------------
-- Consumed RP_DAT frame Validation --
---------------------------------------------------------------------------------------------------
-- Sequential process Frame_Validation: validation of a consumed RP_DAT frame, with
-- respect to the Ctrl, PDU_TYPE and Length bytes as well as to the CRC, FSS & FES.
-- respect to the CTRL, PDU_TYPE and LGTH bytes as well as to the CRC, FSS & FES.
-- The bytes cons_ctrl_byte_i, cons_pdu_byte_i, cons_lgth_byte_i that
-- arrive at the beginning of a frame, have been registered and keep their values until the end
-- of it. The signal rx_fss_crc_fes_ok_p_i, is a pulse at the end of the FES that combines
-- the checks of the FSS, CRC & FES.
-- To check the correctness of the the RP_DAT.Data.Length byte, we compare it to the value of the
-- rx_byte_index, when the FES is detected (pulse rx_fss_crc_fes_ok_p_i).
-- Note: In addition to the &Length bytes, the rx_byte_index also counts the Control, PDU_TYPE,
-- Length, the 2 CRC and the FES bytes (and counting starts from 0!).
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- To check the correctness of the the RP_DAT.Data.LGTH byte, we compare it to the value of the
-- bytes counter byte_index_i, when the FES is detected (pulse rx_fss_crc_fes_ok_p_i).
-- Note: Upon FES detection the counter byte_index_i should be equal to &cons_lgth_byte_i + 5.
-- The byte_index_i includes the counting of the the CTRL, PDU_TYPE, LGTH, the 2 CRC and
-- the bytes (and counting starts from 0!).
-- The same process is also used for the generation of the of the nanoFIP status byte, bit 4, that
-- indicates a received Control or PDU_TYPE byte error or a Length byte incoherency in a consumed
-- RP_DAT frame.
-- indicates a received CTRL or PDU_TYPE byte error or a LGTH byte incoherency.
-- Note: The end of a frame is marked by either the signal rx_fss_crc_fes_ok_p_i or by the
-- rx_crc_wrong_p_i.
......@@ -206,7 +213,7 @@ begin
(cons_pdu_byte_i = c_PDU_TYPE_BYTE) and -- PDU_TYPE byte check
(unsigned(byte_index_i ) = (unsigned(cons_lgth_byte_i) + 5)) then --LGTH byte check
(unsigned(byte_index_i ) = (unsigned(cons_lgth_byte_i) + 5)) then -- LGTH byte check
s_cons_frame_ok_p <= '1';
else
......@@ -214,9 +221,9 @@ begin
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
if (cons_bytes_excess_i = '1') or -- excess of bytes(without FES detection)
if (cons_bytes_excess_i = '1') or -- excess of bytes (without FES detection)
(((rx_fss_crc_fes_ok_p_i = '1') or (rx_crc_wrong_p_i = '1')) and -- upon FES detection
(((rx_fss_crc_fes_ok_p_i = '1') or (rx_crc_wrong_p_i = '1')) and -- upon FES detection checking of CTRL, PDU_TUPE, LGTH
((not ((cons_ctrl_byte_i(5 downto 0) = c_RP_DAT_CTRL_BYTE) or -- CTRL byte check
(cons_ctrl_byte_i(5 downto 0) = c_RP_DAT_MSG_CTRL_BYTE) or
......@@ -242,6 +249,9 @@ begin
---------------------------------------------------------------------------------------------------
-- var_3: VAR_RDY_Generation --
---------------------------------------------------------------------------------------------------
-- Synchronous process VAR_RDY_Generation:
-- Memory Mode:
......@@ -250,13 +260,13 @@ begin
-- consumed var is being received the user can read from the consumed broadcast memory.
-- VAR1_RDY (for consumed vars) : signals that the user can safely read from the
-- consumed memory. The signal is asserted only after the reception of a correct RP_DAT frame.
-- It is de-asserted after the reception of a correct var_1 ID_DAT frame.
-- consumed memory. The signal is asserted only after the reception of a correct var_1 RP_DAT
-- frame. It is de-asserted after the reception of a correct var_1 ID_DAT frame.
-- VAR2_RDY (for broadcast consumed vars): signals that the user can safely read from the
-- consumed broadcast memory. The signal is asserted only after the reception of a correct
-- consumed broadcast RP_DAT frame. It is de-asserted after the reception of a correct var_2
-- ID_DAT frame.
-- consumed broadcast var_2 RP_DAT frame. It is de-asserted after the reception of a correct
-- var_2 ID_DAT frame.
-- Stand-alone Mode:
......@@ -264,8 +274,8 @@ begin
-- bytes are independent. Stand-alone mode though does not treat the consumed broadcast variable.
-- VAR1_RDY (for consumed vars) : signals that the user can safely retrieve data from
-- the DAT_O bus. The signal is asserted only after the reception of a correct RP_DAT frame.
-- It is de-asserted after the reception of a correct var_1 ID_DAT frame(same as in memory mode).
-- the DAT_O bus. The signal is asserted only after the reception of a correct var_1 RP_DAT frame.
-- It is de-asserted after the reception of a correct var_1 ID_DAT frame (same as in memory mode).
-- VAR2_RDY (for broadcast consumed vars): stays always deasserted.
......@@ -273,12 +283,12 @@ begin
-- FES detection. A correct ID_DAT frame along with the variable it contained is signaled by the
-- var_i. The signal var_i gets its value (var_1, var_2, var_rst) after the reception of a correct
-- ID_DAT and of a correct RP_DAT FSS; var_i retains its value until the FES detectionon of the
-- RP_DAT frame.
-- RP_DAT frame. An example follows:
--
-- frames : ___[ID_DAT,var_1]__[......RP_DAT......]______________[ID_DAT,var_1]___[.....RP_DAT..
-- cons_frame_ok_p : ______________________________________|-|___________________________________________
-- var_i : var_whatever > < var_1 > < var_whatever > < var_1
-- VAR1_RDY : ________________________________________|-------------------------------|___________
-- var_i : var_whatever > < var_1 > < var_whatever > < var_1
-- VAR1_RDY : ______________________________________|--------------------------------|____________
VAR_RDY_Generation: process (uclk_i)
begin
......@@ -316,17 +326,6 @@ begin
var2_rdy_o <= '0'; -- while consuming a var_2, VAR2_RDY is 0
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- JTAG_controller -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
if (var_i = var_jc1) and (s_cons_frame_ok_p = '1') then
jc_start_p_o <= '1';
else
jc_start_p_o <= '0';
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
end if;
end if;
......@@ -335,6 +334,9 @@ begin
---------------------------------------------------------------------------------------------------
-- var_rst: Reset Signals Generation --
---------------------------------------------------------------------------------------------------
-- Generation of the signals rst_nfip_and_fd : signals that the 1st byte of a consumed
-- var_rst contains the station address
-- and assert_rston : signals that the 2nd byte of a consumed
......@@ -371,12 +373,36 @@ begin
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
rst_nfip_and_fd_p_o <= '1' when s_rst_nfip_and_fd = '1' and s_cons_frame_ok_p = '1'
else '0';
rst_nfip_and_fd_p_o <= '1' when s_rst_nfip_and_fd = '1' and s_cons_frame_ok_p = '1' else '0';
assert_rston_p_o <= '1' when s_assert_rston = '1' and s_cons_frame_ok_p = '1' else '0';
---------------------------------------------------------------------------------------------------
-- var_jc3: JTAG_contoller startup signal --
---------------------------------------------------------------------------------------------------
-- Generation of the signal jc_start_p_o that is a 1 uclk-long pulse after the reception of a
-- valid var_jc1. The pulse triggers the startup of the WF_jtag_controller state machine.
jc_start_p_generation: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
jc_start_p_o <= '0';
else
if (var_i = var_jc1) and (s_cons_frame_ok_p = '1') then
jc_start_p_o <= '1';
assert_rston_p_o <= '1' when s_assert_rston = '1' and s_cons_frame_ok_p = '1'
else '0';
else
jc_start_p_o <= '0';
end if;
end if;
end if;
end process;
end architecture rtl;
......
wf_consumption.vhd
View file @ caddc235
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- --
-- WF_consumption --
-- --
-- |
-- WF_consumption |
-- |
---------------------------------------------------------------------------------------------------
-- File WF_consumption.vhd
--
-- Description The unit groups the main actions that regard data consumption.
-- It instantiates the units:
--
-- o WF_cons_bytes_processor : for the handling of consumed RP_DAT data bytes as they
-- arrive from the WF_fd_receiver (registration to the RAM
-- or outputting to the DAT_O).
--
--
-- o WF_cons_outcome : for the validation of the consumed frame at the end of
-- its arrival (in terms of FSS, Ctrl, PDU_TYPE, Lgth &
-- CRC bytes) and the generation of the
-- "nanoFIP User Interface,NON-WISHBONE" outputs VAR1_RDY
-- and VAR2_RDY (for var_1, var_2) or of the internal
-- signals for the nanoFIP and the FIELDRIVE resets (var_rst).
--
-- ___________________________________________________________
-- | WF_consumption |
-- | |
-- | _____________________________________________ |
-- | | | |
-- | | WF_cons_outcome | |
-- | | | |
-- | |_____________________________________________| |
-- | |
-- | _____________________________________________ |
-- | | | |
-- | | WF_cons_bytes_processor | |
-- | | | |
-- | |_____________________________________________| |
-- |___________________________________________________________|
-- /\
-- ___________________________________________________________
-- | |
-- | WF_fd_receiver |
-- |___________________________________________________________|
-- /\
-- ___________________________________________________________________
-- 0_____________________________FIELDBUS______________________________O
--
--
-- Note : In the entity declaration of this unit, below each input signal, we mark
-- for which of the instantiated units it is essential.
--
--
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
-- Date 11/01/2011
-- Version v0.01
-- Depends on WF_reset_unit
-- WF_fd_receiver
-- WF_engine_control
----------------
-- Last changes
-- 01/2011 EG v0.01 first version
-- File WF_consumption.vhd |
-- |
-- Description The unit groups the main actions that regard data consumption. |
-- It instantiates the units: |
-- |
-- o WF_cons_bytes_processor: for the handling of consumed RP_DAT data bytes as they |
-- arrive from the WF_fd_receiver (registration to the |
-- RAM or outputting to the DAT_O). |
-- |
-- |
-- o WF_cons_outcome : for the validation of the consumed frame at the end of |
-- its arrival (in terms of FSS, CTRL, PDU_TYPE, Lgth & |
-- CRC bytes). |
-- |
-- ___________________________________________________________ |
-- | WF_consumption | |
-- | | |
-- | _____________________________________________ | |
-- | | | | |
-- | | WF_cons_outcome | | |
-- | | | | |
-- | |_____________________________________________| | |
-- | | |
-- | _____________________________________________ | |
-- | | | | |
-- | | WF_cons_bytes_processor | | |
-- | | | | |
-- | |_____________________________________________| | |
-- |___________________________________________________________| |
-- /\ |
-- ___________________________________________________________ |
-- | | |
-- | WF_fd_receiver | |
-- |___________________________________________________________| |
-- /\ |
-- ___________________________________________________________________ |
-- O____________________________FIELDBUS______________________________O |
-- |
-- |
-- Note: In the entity declaration of this unit, below each input signal, we mark |
-- for which of the instantiated units it is essential. |
-- |
-- |
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 11/01/2011 |
-- Version v0.01 |
-- Depends on WF_reset_unit |
-- WF_fd_receiver |
-- WF_engine_control |
---------------- |
-- Last changes |
-- 01/2011 EG v0.01 first version |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
......@@ -99,10 +96,9 @@ use work.WF_PACKAGE.all; -- definitions of types, constants, entities
--=================================================================================================
-- Entity declaration for WF_consumption
--=================================================================================================
entity WF_consumption is
port (
entity WF_consumption is port(
-- INPUTS
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- nanoFIP User Interface, General signals
......@@ -113,21 +109,18 @@ entity WF_consumption is
-- used by: WF_cons_bytes_processor for selecting the data storage (RAM or DAT_O bus)
-- used by: WF_cons_outcome for the VAR2_RDY signal (stand-alone mode does not treat var_2)
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- nanoFIP WorldFIP Settings
subs_i : in std_logic_vector (7 downto 0);
-- used by: WF_cons_outcome for checking if the 2 bytes of a var_rst match the station's addr
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Signal from the WF_reset_unit
nfip_rst_i : in std_logic;
-- used by: all the units
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Signals from the WF_fd_receiver
......@@ -139,7 +132,6 @@ entity WF_consumption is
rx_crc_wrong_p_i : in std_logic;
-- used by: WF_cons_outcome
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- nanoFIP User Interface, WISHBONE Slave
......@@ -147,7 +139,6 @@ entity WF_consumption is
wb_adr_i : in std_logic_vector (8 downto 0);
-- used by: WF_cons_bytes_processor for the managment of the Consumption RAM
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Signals from the WF_engine_control unit
......@@ -159,24 +150,21 @@ entity WF_consumption is
byte_index_i : in std_logic_vector (7 downto 0);
-- used by: WF_cons_bytes_processor for the reception coordination
-- used by: WF_cons_outcome for the validation of the Length byte
-- used by: WF_cons_outcome for the validation of the LGTH byte
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Signal from the WF_jtag_controller unit
jc_mem_adr_rd_i : in std_logic_vector (8 downto 0);
-----------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------
-- OUTPUTS
-- nanoFIP User Interface, NON-WISHBONE outputs
var1_rdy_o : out std_logic;
var2_rdy_o : out std_logic;
-- Signals to the WF_jtag_controller
jc_start_p_o : out std_logic;
-- nanoFIP User Interface, WISHBONE Slave outputs
data_o : out std_logic_vector (15 downto 0);
......@@ -188,8 +176,8 @@ entity WF_consumption is
rst_nfip_and_fd_p_o : out std_logic;
-- Signals to the WF_jtag_controller unit
jc_mem_data_o : out std_logic_vector (7 downto 0)
);
jc_start_p_o : out std_logic;
jc_mem_data_o : out std_logic_vector (7 downto 0));
end entity WF_consumption;
......@@ -203,6 +191,7 @@ architecture struc of WF_consumption is
signal s_cons_ctrl_byte, s_cons_pdu_byte, s_cons_lgth_byte : std_logic_vector (7 downto 0);
signal s_cons_var_rst_byte_1, s_cons_var_rst_byte_2 : std_logic_vector (7 downto 0);
--=================================================================================================
-- architecture begin
--=================================================================================================
......@@ -214,25 +203,25 @@ begin
---------------------------------------------------------------------------------------------------
Consumption_Bytes_Processor : WF_cons_bytes_processor
port map (
uclk_i => uclk_i,
nfip_rst_i => nfip_rst_i,
slone_i => slone_i,
byte_ready_p_i => rx_byte_ready_p_i,
var_i => var_i,
byte_index_i => byte_index_i,
byte_i => rx_byte_i,
wb_clk_i => wb_clk_i,
wb_adr_i => wb_adr_i,
jc_mem_adr_rd_i => jc_mem_adr_rd_i,
port map(
uclk_i => uclk_i,
nfip_rst_i => nfip_rst_i,
slone_i => slone_i,
byte_ready_p_i => rx_byte_ready_p_i,
var_i => var_i,
byte_index_i => byte_index_i,
byte_i => rx_byte_i,
wb_clk_i => wb_clk_i,
wb_adr_i => wb_adr_i,
jc_mem_adr_rd_i => jc_mem_adr_rd_i,
--------------------------------------------------------
data_o => data_o,
jc_mem_data_o => jc_mem_data_o,
cons_ctrl_byte_o => s_cons_ctrl_byte,
cons_pdu_byte_o => s_cons_pdu_byte,
cons_lgth_byte_o => s_cons_lgth_byte,
cons_var_rst_byte_1_o => s_cons_var_rst_byte_1,
cons_var_rst_byte_2_o => s_cons_var_rst_byte_2);
data_o => data_o,
jc_mem_data_o => jc_mem_data_o,
cons_ctrl_byte_o => s_cons_ctrl_byte,
cons_pdu_byte_o => s_cons_pdu_byte,
cons_lgth_byte_o => s_cons_lgth_byte,
cons_var_rst_byte_1_o => s_cons_var_rst_byte_1,
cons_var_rst_byte_2_o => s_cons_var_rst_byte_2);
--------------------------------------------------------
......@@ -242,7 +231,7 @@ begin
---------------------------------------------------------------------------------------------------
Consumption_Outcome : WF_cons_outcome
port map (
port map(
uclk_i => uclk_i,
slone_i => slone_i,
subs_i => subs_i,
......
wf_crc.vhd
View file @ caddc235
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- --
-- WF_crc --
-- --
-- |
-- WF_crc |
-- |
---------------------------------------------------------------------------------------------------
-- File WF_crc.vhd
-- Description The unit creates the modules for:
-- o the generation of the CRC of serial data,
-- o the verification of an incoming CRC syndrome.
--
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Date 23/02/2011
-- Version v0.04
-- Depends on WF_reset_unit
-- WF_rx_deserializer
-- WF_tx_serializer
----------------
-- Last changes
-- 07/08/2009 v0.02 PAS Entity Ports added, start of architecture content
-- 08/2010 v0.03 EG Data_FCS_select and crc_ready_p_o signals removed,
-- variable v_q_check_mask replaced with a signal,
-- code cleaned-up+commented
-- 02/2011 v0.04 EG s_q_check_mask was not in Syndrome_Verification sensitivity list!
-- xor replaced with if(Syndrome_Verification); processes rewritten;
-- delay on data_bit_ready_p_i removed.
-- File WF_crc.vhd |
-- |
-- Description The unit creates the modules for: |
-- o the generation of the CRC of serial data, |
-- o the verification of an incoming CRC syndrome. |
-- |
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) |
-- Date 23/02/2011 |
-- Version v0.04 |
-- Depends on WF_reset_unit |
-- WF_rx_deserializer |
-- WF_tx_serializer |
---------------- |
-- Last changes |
-- 07/08/2009 v0.02 PAS Entity Ports added, start of architecture content |
-- 08/2010 v0.03 EG Data_FCS_select and crc_ready_p_o signals removed, |
-- variable v_q_check_mask replaced with a signal, |
-- code cleaned-up+commented |
-- 02/2011 v0.04 EG s_q_check_mask was not in Syndrome_Verification sensitivity list! |
-- xor replaced with if(Syndrome_Verification); processes rewritten; |
-- delay on data_bit_ready_p_i removed. |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
......@@ -63,8 +64,7 @@ use work.WF_PACKAGE.all; -- definitions of types, constants, entities
--=================================================================================================
-- Entity declaration for WF_crc
--=================================================================================================
entity WF_crc is
port (
entity WF_crc is port(
-- INPUTS
-- nanoFIP User Interface, General signals
uclk_i : in std_logic; -- 40 MHz clock
......@@ -83,8 +83,7 @@ entity WF_crc is
crc_ok_p_o : out std_logic; -- signals a correct received CRC syndrome
-- Signal to the WF_tx_serializer unit
crc_o : out std_logic_vector (c_CRC_POLY_LGTH-1 downto 0) -- calculated CRC
);
crc_o : out std_logic_vector (c_CRC_POLY_LGTH-1 downto 0)); -- calculated CRC
end entity WF_crc;
......@@ -96,13 +95,17 @@ architecture rtl of WF_crc is
signal s_q, s_q_nx : std_logic_vector (c_CRC_POLY_LGTH - 1 downto 0);
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
---------------------------------------------------------------------------------------------------
-- CRC Calculation --
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- The Gen_16_bit_Register_and_Interconnections generator, follows the scheme of figure A.1
-- of the Annex A 61158-4-7 IEC:2007 and constructs a register of 16 master-slave flip-flops which
-- are interconnected as a linear feedback shift register.
......@@ -116,8 +119,7 @@ begin
end generate;
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Synchronous process CRC_calculation: the process "moves" the shift register described
-- above, for the calculation of the CRC.
......@@ -146,25 +148,18 @@ begin
crc_o <= not s_q;
---------------------------------------------------------------------------------------------------
-- Combinatorial process Syndrome_Verification: On the reception, the CRC is being
-- calculated as data is arriving (same as in the transmission) and it is being compared to the
-- predefined c_CRC_VERIF_POLY. When the CRC calculated from the received data matches the
-- c_CRC_VERIF_POLY, it is implied that a correct CRC word has been received for the preceded
-- data and the signal crc_ok_p_o gives a 1 uclk-wide pulse.
Syndrome_Verification: process (s_q, data_bit_ready_p_i)
begin
if s_q = not c_CRC_VERIF_POLY then
---------------------------------------------------------------------------------------------------
-- CRC Verification --
---------------------------------------------------------------------------------------------------
crc_ok_p_o <= data_bit_ready_p_i;
-- During reception, the CRC is being calculated as data is arriving (same as in the transmission)
-- and it is being compared to the predefined c_CRC_VERIF_POLY. When the CRC calculated from the
-- received data matches the c_CRC_VERIF_POLY, it is implied that a correct CRC word has been
-- received for the preceded data and the signal crc_ok_p_o gives a 1 uclk-wide pulse.
else
crc_ok_p_o <= '0';
crc_ok_p_o <= data_bit_ready_p_i when s_q = not c_CRC_VERIF_POLY else '0';
end if;
end process;
end architecture rtl;
......
wf_decr_counter.vhd
View file @ caddc235
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- --
-- WF_decr_counter --
-- --
-- |
-- WF_decr_counter |
-- |
---------------------------------------------------------------------------------------------------
-- File WF_decr_counter.vhd
-- Description Decreasing counter with synchronous reset, load enable and decrease enable
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
-- Date 10/2010
-- Version v0.01
-- Depends on WF_reset_unit
----------------
-- Last changes
-- 10/2010 EG v0.01 first version
-- File WF_decr_counter.vhd |
-- Description Decreasing counter with synchronous reset, load enable and decrease enable |
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 10/2010 |
-- Version v0.01 |
-- Depends on WF_reset_unit |
---------------- |
-- Last changes |
-- 10/2010 EG v0.01 first version |
-- 10/2010 EG v0.01b initial value after reset is all '1' not all '0' |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
......@@ -55,8 +56,8 @@ use work.WF_PACKAGE.all; -- definitions of types, constants, entities
--=================================================================================================
entity WF_decr_counter is
generic (g_counter_lgth : natural := 4); -- default length
port (
generic(g_counter_lgth : natural := 4); -- default length
port(
-- INPUTS
-- nanoFIP User Interface general signal
uclk_i : in std_logic; -- 40 MHz clock
......@@ -73,8 +74,8 @@ entity WF_decr_counter is
-- OUTPUTS
-- Signal to any unit
counter_o : out unsigned (g_counter_lgth-1 downto 0); -- counter
counter_is_zero_o : out std_logic -- empty counter indication
);
counter_is_zero_o : out std_logic); -- empty counter indication
end entity WF_decr_counter;
......@@ -83,8 +84,8 @@ end entity WF_decr_counter;
--=================================================================================================
architecture rtl of WF_decr_counter is
signal s_counter_is_zero : std_logic;
signal s_counter : unsigned (g_counter_lgth-1 downto 0);
signal s_counter : unsigned (g_counter_lgth-1 downto 0);
--=================================================================================================
-- architecture begin
......@@ -100,7 +101,7 @@ begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
s_counter <= (others => '0');
s_counter <= (others => '1');
else
if counter_load_i = '1' then
......@@ -110,19 +111,14 @@ begin
s_counter <= s_counter - 1;
end if;
counter_is_zero_o <= s_counter_is_zero; -- for slack reasons, especially for the
-- 21 bits "session_timeout" counters
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Concurrent assignments
counter_o <= s_counter;
s_counter_is_zero <= '1' when s_counter = to_unsigned(0,s_counter'length) else '0';
counter_is_zero_o <= '1' when s_counter = to_unsigned(0, s_counter'length) else '0';
end architecture rtl;
......
wf_bits_to_txd.vhd → wf_dualram_512x8_clka_rd_clkb_wr.vhd
View file @ caddc235
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- --
-- WF_bits_to_txd --
-- --
---------------------------------------------------------------------------------------------------
-- File WF_bits_to_txd.vhd
--
-- Description According to the state of the FSM of the WF_tx_serializer, the unit is responsible
-- for putting in nanoFIP's output FD_TXD one by one all the bits required for the
-- formation of the RP_DAT frame (that is: manch. encoded FSS, data, CRC and FES bits).
-- The unit also manages the output FD_TXENA.
--
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
-- Date 07/01/2011
-- Version v0.03
-- Depends on WF_reset_unit
-- WF_tx_osc
-- WF_tx_serializer
----------------
-- Last changes
-- 8/2010 v0.02 EG tx_enable has to be synched with txd! sending_fss not enough;
-- need for tx_sched_p_buff signal
-- 7/1/2011 v0.03 EG tx_enable now starts 1 uclk tick earlier, at the same moment as txd
-- becomes 1 for the 1st bit of preamble
-- signals s_tx_enable & s_start_tx_enable removed for simplification
--
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
--=================================================================================================
-- Libraries & Packages
--=================================================================================================
-- Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific library
library work;
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
--=================================================================================================
-- Entity declaration for WF_bits_to_txd
--=================================================================================================
entity WF_bits_to_txd is
port (
-- INPUTS
-- nanoFIP User Interface, General signals
uclk_i : in std_logic; -- 40 MHz clock
-- Signal from the WF_reset_unit
nfip_rst_i : in std_logic; -- nanoFIP internal reset
-- Signals from the WF_tx_serializer unit
crc_byte_manch_i : in std_logic_vector (31 downto 0); -- manch. encoded CRC bytes to be sent
data_byte_manch_i : in std_logic_vector (15 downto 0); -- manch. encoded data byte to be sent
sending_fss_i : in std_logic; -- WF_tx_serializer FSM states
sending_data_i : in std_logic; -- -------"----"-----"--------
sending_crc_i : in std_logic; -- -------"----"-----"--------
sending_fes_i : in std_logic; -- -------"----"-----"--------
stop_transmission_i : in std_logic; -- -------"----"-----"--------
txd_bit_index_i : in unsigned(4 downto 0); -- index of a bit inside a byte
-- Signals from the WF_tx_osc unit
tx_clk_p_i : in std_logic; --clk for transmission synchronization
-- OUTPUTS
-- nanoFIP FIELDRIVE outputs
txd_o : out std_logic; -- FD_TXD
tx_enable_o : out std_logic -- FD_TXENA
);
end entity WF_bits_to_txd;
--=================================================================================================
-- architecture declaration
--=================================================================================================
architecture rtl of WF_bits_to_txd is
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
---------------------------------------------------------------------------------------------------
-- Synchronous process Bits_Delivery: handling of nanoFIP output signal FD_TXD by
-- placing bits of data according to the state of WF_tx_serializer's state machine (sending_fss,
-- sending_data, sending_crc, sending_fes, stop_transmission) and to the counter txd_bit_index.
-- The delivery is synchronised by the tx_sched_p_buff(1) signal.
Bits_Delivery: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
txd_o <= '0';
else
if tx_clk_p_i = '1' then
if sending_fss_i = '1' then
txd_o <= c_FSS (to_integer (txd_bit_index_i)); -- FSS: 2 bytes long (no need to resize)
elsif sending_data_i = '1' then
txd_o <= data_byte_manch_i (to_integer (resize(txd_bit_index_i, 4))); -- 1 data-byte
elsif sending_crc_i = '1' then
txd_o <= crc_byte_manch_i (to_integer (txd_bit_index_i)); -- CRC: 2 bytes long
elsif sending_fes_i = '1' then
txd_o <= c_FES(to_integer (resize(txd_bit_index_i,4))); -- FES: 1 byte
else
txd_o <= '0';
end if;
end if;
end if;
end if;
end process;
---------------------------------------------------------------------------------------------------
-- Synchronous process FD_TXENA_Generator: The nanoFIP output FD_TXENA is activated at the
-- same moment as the first bit of the PRE starts being delivered and stays asserted until the
-- end of the delivery of the last FES bit.
FD_TXENA_Generator: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
tx_enable_o <= '0';
else
if ((sending_fss_i = '1') or (sending_data_i = '1') or -- tx sending bits
(sending_crc_i = '1') or (sending_fes_i = '1') or (stop_transmission_i = '1')) then
if tx_clk_p_i = '1' then -- in order to synchronise the
tx_enable_o <= '1'; -- activation of tx_enable with the
end if; -- the delivery of the 1st FSS bit
-- FD_TXD (FSS) :________|-----|___________|--------
-- tx_sched_p_buff(1):______|-|___|-|___|-|___|-|___|-|__
-- sending_FSS :___|-------------------------------
-- FD_TXENA :________|--------------------------
else
tx_enable_o <= '0';
end if;
end if;
end if;
end process;
end architecture rtl;
--=================================================================================================
-- architecture end
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- |
-- WF_dualram_512x8_clka_rd_clkb_wr |
-- |
---------------------------------------------------------------------------------------------------
-- File WF_dualram_512x8_clka_rd_clkb_wr.vhd |
-- |
-- Description The unit takes the complete dual port 512x8 memory and disables writing from one |
-- side and reading from the other. Finally from port A only reading is possible |
-- and from port B only writing. |
-- Commented in the unit is the memory triplication. Precision RadTol makes the |
-- triplication automatically; in Synplify the comments have to be removed. With the |
-- triplication each incoming byte is written at the same position in the three |
-- memories, whereas each outgoing one is the outcome of a majority voter. |
-- |
-- |
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 10/12/2010 |
-- Version v0.02 |
-- Depends on dualram_512x8.vhd |
---------------- |
-- Last changes |
-- 12/2010 v0.02 EG code cleaned-up+commented |
-- 11/2011 v0.03 EG removed generics! addr+data lgth already defined at the |
-- dualram_512x8 |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
--=================================================================================================
-- Libraries & Packages
--=================================================================================================
-- Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific library
library work;
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
--=================================================================================================
-- Entity declaration for WF_dualram_512x8_clka_rd_clkb_wr
--=================================================================================================
entity WF_dualram_512x8_clka_rd_clkb_wr is port(
-- INPUTS
-- Inputs concerning port A
clk_porta_i : in std_logic;
addr_porta_i : in std_logic_vector (8 downto 0);
-- Inputs concerning port B
clk_portb_i : in std_logic;
addr_portb_i : in std_logic_vector (8 downto 0);
data_portb_i : in std_logic_vector (7 downto 0);
write_en_portb_i : in std_logic;
-- OUTPUT
-- Output concerning port A
data_porta_o : out std_logic_vector (7 downto 0));
end WF_dualram_512x8_clka_rd_clkb_wr;
--=================================================================================================
-- architecture declaration
--=================================================================================================
architecture syn of WF_dualram_512x8_clka_rd_clkb_wr is
signal s_one, s_rwB : std_logic;
signal s_zeros : std_logic_vector (7 downto 0);
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
s_one <= '1';
s_zeros <= (others => '0');
s_rwB <= not write_en_portb_i;
---------------------------------------------------------------------------------------------------
-- Port A used for reading only, port B for writing only.
-- for triplication: G_memory_triplication: for I in 0 to 2 generate
DualRam : dualram_512x8
port map(
DINA => s_zeros,
ADDRA => addr_porta_i,
RWA => s_one,
CLKA => clk_porta_i,
DINB => data_portb_i,
ADDRB => addr_portb_i,
RWB => s_rwB,
CLKB => clk_portb_i,
RESETn => s_one,
DOUTA => data_porta_o, -- for triplication: s_data_o_A_array(I)
DOUTB => open);
-- end generate;
---------------------------------------------------------------------------------------------------
-- for triplication: Combinatorial Majority_Voter
-- for triplication: Majority_Voter: data_porta_o <= (s_data_o_A_array(0) and s_data_o_A_array(1)) or
-- (s_data_o_A_array(1) and s_data_o_A_array(2)) or
-- (s_data_o_A_array(2) and s_data_o_A_array(0));
end syn;
--=================================================================================================
-- architecture end
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
---------------------------------------------------------------------------------------------------
\ No newline at end of file
wf_engine_control.vhd
View file @ caddc235
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- --
-- WF_engine_control --
-- --
-- |
-- WF_engine_control |
-- |
---------------------------------------------------------------------------------------------------
-- File WF_engine_control.vhd
--
-- Description The WF_engine_control is following the reception of an incoming ID_DAT frame and
-- o identifies the variable to be treated
-- o signals accordingly the WF_production and WF_consumption units.
-- During the production or consumption the unit is keeping track of the amounts of
-- produced and consumed bytes.
--
--
-- Reminder:
--
-- ID_DAT frame structure :
-- ___________ ______ _______ ______ ___________ _______
-- |____FSS____|_Ctrl_||__Var__|_SUBS_||____FCS____|__FES__|
--
--
-- Produced RP_DAT frame structure :
-- ___________ ______ _______ ______ _________________ _______ _______ ___________ _______
-- |____FSS____|_Ctrl_||__PDU__|_LGTH_|__..User-Data..__|_nstat_|__MPS__||____FCS____|__FES__|
--
--
-- Consumed RP_DAT frame structure :
-- ___________ ______ _______ ______ _________________________ _______ ___________ _______
-- |____FSS____|_Ctrl_||__PDU__|_LGTH_|_____..Applic-Data.._____|__MPS__||____FCS____|__FES__|
--
--
-- Turnaround time : Time between the end of the reception of an ID_DAT frame
-- requesting for a variable to be produced and the starting of the delivery of a
-- produced RP_DAT frame.
--
-- Silence time : Maximum time that nanoFIP waits for a consumed RP_DAT frame after
-- the reception of an ID_DAT frame indicating a variable to be consumed.
--
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch),
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
-- Date 15/01/2011
-- Version v0.06
-- Depends on WF_reset_unit
-- WF_fd_transmitter
-- WF_fd_receiver
----------------
-- Last changes
-- 07/2009 v0.01 EB First version
-- 08/2010 v0.02 EG E0 added as broadcast
-- PDU,length,ctrl bytes of RP_DAT checked bf VAR1_RDY/ var_2_rdy assertion;
-- if ID_DAT>8 bytes or RP_DAT>133 (bf reception of a FES) go to idle;
-- state consume_wait_FSS, for the correct use of the silence time(time
-- stops counting when an RP_DAT frame has started)
-- 12/2010 v0.03 EG state machine rewritten moore style; removed check on slone mode
-- for #bytes>4; in slone no broadcast
-- 01/2011 v0.04 EG signals named according to their origin; signals var_rdy (1,2,3),
-- assert_rston_p_o,rst_nfip_and_fd_p_o, nFIP status bits and
-- rx_byte_ready_p_o removed cleaning-up+commenting
-- 02/2011 v0.05 EG Independant timeout counter added; time counter 18 digits instead of 15
-- id_dat_frame_ok: corrected mistake if rx_fss_crc_fes_ok_p not
-- activated; rx reset during production (rx_rst_o);
-- cons_bytes_excess_o added
-- tx_completed_p_i added (bf for the engine ctrl production was finished
-- after the delivery of the last data byte (MPS))
-- 07/2011 v0.06 EG rst_rx state added
-- File WF_engine_control.vhd |
-- |
-- Description The WF_engine_control is following the reception of an incoming ID_DAT frame and |
-- o identifies the variable to be treated |
-- o signals accordingly the WF_production or WF_consumption units. |
-- |
-- Reminder: |
-- |
-- ID_DAT frame structure: |
-- ___________ ______ _______ ______ ___________ _______ |
-- |____FSS____|_CTRL_||__Var__|_SUBS_||____FCS____|__FES__| |
-- |
-- |
-- Produced RP_DAT frame structure: |
-- ___________ ______ _______ ______ _________________ _______ _______ ___________ _______ |
-- |____FSS____|_CTRL_||__PDU__|_LGTH_|__..User-Data..__|_nstat_|__MPS__||____FCS____|__FES__| |
-- |
-- |
-- Consumed RP_DAT frame structure: |
-- ___________ ______ _______ ______ _________________________ _______ ___________ _______ |
-- |____FSS____|_CTRL_||__PDU__|_LGTH_|_____..Applic-Data.._____|__MPS__||____FCS____|__FES__| |
-- |
-- |
-- Turnaround time: Time between the end of the reception of an ID_DAT frame |
-- requesting for a variable to be produced and the starting of the delivery of a |
-- produced RP_DAT frame. |
-- |
-- Silence time : Maximum time that nanoFIP waits for a consumed RP_DAT frame |
-- after the reception of an ID_DAT frame indicating a variable to be consumed. |
-- |
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 15/01/2011 |
-- Version v0.06 |
-- Depends on WF_reset_unit |
-- WF_fd_transmitter |
-- WF_fd_receiver |
---------------- |
-- Last changes |
-- 07/2009 v0.01 EB First version |
-- 08/2010 v0.02 EG E0 added as broadcast |
-- PDU,LGTH,CTRL bytes of RP_DAT checked bf VAR1_RDY/var_2_rdy assertion; |
-- if ID_DAT>8 bytes or RP_DAT>133 (bf reception of a FES) go to idle; |
-- state consume_wait_FSS, for the correct use of the silence time(time |
-- stops counting when an RP_DAT frame has started) |
-- 12/2010 v0.03 EG state machine rewritten moore style; removed check on slone mode |
-- for #bytes>4; in slone no broadcast |
-- 01/2011 v0.04 EG signals named according to their origin; signals var_rdy (1,2,3), |
-- assert_rston_p_o,rst_nfip_and_fd_p_o, nFIP status bits and |
-- rx_byte_ready_p_o removed cleaning-up+commenting |
-- 02/2011 v0.05 EG Independant timeout counter added; time counter 18 digits instead of 15|
-- id_dat_frame_ok: corrected mistake if rx_fss_crc_fes_ok_p not |
-- activated; rx reset during production (rx_rst_o); |
-- cons_bytes_excess_o added |
-- tx_completed_p_i added (bf for the engine ctrl production was finished |
-- after the delivery of the last data byte (MPS)) |
-- 07/2011 v0.06 EG rst_rx state added |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
......@@ -103,8 +100,7 @@ use work.WF_PACKAGE.all; -- definitions of types, constants, entities
--=================================================================================================
-- Entity declaration for WF_engine_control
--=================================================================================================
entity WF_engine_control is
port (
entity WF_engine_control is port(
-- INPUTS
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- nanoFIP User Interface, General signals
......@@ -167,7 +163,7 @@ entity WF_engine_control is
rx_rst_o : out std_logic; -- reset during production or
-- reset pulse when during reception a frame is rejected
-- (example: ID_DAT > 8 bytes, RP_DAT > 133 bytes,
-- wrong ID_DAT Ctrl, variable, subs bytes)
-- wrong ID_DAT CTRL, variable, subs bytes)
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Signal to the WF_consumption unit
......@@ -176,14 +172,15 @@ entity WF_engine_control is
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Signals to the WF_production & WF_consumption
prod_cons_byte_index_o : out std_logic_vector (7 downto 0); -- index of the byte being
-- consumed/ produced
prod_byte_index_o : out std_logic_vector (7 downto 0); -- index of the byte being
-- produced
cons_byte_index_o : out std_logic_vector (7 downto 0); -- index of the byte being
-- consumed
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Signals to the WF_production, WF_consumption, WF_reset_unit
var_o : out t_var -- variable received by a valid ID_DAT frame
var_o : out t_var); -- variable received by a valid ID_DAT frame
-- that concerns this station
);
end entity WF_engine_control;
......@@ -193,31 +190,34 @@ end entity WF_engine_control;
--=================================================================================================
architecture rtl of WF_engine_control is
-- FSM
type control_st_t is (idle,
id_dat_control_byte, id_dat_var_byte, id_dat_subs_byte, id_dat_frame_ok,
consume_wait_FSS, consume, rst_rx,
produce_wait_turnar_time, produce);
signal control_st, nx_control_st : control_st_t;
signal s_idle_state, s_id_dat_ctrl_byte, s_id_dat_var_byte, s_id_dat_frame_ok : std_logic;
signal s_cons_wait_FSS, s_consuming, s_rst_rx_p : std_logic;
signal s_prod_wait_turnar_time, s_producing : std_logic;
-- variable identification
signal s_var_aux, s_var : t_var;
signal s_var_identified : std_logic;
signal s_var_identified, s_broadcast_var : std_logic;
signal s_prod_or_cons : std_logic_vector (1 downto 0);
-- time counters (turnaround, silence, timeout)
signal s_time_c_top, s_turnaround_time, s_silence_time : unsigned (17 downto 0);
signal s_time_c_load, s_time_c_is_zero : std_logic;
signal s_session_timedout : std_logic;
-- received & produced byte counters
signal s_rx_bytes_c, s_prod_bytes_c : unsigned (7 downto 0);
signal s_rx_byte_index, s_prod_byte_index : std_logic_vector (7 downto 0);
signal s_prod_bytes_c_rst, s_prod_bytes_c_inc : std_logic;
signal s_rx_bytes_c_rst, s_rx_bytes_c_inc : std_logic;
-- transmitter controls
signal s_tx_start_prod_p, s_tx_byte_request_accept_p, s_tx_byte_request_accept_p_d1 : std_logic;
signal s_tx_byte_request_accept_p_d2, s_tx_last_data_byte_p, s_tx_last_data_byte_p_d : std_logic;
-- length of produced data calculations
signal s_prod_data_lgth : std_logic_vector (7 downto 0);
signal s_prod_data_lgth_match : std_logic;
signal s_broadcast_var : std_logic;
signal s_prod_or_cons : std_logic_vector (1 downto 0);
--=================================================================================================
-- architecture begin
......@@ -235,20 +235,29 @@ begin
-- The FSM stays in idle until the reception of a FSS from the WF_fd_receiver.
-- It continues by checking one by one the bytes of the frame as they arrive:
-- o if the Control byte corresponds to an ID_DAT,
-- o if the CTRL byte corresponds to an ID_DAT,
-- o if the variable byte corresponds to a defined variable,
-- o if the subscriber byte matches the station's address, or if the variable is a broadcast
-- o and if the frame finishes with a correct CRC and FES.
-- If any of the bytes above has been different than the expected, the FSM goes back to idle after
-- resetting the WF_fd_receiver.
-- If the ID_DAT frame has been correct and the received variable is a produced (var_presence,
-- var_identif, var_3, var_jc3) the FSM stays in the "produce_wait_turnar_time" state until the
-- expiration of the turnaround time and then jumps to the "produce" state, waiting for the
-- WF_fd_serializer to finish the transmission; then it goes back to idle.
-- If the received variable is a consumed (var_1, var_2, var_rst, var_jc1) the FSM stays in the
-- "consume_wait_FSS" state until the arrival of a FSS or the expiration of the silence time.
-- After the arrival of a FSS the FSM jumps to the "consume" state, where it stays until the
-- WF_fd_receiver receives a FES.
-- If any of the bytes above has been different than the expected, the FSM resets the WF_fd_receiver
-- and goes back to idle.
-- o if the ID_DAT frame has been correct and the received variable is a produced (var_presence,
-- var_identif, var_3, var_jc3) the FSM stays in the "produce_wait_turnar_time" state until the
-- expiration of the turnaround time and then jumps to the "produce" state, waiting for the
-- WF_fd_serializer to finish the transmission; then it goes back to idle.
-- o if the received variable is a consumed (var_1, var_2, var_rst, var_jc1) the FSM stays in the
-- "consume_wait_FSS" state until the arrival of a FSS or the expiration of the silence time.
-- After the arrival of the FSS the FSM jumps to the "consume" state, where it stays until the
-- end of the reception of the consumed frame (marked by a FES).
-- Note: In the case of a var_jc3, it is the WF_consumption unit that signals the start-up of
-- the WF_jtag_controller which will work in parallel and independantly from the
-- WF_engine_control; i.e. new frames reception can take place while the
-- WF_jtag_controller is working.
-- To add a rubust layer of protection to the FSM, we have added a counter, dependant only on the
-- system clock, that from any state can bring the FSM back to idle. At any bit rate the
-- reception of an ID_DAT frame followed by the reception/ transmission of an RP_DAT should not
-- last more than 37ms. Hence, we have generated a 21 bits counter that will bring the machine back
-- to idle if more than 52ms (complete 21 bit counter) have passed since it has left this idle state.
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Synchronous process Engine_Control_FSM_Sync: storage of the current state of the FSM
......@@ -298,13 +307,13 @@ begin
nx_control_st <= rst_rx;
elsif (rx_byte_ready_p_i = '1') and (rx_byte_i(5 downto 0) = c_ID_DAT_CTRL_BYTE) then
nx_control_st <= id_dat_var_byte; -- check of ID_DAT Control byte
nx_control_st <= id_dat_var_byte; -- check of ID_DAT CTRL byte
elsif rx_byte_ready_p_i = '1' then
nx_control_st <= rst_rx; -- byte different than the expected ID_DAT Control
nx_control_st <= rst_rx; -- byte different than the expected ID_DAT CTRL
else
nx_control_st <= id_dat_control_byte;-- ID_DAT Control byte being arriving
nx_control_st <= id_dat_control_byte;-- ID_DAT CTRL byte being arriving
end if;
......@@ -332,14 +341,14 @@ begin
nx_control_st <= rst_rx;
elsif (rx_byte_ready_p_i = '1') and ((rx_byte_i = subs_i) or (s_broadcast_var = '1')) then
nx_control_st <= id_dat_frame_ok; -- check of the ID_DAT subscriber
nx_control_st <= id_dat_frame_ok; -- checking of the ID_DAT subscriber
-- or if it is a broadcast variable
-- note: broadcast consumed vars are only treated in
-- memory mode, but at this moment we do not do this
-- check as the var_rst which is broadcast is treated
-- also in stand-alone mode.
elsif rx_byte_ready_p_i = '1' then -- not the station's address, neither a broadcast
elsif rx_byte_ready_p_i = '1' then -- not the station's address, neither a broadcast var
nx_control_st <= rst_rx;
else
......@@ -431,9 +440,9 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when rst_rx =>
nx_control_st <= idle;
when rst_rx => -- the current reception has finished
-- a reset pulse is sent to the WF_receiver
nx_control_st <= idle; -- which will start looking for a new FSS
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
......@@ -613,6 +622,7 @@ begin
s_rst_rx_p <= '0';
s_producing <= '0';
end case;
end process;
......@@ -624,11 +634,13 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Instantiation of the WF_prod_data_lgth_calc unit that calculates the amount of bytes that have
-- to be transmitted when a variable is produced; the RP_DAT.Control, RP_DAT.Data.MPS_status and
-- to be transmitted when a variable is produced; the RP_DAT.CTRL, RP_DAT.Data.MPS_status and
-- RP_DAT.Data.nanoFIP_status bytes are included; The FSS, CRC and FES bytes are not included!
Produced_Data_Length_Calculator: WF_prod_data_lgth_calc
port map (
port map(
uclk_i => uclk_i,
nfip_rst_i => nfip_rst_i,
slone_i => slone_i,
nostat_i => nostat_i,
p3_lgth_i => p3_lgth_i,
......@@ -643,8 +655,8 @@ begin
-- counts bytes following the "tx_byte_request_p_i" pulse in the "produce" state.
Prod_Bytes_Counter: WF_incr_counter
generic map (g_counter_lgth => 8)
port map (
generic map(g_counter_lgth => 8)
port map(
uclk_i => uclk_i,
reinit_counter_i => s_prod_bytes_c_rst,
incr_counter_i => s_prod_bytes_c_inc,
......@@ -654,24 +666,27 @@ begin
-------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- --
s_prod_bytes_c_rst <= '0' when s_producing = '1' else '1';
s_prod_bytes_c_inc <= tx_byte_request_p_i when s_producing = '1' else '0';
-- when s_prod_data_lgth bytes have been counted,the signal s_prod_data_lgth_match is activated
s_prod_data_lgth_match <= '1' when s_prod_bytes_c = unsigned (s_prod_data_lgth) else '0';
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Instantiation of a WF_incr_counter for the counting of the number of bytes that are
-- being received. The same counter is used for the bytes of an ID_DAT frame or a consumed RP_DAT
-- frame (that is why the name of the counter is s_rx_bytes_c and not s_cons_bytes_c!)
-- Regarding an ID_DAT frame : the FSS, Control, var and SUBS bytes are being followed by the
-- Instantiation of a WF_incr_counter for the counting of the number of bytes that are being
-- received. The same counter is used for the bytes of an ID_DAT frame or a consumed RP_DAT
-- frame (hence the name of the counter is s_rx_bytes_c and not s_cons_bytes_c).
-- Regarding an ID_DAT frame: the FSS, CTRL, var and SUBS bytes are being followed by the
-- Engine_Control_FSM; the counter is used for the counting of the bytes from then on and until
-- the arrival of a FES. Therefore, the counter is reset at the "id_dat_subs_byte" state and counts
-- bytes following the "rx_byte_ready_p_i" pulse in the "id_dat_frame_ok" state.
-- Regarding a RP_DAT frame : the counter is reset at the "consume_wait_FSS" state and counts
-- Regarding a RP_DAT frame : the counter is reset at the "consume_wait_FSS" state and counts
-- bytes following the "rx_byte_ready_p_i" pulse in the "consume" state.
Rx_Bytes_Counter: WF_incr_counter
generic map (g_counter_lgth => 8)
port map (
generic map(g_counter_lgth => 8)
port map(
uclk_i => uclk_i,
reinit_counter_i => s_rx_bytes_c_rst,
incr_counter_i => s_rx_bytes_c_inc,
......@@ -680,56 +695,9 @@ begin
counter_o => s_rx_bytes_c);
-------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Combinatorial process Inputs_for_Rx_and_Prod_Byte_Counters: The process gives values to
-- the signals reinit_counter_i and incr_counter_i of the Prod_Bytes_Counter and
-- Rx_Bytes_Counter according to the state of the FSM.
Inputs_for_Rx_and_Prod_Byte_Counters: process (s_id_dat_frame_ok, s_consuming, tx_byte_request_p_i,
s_producing, rx_byte_ready_p_i, s_rx_bytes_c, s_prod_bytes_c)
begin
if s_id_dat_frame_ok = '1' then
s_prod_bytes_c_rst <= '1';
s_prod_bytes_c_inc <= '0';
s_prod_byte_index <= (others => '0');
s_rx_bytes_c_rst <= '0';
s_rx_bytes_c_inc <= rx_byte_ready_p_i;
s_rx_byte_index <= (others => '0');
elsif s_consuming = '1' then
s_prod_bytes_c_rst <= '1';
s_prod_bytes_c_inc <= '0';
s_prod_byte_index <= (others => '0');
s_rx_bytes_c_rst <= '0';
s_rx_bytes_c_inc <= rx_byte_ready_p_i;
s_rx_byte_index <= std_logic_vector (s_rx_bytes_c);
elsif s_producing = '1' then
s_rx_bytes_c_rst <= '1';
s_rx_bytes_c_inc <= '0';
s_rx_byte_index <= (others => '0');
s_prod_bytes_c_rst <= '0';
s_prod_bytes_c_inc <= tx_byte_request_p_i;
s_prod_byte_index <= std_logic_vector (s_prod_bytes_c);
else
s_prod_bytes_c_rst <= '1';
s_prod_bytes_c_inc <= '0';
s_prod_byte_index <= (others => '0');
s_rx_bytes_c_rst <= '1';
s_rx_bytes_c_inc <= '0';
s_rx_byte_index <= (others => '0');
end if;
end process;
-- -- -- -- -- -- -- -- -- -- --
s_rx_bytes_c_rst <= '0' when (s_id_dat_frame_ok = '1') or (s_consuming = '1') else '1';
s_rx_bytes_c_inc <= rx_byte_ready_p_i when (s_id_dat_frame_ok = '1') or (s_consuming = '1') else '0';
......@@ -737,13 +705,12 @@ begin
-- Independant Timeout Counter --
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Instantiation of a WF_decr_counter relying only on the system clock as an additional
-- way to go back to Idle state, in case any other logic is being stuck.
Session_Timeout_Counter: WF_decr_counter
generic map (g_counter_lgth => 21)
port map (
generic map(g_counter_lgth => 21)
port map(
uclk_i => uclk_i,
nfip_rst_i => nfip_rst_i,
counter_top => (others => '1'),
......@@ -760,6 +727,15 @@ begin
-- Turnaround & Silence times --
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- retrieval of the turnaround and silence times (in equivalent number of uclk ticks) from the
-- c_TIMEOUTS_TABLE declared in the WF_package unit.
s_turnaround_time <= to_unsigned((c_TIMEOUTS_TABLE(to_integer(unsigned(rate_i))).turnaround),
s_turnaround_time'length);
s_silence_time <= to_unsigned((c_TIMEOUTS_TABLE(to_integer(unsigned(rate_i))).silence),
s_turnaround_time'length);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Instantiation of a WF_decr_counter for the counting of turnaround and silence times.
-- The same counter is used in both cases. The signal s_time_c_top initializes the counter
......@@ -769,8 +745,8 @@ begin
-- states "produce_wait_turnar_time" and "consume_wait_FSS" respectively.
Turnaround_and_Silence_Time_Counter: WF_decr_counter
generic map (g_counter_lgth => 18)
port map (
generic map(g_counter_lgth => 18)
port map(
uclk_i => uclk_i,
nfip_rst_i => nfip_rst_i,
counter_top => s_time_c_top,
......@@ -781,48 +757,9 @@ begin
counter_is_zero_o => s_time_c_is_zero);
-------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- retrieval of the turnaround and silence times (in equivalent number of uclk ticks) from the
-- c_TIMEOUTS_TABLE declared in the WF_package unit.
s_turnaround_time <= to_unsigned((c_TIMEOUTS_TABLE(to_integer(unsigned(rate_i))).turnaround),
s_turnaround_time'length);
s_silence_time <= to_unsigned((c_TIMEOUTS_TABLE(to_integer(unsigned(rate_i))).silence),
s_turnaround_time'length);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Combinatorial process Inputs_for_Turnaround_and_Silence_Time_Counter: The process gives values
-- to the counter_top_i and counter_load_i inputs of the Turnaround_and_Silence_Time_Counter,
-- according to the state of the FSM and the type of received variable (s_prod_or_cons).
Inputs_for_Turnaround_and_Silence_Time_Counter: process (s_prod_wait_turnar_time, s_turnaround_time,
s_id_dat_frame_ok, s_prod_or_cons,
s_cons_wait_FSS, s_silence_time)
begin
if s_id_dat_frame_ok = '1' and s_prod_or_cons = "10" then
s_time_c_load <= '1'; -- counter loads
s_time_c_top <= s_turnaround_time;
elsif s_id_dat_frame_ok = '1' and s_prod_or_cons = "01" then
s_time_c_load <= '1'; -- counter loads
s_time_c_top <= s_silence_time;
elsif s_prod_wait_turnar_time = '1' then
s_time_c_load <= '0'; -- counter counts
s_time_c_top <= s_silence_time;
elsif s_cons_wait_FSS = '1' then
s_time_c_load <= '0'; -- counter counts
s_time_c_top <= s_silence_time;
else
s_time_c_load <= '1';
s_time_c_top <= s_silence_time;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- --
s_time_c_top <= s_turnaround_time when (s_id_dat_frame_ok = '1' and s_prod_or_cons = "10") else s_silence_time;
s_time_c_load <= '0' when s_prod_wait_turnar_time= '1' or s_cons_wait_FSS = '1' else '1';
......@@ -836,10 +773,11 @@ begin
-- upon its arrival
-- o output signal var_o (or s_var, used also internally by the WF_prod_data_lgth_calc) that
-- locks to the value of the ID_DAT.Identifier.Variable byte at the end of the reception of a
-- valid ID_DAT frame, if the specified station address concerns the station.
-- valid ID_DAT frame, if the received SUBS byte matches the station's address.
-- For a produced var this takes place at the "produce_wait_turnar_time" state, and
-- for a consumed at the "consume" state (not in the "consume_wait_silence_time", as at this
-- state there is no knowledge that a consumed RP_DAT frame will indeed arrive).
-- state there is no knowledge that a consumed RP_DAT frame will indeed arrive!).
-- (the process is very simple but very big as we decided not to use a for loop:s)
ID_DAT_var: process (uclk_i)
begin
......@@ -862,60 +800,62 @@ begin
-------------------------------------------------------------------------------------------
elsif (s_id_dat_var_byte = '1') and (rx_byte_ready_p_i = '1') then -- var byte arrived
case rx_byte_i is
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
if rx_byte_i = c_VARS_ARRAY(c_VAR_PRESENCE_INDEX).hexvalue then
when c_VARS_ARRAY(c_VAR_PRESENCE_INDEX).hexvalue =>
s_var_aux <= var_presence;
s_prod_or_cons <= c_VARS_ARRAY(c_VAR_PRESENCE_INDEX).prod_or_cons;
s_broadcast_var <= c_VARS_ARRAY(c_VAR_PRESENCE_INDEX).broadcast;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
elsif rx_byte_i = c_VARS_ARRAY(c_VAR_IDENTIF_INDEX).hexvalue then
when c_VARS_ARRAY(c_VAR_IDENTIF_INDEX).hexvalue =>
s_var_aux <= var_identif;
s_prod_or_cons <= c_VARS_ARRAY(c_VAR_IDENTIF_INDEX).prod_or_cons;
s_broadcast_var <= c_VARS_ARRAY(c_VAR_IDENTIF_INDEX).broadcast;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
elsif rx_byte_i = c_VARS_ARRAY(c_VAR_1_INDEX).hexvalue then
when c_VARS_ARRAY(c_VAR_1_INDEX).hexvalue =>
s_var_aux <= var_1;
s_prod_or_cons <= c_VARS_ARRAY(c_VAR_1_INDEX).prod_or_cons;
s_broadcast_var <= c_VARS_ARRAY(c_VAR_1_INDEX).broadcast;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
elsif rx_byte_i = c_VARS_ARRAY(c_VAR_2_INDEX).hexvalue then
when c_VARS_ARRAY(c_VAR_2_INDEX).hexvalue =>
s_var_aux <= var_2;
s_prod_or_cons <= c_VARS_ARRAY(c_VAR_2_INDEX).prod_or_cons;
s_broadcast_var <= c_VARS_ARRAY(c_VAR_2_INDEX).broadcast;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
elsif rx_byte_i = c_VARS_ARRAY(c_VAR_3_INDEX).hexvalue then
when c_VARS_ARRAY(c_VAR_3_INDEX).hexvalue =>
s_var_aux <= var_3;
s_prod_or_cons <= c_VARS_ARRAY(c_VAR_3_INDEX).prod_or_cons;
s_broadcast_var <= c_VARS_ARRAY(c_VAR_3_INDEX).broadcast;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
elsif rx_byte_i = c_VARS_ARRAY(c_VAR_RST_INDEX).hexvalue then
when c_VARS_ARRAY(c_VAR_RST_INDEX).hexvalue =>
s_var_aux <= var_rst;
s_prod_or_cons <= c_VARS_ARRAY(c_VAR_RST_INDEX).prod_or_cons;
s_broadcast_var <= c_VARS_ARRAY(c_VAR_RST_INDEX).broadcast;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
elsif rx_byte_i = c_VARS_ARRAY(c_VAR_JC1_INDEX).hexvalue then
when c_VARS_ARRAY(c_VAR_JC1_INDEX).hexvalue =>
s_var_aux <= var_jc1;
s_prod_or_cons <= c_VARS_ARRAY(c_VAR_JC1_INDEX).prod_or_cons;
s_broadcast_var <= c_VARS_ARRAY(c_VAR_JC1_INDEX).broadcast;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
elsif rx_byte_i = c_VARS_ARRAY(c_VAR_JC3_INDEX).hexvalue then
when c_VARS_ARRAY(c_VAR_JC3_INDEX).hexvalue =>
s_var_aux <= var_jc3;
s_prod_or_cons <= c_VARS_ARRAY(c_VAR_JC3_INDEX).prod_or_cons;
s_broadcast_var <= c_VARS_ARRAY(c_VAR_JC3_INDEX).broadcast;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
else
when others =>
s_var_aux <= var_whatever;
s_prod_or_cons <= "00";
s_broadcast_var <= '0';
end if;
end case;
-------------------------------------------------------------------------------------------
......@@ -928,7 +868,6 @@ begin
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Concurrent signal assignment (used by the FSM)
......@@ -939,18 +878,14 @@ begin
rx_byte_i = c_VARS_ARRAY(c_VAR_2_INDEX).hexvalue or
rx_byte_i = c_VARS_ARRAY(c_VAR_3_INDEX).hexvalue or
rx_byte_i = c_VARS_ARRAY(c_VAR_JC1_INDEX).hexvalue or
rx_byte_i = c_VARS_ARRAY(c_VAR_JC3_INDEX).hexvalue
else '0';
rx_byte_i = c_VARS_ARRAY(c_VAR_JC3_INDEX).hexvalue else '0';
---------------------------------------------------------------------------------------------------
-- Introducing delays --
-- Signals Registration --
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Registering the signals tx_last_data_byte_p_o, tx_byte_request_accept_p_o, tx_start_p_o
process (uclk_i)
begin
if rising_edge (uclk_i) then
......@@ -971,33 +906,38 @@ begin
end if;
end process;
-- -- -- -- -- -- -- -- -- -- --
s_tx_byte_request_accept_p <= s_producing and (tx_byte_request_p_i or s_tx_start_prod_p);
s_tx_last_data_byte_p <= s_producing and s_prod_data_lgth_match and tx_byte_request_p_i;
---------------------------------------------------------------------------------------------------
-- Concurrent Signal Assignments --
---------------------------------------------------------------------------------------------------
-- variable received by a valid ID_DAT frame that concerns this station
var_o <= s_var;
-- number of bytes of the Control & Data fields of a produced RP_DAT frame
-- number of bytes for the CTRL & Data fields of a produced RP_DAT frame
prod_data_lgth_o <= s_prod_data_lgth;
-- response to WF_tx_serializer request for a byte
tx_byte_request_accept_p_o <= s_tx_byte_request_accept_p_d2;
-- index of the byte being consumed or produced
prod_cons_byte_index_o <= s_prod_byte_index when s_producing = '1' else s_rx_byte_index;
-- index of the byte being produced/ consumed
prod_byte_index_o <= std_logic_vector (s_prod_bytes_c);
cons_byte_index_o <= std_logic_vector (s_rx_bytes_c);
-- The WF_fd_receiver receives a 1 uclk long reset pulse if during the reception of an ID or an
-- RP_DAT the engine control FSM goes back to idle.
-- This may happen if : any of the Ctrl, variable, subs bytes of an ID_DAT frame are wrong or
-- RP_DAT the engine control FSM has to go back to idle.
-- This may happen if : any of the CTRL, variable, subs bytes of an ID_DAT frame are wrong or
-- an ID_DAT is lasting more than 8 bytes or
-- an RP_DAT is lasting more than 133 bytes or
-- the silence times expires --------------------------------------------------------------------------------
-- the silence times expires
-- the engine control FSM times out
-- The receiver discards the frame that was being received and restarts looking for the FSS of a new one.
-- After this reset, the receiver will discard any frame being received and will restart looking
-- for the FSS of a new one.
-- The WF_fd_receiver also stays reset during a production session.
rx_rst_o <= '1' when (s_rst_rx_p = '1') or
(s_prod_wait_turnar_time = '1') or (s_producing = '1') else '0';
......@@ -1008,7 +948,6 @@ begin
-- production starts after the expiration of the turnaround time
tx_start_p_o <= s_tx_start_prod_p;
---------------------------------------------------------------------------------------------------
end architecture rtl;
......
wf_fd_receiver.vhd
View file @ caddc235
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- --
-- WF_fd_receiver --
-- --
-- |
-- WF_fd_receiver |
-- |
---------------------------------------------------------------------------------------------------
-- File WF_fd_receiver.vhd
--
-- Description The unit groups the main actions that regard FIELDRIVE data reception.
-- It instantiates the units:
--
-- o WF_rx_deserializer : for the formation of bytes of data to be provided to the:
-- o WF_engine_control unit, for the contents of ID_DAT frames
-- o WF_cons_bytes_processor unit, for the contents of consumed
-- RP_DAT frames
--
-- o WF_rx_osc : for the clock recovery
--
-- o WF_rx_deglitcher : for the filtering of the input FD_RXD
--
--
-- _________________________ _________________________
-- | | | |
-- | WF_Consumption | | WF_engine_control |
-- |_________________________| |_________________________|
-- /\ /\
-- ___________________________________________________________
-- | WF_fd_revceiver |
-- | _________ |
-- | _______________________________________ | | |
-- | | | | | |
-- | | WF_rx_deserializer | | WF_rx | |
-- | | | < | _osc | |
-- | |_______________________________________| | | |
-- | /\ |_________| |
-- | _______________________________________ |
-- | | | |
-- | | WF_rx_deglitcher | |
-- | |_______________________________________| |
-- | |
-- |___________________________________________________________|
-- \/
-- ___________________________________________________________________
-- 0_____________________________FIELDBUS______________________________O
--
--
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
-- Date 15/02/2011
-- Version v0.01
-- Depends on WF_reset_unit
-- WF_engine_control
----------------
-- Last changes
-- 02/2011 v0.01 EG First version
-- File WF_fd_receiver.vhd |
-- |
-- Description The unit groups the main actions that regard FIELDRIVE data reception. |
-- It instantiates the units: |
-- |
-- o WF_rx_deserializer: for the formation of bytes of data to be provided to the: |
-- o WF_engine_control unit, for the contents of ID_DAT frames |
-- o WF_cons_bytes_processor unit, for the contents of consumed|
-- RP_DAT frames |
-- |
-- o WF_rx_osc : for the clock recovery |
-- |
-- o WF_rx_deglitcher : for the filtering of the input FD_RXD |
-- |
-- |
-- _________________________ _________________________ |
-- | | | | |
-- | WF_Consumption | | WF_engine_control | |
-- |_________________________| |_________________________| |
-- /\ /\ |
-- ___________________________________________________________ |
-- | WF_fd_revceiver | |
-- | _________ | |
-- | _______________________________________ | | | |
-- | | | | | | |
-- | | WF_rx_deserializer | | WF_rx | | |
-- | | | < | _osc | | |
-- | |_______________________________________| | | | |
-- | /\ |_________| | |
-- | _______________________________________ | |
-- | | | | |
-- | | WF_rx_deglitcher | | |
-- | |_______________________________________| | |
-- | | |
-- |___________________________________________________________| |
-- \/ |
-- ___________________________________________________________________ |
-- 0_____________________________FIELDBUS______________________________O |
-- |
-- |
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 15/02/2011 |
-- Version v0.01 |
-- Depends on WF_reset_unit |
-- WF_engine_control |
---------------- |
-- Last changes |
-- 02/2011 v0.01 EG First version |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
......@@ -92,9 +92,7 @@ use work.WF_PACKAGE.all; -- definitions of types, constants, entities
--=================================================================================================
-- Entity declaration for WF_fd_receiver
--=================================================================================================
entity WF_fd_receiver is
port (
entity WF_fd_receiver is port(
-- INPUTS
-- nanoFIP User Interface, General signals
uclk_i : in std_logic; -- 40 MHZ clock
......@@ -124,8 +122,8 @@ entity WF_fd_receiver is
-- wrong CRC; pulse upon FES detection
-- Signals to the WF_engine_control
rx_fss_received_p_o : out std_logic -- pulse upon FSS detection (ID/ RP_DAT)
);
rx_fss_received_p_o : out std_logic);-- pulse upon FSS detection (ID/ RP_DAT)
end entity WF_fd_receiver;
......@@ -139,6 +137,7 @@ architecture struc of WF_fd_receiver is
signal s_fd_rxd_filt, s_rxd_filt_edge_p : std_logic;
signal s_fd_rxd_filt_f_edge_p, s_fd_rxd_filt_r_edge_p : std_logic;
--=================================================================================================
-- architecture begin
--=================================================================================================
......@@ -150,7 +149,7 @@ begin
---------------------------------------------------------------------------------------------------
FIELDRIVE_Receiver_Deglitcher: WF_rx_deglitcher
port map (
port map(
uclk_i => uclk_i,
nfip_rst_i => nfip_rst_i,
fd_rxd_a_i => fd_rxd_a_i,
......@@ -169,7 +168,7 @@ begin
---------------------------------------------------------------------------------------------------
FIELDRIVE_Receiver_Oscillator: WF_rx_osc
port map (
port map(
uclk_i => uclk_i,
rate_i => rate_i,
nfip_rst_i => nfip_rst_i,
......@@ -189,7 +188,7 @@ begin
---------------------------------------------------------------------------------------------------
FIELDRIVE_Receiver_Deserializer: WF_rx_deserializer
port map (
port map(
uclk_i => uclk_i,
nfip_rst_i => nfip_rst_i,
rx_rst_i => rx_rst_i,
......
wf_fd_transmitter.vhd
View file @ caddc235
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- --
-- WF_fd_transmitter --
-- --
-- |
-- WF_fd_transmitter |
-- |
---------------------------------------------------------------------------------------------------
-- File WF_fd_transmitter.vhd
--
-- Description The unit groups the main actions that regard FIELDRIVE data transmission.
-- It instantiates the units:
--
-- o WF_tx_serializer : that receives bytes from the WF_Production, encodes them
-- (Manchester 2), adds the FSS, FCS & FES fields and puts one
-- by one bits to the FIELDRIVE output FD_TXD, following the
-- synchronization signals from the WF_tx_osc unit.
-- Also generates the nanoFIP output FD_TXENA.
--
-- o WF_tx_osc : that generates the nanoFIP FIELDRIVE output FD_TXCK
-- and the array of pulses tx_sched_p_buff (used for the
-- synchronization of the WF_tx_serializer's actions).
-- ___________________________________________________________
-- | |
-- | WF_Production |
-- |___________________________________________________________|
-- \/
-- ___________________________________________________________
-- | WF_fd_transmitter |
-- | |
-- | ________________________________________________ |
-- | | | |
-- | | WF_tx_osc | |
-- | |________________________________________________| |
-- | |
-- | _________________________________________________ |
-- | | | |
-- | | WF_tx_serializer | |
-- | | | |
-- | |_________________________________________________| |
-- |___________________________________________________________|
-- \/
-- ___________________________________________________________________
-- 0_____________________________FIELDBUS______________________________O
--
--
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
-- Date 11/01/2011
-- Version v0.01
-- Depends on WF_reset_unit
-- WF_production
-- WF_engine_control
----------------
-- Last changes
-- 01/2011 EG v0.01 first version
-- File WF_fd_transmitter.vhd |
-- |
-- Description The unit groups the main actions that regard FIELDRIVE data transmission. |
-- It instantiates the units: |
-- |
-- o WF_tx_serializer: that receives bytes from the WF_Production, encodes them |
-- (Manchester 2), adds the FSS, FCS & FES fields and puts one |
-- by one bits to the FIELDRIVE output FD_TXD, following the |
-- synchronization signals from the WF_tx_osc unit. |
-- Also generates the nanoFIP output FD_TXENA. |
-- |
-- o WF_tx_osc : that generates the nanoFIP FIELDRIVE output FD_TXCK |
-- and the array of pulses tx_sched_p_buff (used for the |
-- synchronization of the WF_tx_serializer's actions). |
-- |
-- ___________________________________________________________ |
-- | | |
-- | WF_Production | |
-- |___________________________________________________________| |
-- \/ |
-- ___________________________________________________________ |
-- | WF_fd_transmitter | |
-- | | |
-- | ________________________________________________ | |
-- | | | | |
-- | | WF_tx_osc | | |
-- | |________________________________________________| | |
-- | | |
-- | _________________________________________________ | |
-- | | | | |
-- | | WF_tx_serializer | | |
-- | | | | |
-- | |_________________________________________________| | |
-- |___________________________________________________________| |
-- \/ |
-- ___________________________________________________________________ |
-- 0_____________________________FIELDBUS______________________________O |
-- |
-- |
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 11/01/2011 |
-- Version v0.01 |
-- Depends on WF_reset_unit |
-- WF_production |
-- WF_engine_control |
---------------- |
-- Last changes |
-- 01/2011 EG v0.01 first version |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
......@@ -92,9 +93,7 @@ use work.WF_PACKAGE.all; -- definitions of types, constants, entities
-- Entity declaration for WF_fd_transmitter
--=================================================================================================
entity WF_fd_transmitter is
port (
entity WF_fd_transmitter is port(
-- INPUTS
-- nanoFIP User Interface, General signal
uclk_i : in std_logic; -- 40 MHz clock
......@@ -125,8 +124,8 @@ entity WF_fd_transmitter is
-- nanoFIP FIELDRIVE outputs
tx_data_o : out std_logic; -- transmitter data
tx_enable_o : out std_logic; -- transmitter enable
tx_clk_o : out std_logic -- line driver half bit clock
);
tx_clk_o : out std_logic);-- line driver half bit clock
end entity WF_fd_transmitter;
......@@ -138,6 +137,7 @@ architecture struc of WF_fd_transmitter is
signal s_tx_clk_p_buff : std_logic_vector (c_TX_SCHED_BUFF_LGTH-1 downto 0);
signal s_tx_osc_rst_p : std_logic;
--=================================================================================================
-- architecture begin
--=================================================================================================
......@@ -149,14 +149,14 @@ begin
---------------------------------------------------------------------------------------------------
tx_oscillator: WF_tx_osc
port map (
uclk_i => uclk_i,
rate_i => rate_i,
nfip_rst_i => nfip_rst_i,
tx_osc_rst_p_i => s_tx_osc_rst_p,
port map(
uclk_i => uclk_i,
rate_i => rate_i,
nfip_rst_i => nfip_rst_i,
tx_osc_rst_p_i => s_tx_osc_rst_p,
-----------------------------------------------
tx_clk_o => tx_clk_o,
tx_sched_p_buff_o => s_tx_clk_p_buff);
tx_clk_o => tx_clk_o,
tx_sched_p_buff_o => s_tx_clk_p_buff);
-----------------------------------------------
......@@ -166,20 +166,20 @@ begin
---------------------------------------------------------------------------------------------------
tx_serializer: WF_tx_serializer
port map (
uclk_i => uclk_i,
nfip_rst_i => nfip_rst_i,
tx_start_p_i => tx_start_p_i,
byte_request_accept_p_i => tx_byte_request_accept_p_i,
byte_i => tx_byte_i,
last_byte_p_i => tx_last_data_byte_p_i,
tx_sched_p_buff_i => s_tx_clk_p_buff,
port map(
uclk_i => uclk_i,
nfip_rst_i => nfip_rst_i,
tx_start_p_i => tx_start_p_i,
byte_request_accept_p_i => tx_byte_request_accept_p_i,
byte_i => tx_byte_i,
last_byte_p_i => tx_last_data_byte_p_i,
tx_sched_p_buff_i => s_tx_clk_p_buff,
-----------------------------------------------
tx_byte_request_p_o => tx_byte_request_p_o,
tx_completed_p_o => tx_completed_p_o,
tx_data_o => tx_data_o,
tx_osc_rst_p_o => s_tx_osc_rst_p,
tx_enable_o => tx_enable_o );
tx_byte_request_p_o => tx_byte_request_p_o,
tx_completed_p_o => tx_completed_p_o,
tx_data_o => tx_data_o,
tx_osc_rst_p_o => s_tx_osc_rst_p,
tx_enable_o => tx_enable_o );
-----------------------------------------------
......
wf_incr_counter.vhd
View file @ caddc235
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- --
-- WF_incr_counter --
-- --
-- |
-- WF_incr_counter |
-- |
---------------------------------------------------------------------------------------------------
-- File WF_incr_counter.vhd
-- Description Increasing counter with synchronous reset, reinitialise and increase enable
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
-- Date 01/2011
-- Version v0.011
----------------
-- Last changes
-- 10/2010 EG v0.01 first version
-- 01/2011 EG v0.011 counter_full became a constant
-- File WF_incr_counter.vhd |
-- Description Increasing counter with synchronous reset, reinitialise and increase enable |
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 01/2011 |
-- Version v0.011 |
---------------- |
-- Last changes |
-- 10/2010 EG v0.01 first version |
-- 01/2011 EG v0.011 counter_full became a constant |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
......@@ -55,8 +55,8 @@ use work.WF_PACKAGE.all; -- definitions of types, constants, entities
--=================================================================================================
entity WF_incr_counter is
generic (g_counter_lgth : natural := 4); -- default length
port (
generic(g_counter_lgth : natural := 4); -- default length
port(
-- INPUTS
-- nanoFIP User Interface general signal
uclk_i : in std_logic; -- 40 MHz clock
......@@ -69,9 +69,8 @@ entity WF_incr_counter is
-- OUTPUT
-- Signal to any unit
counter_o : out unsigned (g_counter_lgth-1 downto 0); -- counter
counter_is_full_o : out std_logic -- counter full indication
); -- (all bits to '1')
counter_is_full_o : out std_logic); -- counter full indication
-- (all bits to '1')
end entity WF_incr_counter;
......@@ -83,6 +82,7 @@ architecture rtl of WF_incr_counter is
constant c_COUNTER_FULL : unsigned (g_counter_lgth-1 downto 0) := (others => '1');
signal s_counter : unsigned (g_counter_lgth-1 downto 0);
--=================================================================================================
-- architecture begin
--=================================================================================================
......@@ -96,18 +96,16 @@ begin
begin
if rising_edge (uclk_i) then
if reinit_counter_i = '1' then
s_counter <= (others => '0');
s_counter <= (others => '0');
elsif incr_counter_i = '1' then
s_counter <= s_counter + 1;
s_counter <= s_counter + 1;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Concurrent assignments for output signals
counter_o <= s_counter;
counter_is_full_o <= '1' when s_counter = c_COUNTER_FULL else '0';
......
wf_jtag_controller.vhd
View file @ caddc235
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- --
-- WF_jtag_controller --
-- --
-- |
-- WF_jtag_controller |
-- |
---------------------------------------------------------------------------------------------------
-- File WF_jtag_controller.vhd
--
-- Description After the reception and validation of a consumed var_jc1 RP_DAT frame, the unit is
-- responsible for driving the "nanoFIP, User Interface, JTAG Controller" signals
-- JC_TCK, JC_TMS, JC_TDI and for sampling the JC_TDO input.
-- o JC_TCK is a 5 MHz clock generated by the 40 MHz uclk; a cycle is created for
-- every JC_TMS/ JC_TDI pair.
-- o JC_TMS and JC_TDI are being retreived from the JC_consumed memory and are
-- put to the corresponding outputs on each falling edge of the JC_TCK.
-- The first and second data bytes of the JC_consumed memory do not contain JC_TMS
-- and JC_TDI bits, but are used to indicate, in big indian order, the amount of
-- JC_TMS and JC_TDI bits that have to be output.
--
-- o the JC_TDO input is sampled on the rising edge of JC_TCK; only the last sampled
-- JC_TDO bit is significant and it is registered and sent at the next var_jc2
-- produced frame.
--
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
-- Date 07/07/2011
-- Version v0.01
-- Depends on WF_reset_unit
-- WF_consumption
----------------
-- Last changes
-- 07/07/2011 v0.01 EG First version
-- File WF_jtag_controller.vhd |
-- |
-- Description After the reception and validation of a consumed var_jc1 RP_DAT frame, the unit |
-- is responsible for driving the "nanoFIP, User Interface, JTAG Controller" signals |
-- JC_TCK, JC_TMS, JC_TDI and for sampling the JC_TDO input. |
-- |
-- o JC_TCK is a 5 MHz clock generated by the 40 MHz uclk; a cycle is created for |
-- every JC_TMS/ JC_TDI pair. |
-- |
-- o JC_TMS and JC_TDI are being retreived from the JC_consumed memory and are |
-- put to the corresponding outputs on each falling edge of the JC_TCK. |
-- |
-- o The first and second data bytes of the JC_consumed memory do not contain |
-- JC_TMS/ JC_TDI bits, but are used to indicate, in big indian order, the |
-- amount of and JC_TDI bits that have to be output. |
-- |
-- o the JC_TDO input is sampled on the rising edge of JC_TCK; only the last |
-- sampled JC_TDO bit is significant. It is registered and sent to the |
-- WF_production unit for it to be delivered in the next var_jc3 produced frame. |
-- |
-- |
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 07/07/2011 |
-- Version v0.01 |
-- Depends on WF_reset_unit |
-- WF_consumption |
---------------- |
-- Last changes |
-- 07/07/2011 v0.01 EG First version |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
......@@ -69,36 +73,34 @@ use work.WF_PACKAGE.all; -- definitions of types, constants, entities
--=================================================================================================
-- Entity declaration for WF_jtag_controller
--=================================================================================================
entity WF_jtag_controller is
port (
entity WF_jtag_controller is port(
-- INPUTS
-- nanoFIP User Interface, General signals
uclk_i : in std_logic; -- 40 MHz clock
uclk_i : in std_logic; -- 40 MHz clock
-- nanoFIP User Interface, JTAG Controller signal
jc_tdo_i : in std_logic; -- JTAG TDO input
jc_tdo_i : in std_logic; -- JTAG TDO input
-- Signal from the WF_reset_unit
nfip_rst_i : in std_logic; -- nanoFIP internal reset
nfip_rst_i : in std_logic; -- nanoFIP internal reset
-- Signals from the WF_consumption unit
jc_start_p_i : in std_logic; -- pulse upon validation of a jc_var1 RP_DAT frame
jc_mem_data_i : in std_logic_vector (7 downto 0); -- byte retreived from the JC_consumed memory
jc_start_p_i : in std_logic; -- pulse upon validation of a jc_var1 RP_DAT frame
jc_mem_data_i : in std_logic_vector (7 downto 0); -- byte retreived from the JC_consumed memory
-- OUTPUTS
-- nanoFIP User Interface, JTAG Controller signals
jc_tms_o : out std_logic; -- JTAG TMS output
jc_tdi_o : out std_logic; -- JTAG TDI output
jc_tck_o : out std_logic; -- JTAG TCK output
jc_tms_o : out std_logic; -- JTAG TMS output
jc_tdi_o : out std_logic; -- JTAG TDI output
jc_tck_o : out std_logic; -- JTAG TCK output
-- Signal to the WF_production unit
jc_tdo_byte_o : out std_logic_vector (7 downto 0);-- byte containing the TDO sample
jc_tdo_byte_o : out std_logic_vector (7 downto 0); -- byte containing the TDO sample
-- Signal to the WF_consumption unit
jc_mem_adr_rd_o : out std_logic_vector (8 downto 0) -- address of byte to be retreived from the JC_cons memory
);
jc_mem_adr_rd_o : out std_logic_vector (8 downto 0));-- address of byte to be retreived from the JC_cons memory
end entity WF_jtag_controller;
......@@ -106,24 +108,26 @@ end entity WF_jtag_controller;
-- architecture declaration
--=================================================================================================
architecture rtl of WF_jtag_controller is
-- FSM
type jc_st_t is (idle, get_byte, play_byte, set_address);
signal jc_st, nx_jc_st : jc_st_t;
signal s_idle, s_get_byte, s_play_byte, s_set_adr : std_logic;
signal s_bytes_c, s_bytes_c_d1 : unsigned (6 downto 0);
signal s_bits_so_far : unsigned (15 downto 0);
signal s_frame_bits_lsb, s_frame_bits_msb : std_logic_vector (7 downto 0);
signal s_frame_bits : unsigned (15 downto 0);
signal s_tck, s_tck_transition, s_tck_c_is_full : std_logic;
signal s_tck_c, s_tck_period, s_tck_four_periods : unsigned (c_FOUR_JC_TCK_C_LGTH-1 downto 0);
signal s_tck_half_period, s_tck_quarter_period : unsigned (c_FOUR_JC_TCK_C_LGTH-1 downto 0);
signal jc_st, nx_jc_st : jc_st_t;
signal s_idle, s_play_byte, s_set_adr : std_logic;
signal s_not_play_byte : std_logic;
signal s_session_timedout : std_logic;
-- bytes counter
signal s_bytes_c, s_bytes_c_d1 : unsigned (6 downto 0);
-- retrieval of the number of TMS/ TDI bits that have to be delivered
signal s_frame_bits_lsb, s_frame_bits_msb : std_logic_vector (7 downto 0);
signal s_frame_bits : unsigned (15 downto 0);
-- number of TMS/ TDI bits delivered so far
signal s_bits_so_far : unsigned (15 downto 0);
-- TCK generation
signal s_tck, s_tck_c_is_full : std_logic;
signal s_tck_r_edge_p, s_tck_f_edge_p : std_logic;
signal s_tck_c, s_tck_period, s_tck_four_periods : unsigned (c_FOUR_JC_TCK_C_LGTH-1 downto 0);
signal s_tck_half_period, s_tck_quarter_period : unsigned (c_FOUR_JC_TCK_C_LGTH-1 downto 0);
--=================================================================================================
-- architecture begin
--=================================================================================================
......@@ -134,6 +138,22 @@ begin
-- FSM --
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- JTAG Controller FSM: the state machine is divided in three parts (a clocked process
-- to store the current state, a combinatorial process to manage state transitions and finally a
-- combinatorial process to manage the output signals), which are the three processes that follow.
-- After the reception of a valid jc_var1 RP_DAT frame the FSM starts retrieving one by one bytes
-- from the JC_consumed memory. The first two bytes concatenated in big endian encoding indicate
-- the total amount of TMS/ TDI bits that have to be retrieved and output.
-- The rest of the bytes contain the TMS/ TDI bits.
-- The FSM goes back to idle if the counter that counts the amount the bits that have been output
-- reaches the total amount.
-- To add a rubust layer of protection to the FSM, we have added a counter, dependant only on the
-- system clock, that from any state can bring the FSM back to idle. At any bit rate the
-- reception of an ID_DAT frame followed by the reception/ transmission of an RP_DAT should not
-- last more than 37ms. Hence, we have generated a 21 bits counter that will bring the machine back
-- to idle if more than 52ms (complete 21 bit counter) have passed since it has left this idle state.
-- Synchronous process JC_FSM_Sync: storage of the current state of the FSM
JC_FSM_Sync: process (uclk_i)
......@@ -151,12 +171,9 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Combinatorial process JC_FSM_Comb_State_Transitions: Definition of the state
-- transitions of the FSM.
-- s_frame_bits indicates the amount of TMS/ TDI bits that have to be output, according to the
-- first 2 data bytes in the JC_consumed memory
-- s_bits_so_far indicates the amount of bits that have been output so far
JC_FSM_Comb_State_Transitions: process (jc_st, s_bytes_c, s_frame_bits, s_bits_so_far,
jc_start_p_i, s_tck_c_is_full, s_tck_transition)
s_session_timedout, jc_start_p_i, s_tck_c_is_full, s_tck_r_edge_p, s_tck_f_edge_p)
begin
case jc_st is
......@@ -171,30 +188,41 @@ begin
end if;
when set_address =>
nx_jc_st <= get_byte; -- 1 uclk cycle for the setting of the memory
if s_session_timedout = '1' then
nx_jc_st <= idle;
else
nx_jc_st <= get_byte; -- 1 uclk cycle for the setting of the memory
-- address; byte available at the next cycle
end if;
when get_byte =>
if s_bytes_c < 2 then -- 2 first bytes: amount of JC_TMS & JC_TDI bits
if s_session_timedout = '1' then
nx_jc_st <= idle;
elsif s_bytes_c < 2 then -- 2 first bytes: amount of JC_TMS & JC_TDI bits
nx_jc_st <= set_address;
else -- the rest of the bytes have to be "played"
nx_jc_st <= play_byte;
end if;
when play_byte =>
if s_frame_bits <= 0 or s_frame_bits > c_MAX_FRAME_BITS then -- outside expected limits
if s_session_timedout = '1' then
nx_jc_st <= idle;
elsif s_frame_bits <= 0 or s_frame_bits > c_MAX_FRAME_BITS then -- outside expected limits
nx_jc_st <= idle;
elsif s_frame_bits > s_bits_so_far then
if s_tck_c_is_full = '1' then -- byte completed
if s_tck_c_is_full = '1' then -- byte completed; a new one has to be retrieved
nx_jc_st <= set_address;
else -- byte being output
nx_jc_st <= play_byte;
end if;
else -- last bit
if s_tck_transition = '1' then
if s_tck_r_edge_p = '1' or s_tck_f_edge_p = '1' then
nx_jc_st <= idle; -- wait until the completion of a JC_TCK cycle
else
nx_jc_st <= play_byte;
......@@ -203,11 +231,12 @@ begin
when others =>
nx_jc_st <= idle;
end case;
end case;
end process;
JCtrler_FSM_Comb_Output_Signals: process (jc_st)
JCTRLer_FSM_Comb_Output_Signals: process (jc_st)
begin
......@@ -218,7 +247,6 @@ begin
s_idle <= '1';
-----------------------------
s_set_adr <= '0';
s_get_byte <= '0';
s_play_byte <= '0';
......@@ -228,26 +256,22 @@ begin
-----------------------------
s_set_adr <= '1';
-----------------------------
s_get_byte <= '0';
s_play_byte <= '0';
when get_byte =>
when play_byte =>
s_idle <= '0';
s_set_adr <= '0';
-----------------------------
s_get_byte <= '1';
s_play_byte <= '1';
-----------------------------
s_play_byte <= '0';
when play_byte =>
when others =>
s_idle <= '0';
s_idle <= '1';
s_set_adr <= '0';
s_get_byte <= '0';
-----------------------------
s_play_byte <= '1';
-----------------------------
s_play_byte <= '0';
end case;
end process;
......@@ -258,18 +282,20 @@ begin
---------------------------------------------------------------------------------------------------
-- Instantiation of a WF_incr_counter used for the generation of the JC_TCK output clock.
-- The counter is filled up after having counted 4 JC_TCK periods; this corresponds to the amount
-- of periods needed for outputting a full JC_TMS/ JC_TDI byte;
-- of periods needed for outputting a full JC_TMS/ JC_TDI byte.
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
JC_TCK_periods_counter: WF_incr_counter
generic map (g_counter_lgth => c_FOUR_JC_TCK_C_LGTH)
port map (
generic map(g_counter_lgth => c_FOUR_JC_TCK_C_LGTH)
port map(
uclk_i => uclk_i,
reinit_counter_i => (not s_play_byte),
reinit_counter_i => s_not_play_byte,
incr_counter_i => s_play_byte,
counter_is_full_o => s_tck_c_is_full,
------------------------------------------
counter_o => s_tck_c);
------------------------------------------
s_not_play_byte <= not s_play_byte;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
JC_TCK_Construction: process (uclk_i)
......@@ -279,7 +305,7 @@ begin
s_tck <= '1';
else
if s_tck_transition = '1' then
if s_tck_f_edge_p = '1' or s_tck_r_edge_p = '1' then
s_tck <= not s_tck;
end if;
......@@ -293,10 +319,15 @@ begin
s_tck_half_period <= (s_tck_four_periods srl 3)+1; -- # uclk ticks for 1/2 JC_TCK period
s_tck_quarter_period <= (s_tck_four_periods srl 4)+1; -- # uclk ticks for 1/4 JC_TCK period
s_tck_transition <= '1' when (s_tck_c = s_tck_quarter_period) or (s_tck_c = s_tck_half_period+s_tck_quarter_period) or
(s_tck_c = (2*s_tck_half_period) +s_tck_quarter_period) or (s_tck_c = (3*s_tck_half_period) +s_tck_quarter_period) or
(s_tck_c = (4*s_tck_half_period) +s_tck_quarter_period) or (s_tck_c = (5*s_tck_half_period) +s_tck_quarter_period) or
(s_tck_c = (6*s_tck_half_period) +s_tck_quarter_period) or (s_tck_c = (7*s_tck_half_period) +s_tck_quarter_period) else '0';
s_tck_f_edge_p <= '1' when (s_tck_c = s_tck_quarter_period) or
(s_tck_c = (2*s_tck_half_period) +s_tck_quarter_period) or
(s_tck_c = (4*s_tck_half_period) +s_tck_quarter_period) or
(s_tck_c = (6*s_tck_half_period) +s_tck_quarter_period) else '0';
s_tck_r_edge_p <= '1' when (s_tck_c = s_tck_half_period+s_tck_quarter_period) or
(s_tck_c = (3*s_tck_half_period) +s_tck_quarter_period) or
(s_tck_c = (5*s_tck_half_period) +s_tck_quarter_period) or
(s_tck_c = (7*s_tck_half_period) +s_tck_quarter_period) else '0';
jc_tck_o <= s_tck;
......@@ -305,11 +336,12 @@ begin
---------------------------------------------------------------------------------------------------
-- Bytes counter --
---------------------------------------------------------------------------------------------------
-- Instantiation of a WF_incr_counter for the bytes that are being retreived from the JC_cons memory.
-- Instantiation of a WF_incr_counter for the counting of the bytes that are being retreived from
-- the JC_cons memory.
JC_bytes_count: WF_incr_counter
generic map (g_counter_lgth => 7)
port map (
JC_bytes_counter: WF_incr_counter
generic map(g_counter_lgth => 7)
port map(
uclk_i => uclk_i,
reinit_counter_i => s_idle,
incr_counter_i => s_set_adr,
......@@ -322,19 +354,47 @@ begin
-- "+2" is bc the first 2 bytes in the memory (PDU_TYPE and Lenght) are not read
---------------------------------------------------------------------------------------------------
-- Delivered bits counter --
---------------------------------------------------------------------------------------------------
-- Creation of a counter counting the number of TMS and TDI bits that have been output.
-- The output of this counter, s_bits_so_far, could have been derived from the s_bytes_c with some
-- combinatorial logic, but then the timing performance was prohibiting.
JC_bits_counter: process (uclk_i)
begin
if rising_edge (uclk_i) then
if s_idle = '1' then
s_bits_so_far <= (others => '0');
elsif s_tck_f_edge_p = '1' then
s_bits_so_far <= s_bits_so_far + 2;
end if;
end if;
end process;
---------------------------------------------------------------------------------------------------
-- Frame bits retreival --
---------------------------------------------------------------------------------------------------
-- Construction of the 16 bits word that indicates the amount of TMS/ TDI bits that have to be
-- played from this frame. The word is the result of the big indian concatenation of the 1st and
-- 2nd data bytes from the memory.
Bits_Number_Retreival: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
s_bytes_c_d1 <= (others => '0');
s_frame_bits_msb <= (others => '0');
s_frame_bits_lsb <= (others => '0');
s_bytes_c_d1 <= (others => '0');
s_frame_bits_msb <= (others => '0');
s_frame_bits_lsb <= (others => '0');
else
s_bytes_c_d1 <= s_bytes_c;
s_bytes_c_d1 <= s_bytes_c;
if s_set_adr = '1' and s_bytes_c_d1 = 0 then
s_frame_bits_msb <= jc_mem_data_i;
......@@ -346,74 +406,92 @@ begin
end if;
end process;
s_frame_bits <= unsigned (s_frame_bits_msb) & unsigned (s_frame_bits_lsb);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
s_frame_bits <= unsigned (s_frame_bits_msb) & unsigned (s_frame_bits_lsb);
---------------------------------------------------------------------------------------------------
-- TMS and TDI player --
---------------------------------------------------------------------------------------------------
-- Delivery of the jc_tms_o and jc_tdi_o bits on the falling edge of the jc_tck_o clock.
-- At the "play_byte" state of the FSM the incoming jc_mem_data_i byte is decomposed to 4 TMS and
-- 4 TDI bits; a pair of TMS/ TDI bits is output on every TCK falling edge.
JC_TMS_TDI_output: process (s_tck, nfip_rst_i)
JC_TMS_TDI_player: process (uclk_i)
begin
if nfip_rst_i = '1' then -- asynchronous reset
jc_tms_o <= '0';
jc_tdi_o <= '0';
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
jc_tms_o <= '0';
jc_tdi_o <= '0';
elsif falling_edge (s_tck) then
elsif s_tck_f_edge_p = '1' then
if s_tck_c < (s_tck_period) then -- 1st JC_TMS/ JC_TDI pair
jc_tms_o <= jc_mem_data_i(7);
jc_tdi_o <= jc_mem_data_i(6);
if s_tck_c < (s_tck_period) then -- 1st JC_TMS/ JC_TDI pair
jc_tms_o <= jc_mem_data_i(7);
jc_tdi_o <= jc_mem_data_i(6);
elsif s_tck_c < (s_tck_period sll 1) then -- 2nd JC_TMS/ JC_TDI pair
jc_tms_o <= jc_mem_data_i(5);
jc_tdi_o <= jc_mem_data_i(4);
elsif s_tck_c < (s_tck_period sll 1) then -- 2nd JC_TMS/ JC_TDI pair
jc_tms_o <= jc_mem_data_i(5);
jc_tdi_o <= jc_mem_data_i(4);
elsif s_tck_c < ((s_tck_period sll 1)+s_tck_period) then -- 3rd JC_TMS/ JC_TDI pair
jc_tms_o <= jc_mem_data_i(3);
jc_tdi_o <= jc_mem_data_i(2);
elsif s_tck_c < ((s_tck_period sll 1)+s_tck_period) then -- 3rd JC_TMS/ JC_TDI pair
jc_tms_o <= jc_mem_data_i(3);
jc_tdi_o <= jc_mem_data_i(2);
else
jc_tms_o <= jc_mem_data_i(1); -- 4th JC_TMS/ JC_TDI pair
jc_tdi_o <= jc_mem_data_i(0);
else
jc_tms_o <= jc_mem_data_i(1); -- 4th JC_TMS/ JC_TDI pair
jc_tdi_o <= jc_mem_data_i(0);
end if;
end if;
end if;
end process;
--------------------------------------------------------------------------------------------------
-- TDO sampler --
---------------------------------------------------------------------------------------------------
-- Delivered bits counter --
---------------------------------------------------------------------------------------------------
JC_bits_counter: process (s_tck, nfip_rst_i, s_idle)
-- Sampling of the jc_tdo_i input on the rising edge of the jc_tck_o clock. Only the last sampled
-- bit is significant and needs to be delivered.
JC_TDO_sampling: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
jc_tdo_byte_o <= (others => '0');
elsif s_tck_r_edge_p = '1' then
jc_tdo_byte_o <= "0000000" & jc_tdo_i;
end if;
if s_idle = '1' then -- asynchronous reset
s_bits_so_far <= (others => '0');
elsif falling_edge (s_tck) then
s_bits_so_far <= s_bits_so_far + 2;
end if;
end process;
--------------------------------------------------------------------------------------------------
-- TDO sampler --
---------------------------------------------------------------------------------------------------
JC_TDO_sampling: process (s_tck, nfip_rst_i)
begin
if nfip_rst_i = '1' then
jc_tdo_byte_o <= (others => '0');
elsif rising_edge (s_tck) then
jc_tdo_byte_o <= "0000000" & jc_tdo_i;
end if;
end process;
---------------------------------------------------------------------------------------------------
-- Independant Timeout Counter --
---------------------------------------------------------------------------------------------------
-- Instantiation of a WF_decr_counter relying only on the system clock, as an additional
-- way to go back to Idle state, in case any other logic is being stuck. The length of the counter
-- is defined using the slowest bit rate and considering reception of the upper limit of 134 bytes.
Session_Timeout_Counter: WF_decr_counter
generic map(g_counter_lgth => 21)
port map(
uclk_i => uclk_i,
nfip_rst_i => nfip_rst_i,
counter_top => (others => '1'),
counter_load_i => s_idle,
counter_decr_p_i => '1', -- on each uclk tick
counter_o => open,
---------------------------------------------------
counter_is_zero_o => s_session_timedout);
---------------------------------------------------
end architecture rtl;
......
wf_model_constr_decoder.vhd
View file @ caddc235
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- --
-- WF_model_constr_decoder --
-- --
-- |
-- WF_model_constr_decoder |
-- |
---------------------------------------------------------------------------------------------------
-- File WF_model_constr_decoder.vhd
--
-- Description Generation of the nanoFIP output S_ID and decoding of the inputs C_ID and M_ID.
-- The output S_ID0 is a clock with period the double of uclk's period and the S_ID1
-- is the opposite clock (it is '0' when S_ID0 is '1' and '1' when S_ID0 is '0').
-- Each one of the 4 pins of the M_ID and C_ID can be connected to either Vcc, Gnd,
-- S_ID1 or S_ID0. Like this (after 2 uclk periods) the 8 bits of the Model and
-- Constructor words take a value, according to the table: Gnd 00
-- S_ID0 01
-- S_ID1 10
-- Vcc 11
--
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
-- Date 21/01/2011
-- Version v0.03
-- Depends on WF_reset_unit
----------------
-- Last changes
-- 11/09/2009 v0.01 PAS First version
-- 20/08/2010 v0.02 EG S_ID corrected so that S_ID0 is always the opposite of S_ID1
-- "for" loop replaced with signals concatenation;
-- Counter is of c_RELOAD_MID_CID bits; Code cleaned-up
-- 06/10/2010 v0.03 EG generic c_RELOAD_MID_CID removed;
-- counter unit instantiated
-- 01/2011 v0.031 EG loading aftern the 2nd cycle (no need for 3)
-- File WF_model_constr_decoder.vhd |
-- |
-- Description Generation of the nanoFIP output S_ID and decoding of the inputs C_ID and M_ID. |
-- The output S_ID0 is a clock with period the double of uclk's period and the S_ID1 |
-- is the opposite clock (it is '0' when S_ID0 is '1' and '1' when S_ID0 is '0'). |
-- Each one of the 4 pins of the M_ID and C_ID can be connected to either Vcc, Gnd, |
-- S_ID1 or S_ID0. Like this (after 2 uclk periods) the 8 bits of the Model and |
-- Constructor words take a value, according to the table: Gnd 00 |
-- S_ID0 01 |
-- S_ID1 10 |
-- Vcc 11 |
-- |
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 21/01/2011 |
-- Version v0.03 |
-- Depends on WF_reset_unit |
---------------- |
-- Last changes |
-- 11/09/2009 v0.01 PAS First version |
-- 20/08/2010 v0.02 EG S_ID corrected so that S_ID0 is always the opposite of S_ID1 |
-- "for" loop replaced with signals concatenation; |
-- Counter is of c_RELOAD_MID_CID bits; Code cleaned-up |
-- 06/10/2010 v0.03 EG generic c_RELOAD_MID_CID removed; |
-- counter unit instantiated |
-- 01/2011 v0.031 EG loading aftern the 2nd cycle (no need for 3) |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
......@@ -69,9 +69,7 @@ use work.WF_PACKAGE.all; -- definitions of types, constants, entities
--=================================================================================================
-- Entity declaration for WF_model_constr_decoder
--=================================================================================================
entity WF_model_constr_decoder is
port (
entity WF_model_constr_decoder is port(
-- INPUTS
-- nanoFIP User Interface general signal
uclk_i : in std_logic; -- 40 Mhz clock
......@@ -86,12 +84,11 @@ entity WF_model_constr_decoder is
-- OUTPUTS
-- nanoFIP WorldFIP Settings output
select_id_o : out std_logic_vector (1 downto 0); -- Identification selection
s_id_o : out std_logic_vector (1 downto 0); -- Identification selection
-- Signal to the WF_prod_bytes_retriever unit
constr_id_dec_o : out std_logic_vector (7 downto 0); -- Constructor identification decoded
model_id_dec_o : out std_logic_vector (7 downto 0) -- Model identification decoded
);
model_id_dec_o : out std_logic_vector (7 downto 0));-- Model identification decoded
end entity WF_model_constr_decoder;
......@@ -119,7 +116,7 @@ begin
-- and on the second uclk tick, the values of the odd bits move to the registers s_model_stage2/
-- s_constr_stage2, giving place to all the even bits to be loaded to the s_model_stage1/
-- s_constr_stage1. The loaded odd and even values are combined after the 2 periods to give the
-- decoded outputs model_id_dec_o & constr_id_dec_o.
-- decoded outputs model_id_dec_o & constr_id_dec_o.
Model_Constructor_Decoder: process (uclk_i)
begin
......@@ -163,8 +160,8 @@ begin
-- Instantiation of a counter WF_incr_counter
Free_Counter: WF_incr_counter
generic map (g_counter_lgth => 2)
port map (
generic map(g_counter_lgth => 2)
port map(
uclk_i => uclk_i,
reinit_counter_i => nfip_rst_i,
incr_counter_i => '1',
......@@ -175,13 +172,13 @@ begin
---------------------------------------------------------------------------------------------------
-- Concurrent signal assignment for the output select_id_o
-- Concurrent signal assignment for the output s_id_o
select_id_o <= ((not s_counter(0)) & s_counter(0));-- 2 opposite clocks generated using
-- the LSB of the counter
-- uclk_i: |-|__|-|__|-|__|-|__|-|__|-|_
-- S_ID0 : |----|____|----|____|----|___
-- S_ID1 : |____|----|____|----|____|---
s_id_o <= ((not s_counter(0)) & s_counter(0)); -- 2 opposite clocks generated using
-- the LSB of the counter
-- uclk_i: |-|__|-|__|-|__|-|__|-|__|-|_
-- S_ID0 : |----|____|----|____|----|___
-- S_ID1 : |____|----|____|----|____|---
end architecture rtl;
......
wf_package.vhd
View file @ caddc235
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- --
-- WF_package --
-- --
-- |
-- WF_package |
-- |
---------------------------------------------------------------------------------------------------
-- File WF_package.vhd
--
-- Description Definitions of constants, types, entities, functions
-- Author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
-- Date 11/01/2011
-- Version v0.04
----------------
-- Last changes
-- 8/2010 v0.01 EG byte_array of all vars cleaned_up (ex: subs_i removed)
-- 10/2010 v0.02 EG base_addr unsigned(8 downto 0) instead of
-- std_logic_vector (9 downto 0) to simplify calculations; cleaning-up
-- 1/2011 v0.03 EG turnaround times & broadcast var (91h) updated following new specs
-- added DualClkRam
-- 2/2011 v0.04 EG function for manch_encoder; cleaning up of constants+generics
-- added Ctrl bytes for RP_DAT_MSG and RP_DAT_RQ and RP_DAT_RQ_MSG
--
-- File WF_package.vhd |
-- |
-- Description Definitions of constants, types, entities, functions |
-- Author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 11/01/2011 |
-- Version v0.05 |
---------------- |
-- Last changes |
-- 8/2010 v0.01 EG byte_array of all vars cleaned_up (ex: subs_i removed) |
-- 10/2010 v0.02 EG base_addr unsigned(8 downto 0) instead of |
-- std_logic_vector (9 downto 0) to simplify calculations; cleaning-up |
-- 1/2011 v0.03 EG turnaround times & broadcast var (91h) updated following new specs |
-- added DualClkRam |
-- 2/2011 v0.04 EG function for manch_encoder; cleaning up of constants+generics |
-- added CTRL bytes for RP_DAT_MSG and RP_DAT_RQ and RP_DAT_RQ_MSG |
-- 2/2011 v0.05 EG JTAG variables added |
-- |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
......@@ -103,7 +104,7 @@ package WF_package is
---------------------------------------------------------------------------------------------------
-- Constants regarding the Control and PDU_TYPE bytes of ID_DAT and RP_DAT frames --
-- Constants regarding the CTRL and PDU_TYPE bytes of ID_DAT and RP_DAT frames --
---------------------------------------------------------------------------------------------------
constant c_ID_DAT_CTRL_BYTE : std_logic_vector (5 downto 0) := "000011";
......@@ -311,7 +312,7 @@ package WF_package is
prod_or_cons => "10",
broadcast => '0',
base_addr => "---------",
array_lgth => "00000111", -- 8 bytes in total including the Control byte
array_lgth => "00000111", -- 8 bytes in total including the CTRL byte
-- (counting starts from 0;-))
byte_array => (0 => "00" & c_RP_DAT_CTRL_BYTE, 1 => x"50", 2 => x"05",
3 => x"80", 4 => x"03" , 5 => x"00", 6 => x"f0",
......@@ -323,7 +324,7 @@ package WF_package is
prod_or_cons => "10",
broadcast => '0',
base_addr => "---------",
array_lgth => "00001010", -- 11 bytes in total including the Control byte
array_lgth => "00001010", -- 11 bytes in total including the CTRL byte
byte_array => (0 => "00" & c_RP_DAT_CTRL_BYTE, 1 => x"52", 2 => x"08",
3 => x"01", 4 => x"00" , 5 => x"00", 6 => x"ff",
7 => x"ff", 8 => x"00" , 9 => x"00", 10 => x"00",
......@@ -335,7 +336,7 @@ package WF_package is
prod_or_cons => "10",
broadcast => '0',
base_addr => "100000000",
array_lgth => "00000001", -- only the Control and PDU_TYPE bytes are
array_lgth => "00000001", -- only the CTRL and PDU_TYPE bytes are
-- predefined
byte_array => (0 => "00" & c_RP_DAT_CTRL_BYTE, 1 => c_PDU_TYPE_BYTE,
others => x"ff")),
......@@ -346,9 +347,8 @@ package WF_package is
prod_or_cons => "01",
broadcast => '0',
base_addr => "000000000",
array_lgth => "00000001", -- array_lgth & byte_array fields not used
byte_array => (0 => "00" & c_RP_DAT_CTRL_BYTE, 1 => c_PDU_TYPE_BYTE,
others => x"ff")),
array_lgth => "00000000", -- array_lgth & byte_array fields not used
byte_array => (others => x"ff")),
c_VAR_2_INDEX => (var => var_2,
......@@ -356,34 +356,31 @@ package WF_package is
prod_or_cons => "01",
broadcast => '1',
base_addr => "010000000",
array_lgth => "00000001", -- array_lgth & byte_array fields not used
byte_array => (0 => "00" & c_RP_DAT_CTRL_BYTE, 1 => c_PDU_TYPE_BYTE,
others => x"ff")),
array_lgth => "00000000", -- array_lgth & byte_array fields not used
byte_array => (others => x"ff")),
c_VAR_RST_INDEX => (var => var_rst,
hexvalue => x"e0",
prod_or_cons => "01",
broadcast => '1',
base_addr => "---------",
array_lgth => "00000001", -- array_lgth & byte_array fields not used
byte_array => (0 => "00" & c_RP_DAT_CTRL_BYTE, 1 => c_PDU_TYPE_BYTE,
others => x"ff")),
array_lgth => "00000000", -- array_lgth & byte_array fields not used
byte_array => (others => x"ff")),
c_VAR_JC1_INDEX => (var => var_jc1,
hexvalue => x"aa",
prod_or_cons => "01",
broadcast => '0',
base_addr => "000000000",
array_lgth => "00000001", -- array_lgth & byte_array fields not used
byte_array => (0 => "00" & c_RP_DAT_CTRL_BYTE, 1 => c_PDU_TYPE_BYTE,
others => x"ff")),
array_lgth => "00000000", -- array_lgth & byte_array fields not used
byte_array => (others => x"ff")),
c_VAR_JC3_INDEX => (var => var_jc3,
hexvalue => x"ab",
prod_or_cons => "10",
broadcast => '0',
base_addr => "000000000",
array_lgth => "00000001", -- only the Control and PDU_TYPE bytes are
base_addr => "---------",
array_lgth => "00000001", -- only the CTRL and PDU_TYPE bytes are
-- predefined
byte_array => (0 => "00" & c_RP_DAT_CTRL_BYTE, 1 => c_PDU_TYPE_BYTE,
others => x"ff")));
......@@ -512,6 +509,7 @@ package WF_package is
jc_tdi_o : out std_logic;
jc_tck_o : out std_logic;
jc_tdo_byte_o : out std_logic_vector (7 downto 0);
--TP39 : out std_logic;
jc_mem_adr_rd_o : out std_logic_vector (8 downto 0));
-----------------------------------------------------------------
end component WF_jtag_controller;
......@@ -682,7 +680,8 @@ end component WF_rx_osc;
tx_byte_request_accept_p_o : out std_logic;
tx_last_data_byte_p_o : out std_logic;
tx_start_p_o : out std_logic;
prod_cons_byte_index_o : out std_logic_vector (7 downto 0);
prod_byte_index_o : out std_logic_vector (7 downto 0);
cons_byte_index_o : out std_logic_vector (7 downto 0);
prod_data_lgth_o : out std_logic_vector (7 downto 0);
cons_bytes_excess_o : out std_logic;
rx_rst_o : out std_logic;
......@@ -714,25 +713,23 @@ end component WF_rx_osc;
---------------------------------------------------------------------------------------------------
component WF_DualClkRAM_clka_rd_clkb_wr
generic (g_ram_data_lgth : integer;
g_ram_addr_lgth : integer);
component WF_dualram_512x8_clka_rd_clkb_wr
port (
clk_porta_i : in std_logic;
addr_porta_i : in std_logic_vector (g_ram_addr_lgth - 1 downto 0);
addr_porta_i : in std_logic_vector (8 downto 0);
clk_portb_i : in std_logic;
addr_portb_i : in std_logic_vector (g_ram_addr_lgth - 1 downto 0);
data_portb_i : in std_logic_vector (g_ram_data_lgth - 1 downto 0);
addr_portb_i : in std_logic_vector (8 downto 0);
data_portb_i : in std_logic_vector (7 downto 0);
write_en_portb_i : in std_logic;
-----------------------------------------------------------------
data_porta_o : out std_logic_vector (g_ram_data_lgth -1 downto 0));
data_porta_o : out std_logic_vector (7 downto 0));
-----------------------------------------------------------------
end component WF_DualClkRAM_clka_rd_clkb_wr;
end component WF_dualram_512x8_clka_rd_clkb_wr;
---------------------------------------------------------------------------------------------------
component DualClkRam is
component dualram_512x8 is
port (
CLKA : in std_logic;
ADDRA : in std_logic_vector (8 downto 0);
......@@ -747,7 +744,7 @@ end component WF_rx_osc;
DOUTA : out std_logic_vector (7 downto 0);
DOUTB : out std_logic_vector (7 downto 0));
-----------------------------------------------------------------
end component DualClkRam;
end component dualram_512x8;
......@@ -892,7 +889,6 @@ end component WF_rx_osc;
dat_o : out std_logic_vector (15 downto 0);
jc_tms_o : out std_logic;
jc_tdi_o : out std_logic;
TP39 : out std_logic;
jc_tck_o : out std_logic);
-----------------------------------------------------------------
end component nanofip;
......@@ -907,7 +903,7 @@ end component WF_rx_osc;
model_id_i : in std_logic_vector (3 downto 0);
constr_id_i : in std_logic_vector (3 downto 0);
-----------------------------------------------------------------
select_id_o : out std_logic_vector (1 downto 0);
s_id_o : out std_logic_vector (1 downto 0);
model_id_dec_o : out std_logic_vector (7 downto 0);
constr_id_dec_o : out std_logic_vector (7 downto 0));
-----------------------------------------------------------------
......@@ -950,6 +946,8 @@ end component WF_rx_osc;
---------------------------------------------------------------------------------------------------
component WF_prod_data_lgth_calc is
port (
uclk_i : in std_logic;
nfip_rst_i : in std_logic;
slone_i : in std_logic;
nostat_i : in std_logic;
p3_lgth_i : in std_logic_vector (2 downto 0);
......
wf_prod_bytes_retriever.vhd
View file @ caddc235
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- --
-- WF_prod_bytes_retriever --
-- --
-- |
-- WF_prod_bytes_retriever |
-- |
---------------------------------------------------------------------------------------------------
-- File WF_prod_bytes_retriever.vhd
--
-- Description After an ID_DAT frame requesting for a variable to be produced, the unit provides
-- to the WF_tx_serializer unit one by one, all the bytes of data needed for the
-- RP_DAT frame (apart from the FSS, FCS and FES bytes). The coordination of the
-- retreival is done through the WF_engine_control and the signal byte_index_i.
--
-- General structure of a produced RP_DAT frame :
-- ___________ ______ _______ ______ _________________ _______ _______ ___________ _______
-- |____FSS____|_Ctrl_||__PDU__|_LGTH_|_...User-Data..._|_nstat_|__MPS__||____FCS____|__FES__|
--
-- Data provided by the this unit :
-- ______ _______ ______ ________________________________________ _______ _______
-- |_Ctrl_||__PDU__|_LGTH_|_____________..User-Data..______________|_nstat_|__MPS__||
--
-- If the variable to be produced is the
-- o presence : The unit retreives the bytes from the WF_package.
-- No MPS & no nanoFIP status are associated with this variable.
-- ______ _______ ______ ______ ______ ______ ______ ______
-- |_Ctrl_||__PDU__|__05__|__80__|__03__|__00__|__F0__|__00__||
--
--
-- o identification : The unit retreives the Constructor & Model bytes from the
-- WF_model_constr_decoder, and all the rest from the WF_package.
-- No MPS & no nanoFIP status are associated with this variable.
-- ______ _______ ______ ______ ______ ______ ______ _______ ______ ______ ______
-- |_Ctrl_||__PDU__|__08__|__01__|__00__|__00__|_cons_|__mod__|__00__|__00__|__00__||
--
--
-- o var_3 : If the operation is in stand-alone mode, the unit retreives the
-- user-data bytes from the "nanoFIP User Interface, NON-WISHBONE"
-- bus DAT_I. If it is in memory mode, it retreives them from the
-- Produced RAM. The unit retreives the MPS and nanoFIP status
-- bytes from the WF_status_bytes_gen, and the LGTH byte from the
-- WF_prod_data_lgth_calc (inside the WF_engine_control). The
-- rest of the bytes (Ctrl & PDU) come from the WF_package.
-- ______ _______ ______ ________________________________________ _______ _______
-- |_Ctrl_||__PDU__|_LGTH_|_____________..User-Data..______________|_nstat_|__MPS__||
--
--
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
-- Date 04/01/2011
-- Version v0.05
-- Depends on WF_reset_unit
-- WF_wb_controller
-- WF_engine_control
-- WF_prod_permit
-- WF_status_bytes_gen
-- WF_model_constr_dec
----------------
-- Last changes
-- 06/2010 v0.02 EG subs_i is not sent in the RP_DAT frames
-- signal s_wb_we includes the wb_stb_r_edge_p_i
-- cleaner structure
-- 06/2010 v0.03 EG signal s_mem_byte was not in sensitivity list in v0.01! by adding it
-- changes were essential in the timing of the tx (WF_osc, WF_tx,
-- WF_engine_control and the configuration of the memory needed changes)
-- 11/2010 v0.04 EG for simplification, new unit Slone_Data_Sampler created
-- 4/1/2011 v0.05 EG unit renamed from WF_prod_bytes_to_tx to WF_prod_bytes_retriever;
-- input byte_being_sent_p_i added, so that the reseting of status bytes
-- does not pass from the engine; clening-up+commenting
-- 2/2011 v0.051 EG WF_prod_bytes_from_dati unit removed.
-- File WF_prod_bytes_retriever.vhd |
-- |
-- Description After an ID_DAT frame requesting for a variable to be produced, the unit provides |
-- to the WF_tx_serializer unit one by one, all the bytes of data needed for the |
-- RP_DAT frame (apart from the FSS, FCS and FES bytes). The coordination of the |
-- retreival is done through the WF_engine_control and the signal byte_index_i. |
-- |
-- General structure of a produced RP_DAT frame: |
-- ___________ ______ _______ ______ _________________ _______ _______ ___________ _______ |
-- |____FSS____|_CTRL_||__PDU__|_LGTH_|_...User-Data..._|_nstat_|__MPS__||____FCS____|__FES__| |
-- |
-- Data provided by the this unit: |
-- ______ _______ ______ _________________ _______ _______ |
-- |_CTRL_||__PDU__|_LGTH_|_...User-Data..._|_nstat_|__MPS__|| |
-- |
-- If the variable to be produced is the |
-- o presence : The unit retreives the bytes from the WF_package. |
-- No MPS & no nanoFIP status are associated with this variable. |
-- ______ _______ ______ ______ ______ ______ ______ ______ |
-- |_CTRL_||__PDU__|__05__|__80__|__03__|__00__|__F0__|__00__|| |
-- |
-- |
-- o identification: The unit retreives the Constructor & Model bytes from the |
-- WF_model_constr_decoder, & all the rest from the WF_package. |
-- No MPS & no nanoFIP status are associated with this variable. |
-- ______ _______ ______ ______ ______ ______ ______ _______ ______ ______ ______ |
-- |_CTRL_||__PDU__|__08__|__01__|__00__|__00__|_cons_|__mod__|__00__|__00__|__00__|| |
-- |
-- |
-- o var_3 : If the operation is in stand-alone mode, the unit retreives |
-- the user-data bytes from the "nanoFIP User Interface, NON- |
-- WISHBONE" bus DAT_I. If it is in memory mode, it retreives |
-- them from the Produced RAM. The unit retreives the MPS and |
-- nanoFIP status bytes from the WF_status_bytes_gen, and the |
-- LGTH byte from the WF_prod_data_lgth_calc (inside the |
-- WF_engine_control). The rest of the bytes (CTRL & PDU) come |
-- from the WF_package. |
-- ______ _______ ______ ________________________________________ _______ _______ |
-- |_CTRL_||__PDU__|_LGTH_|_____________..User-Data..______________|_nstat_|__MPS__|| |
-- |
-- |
-- o var_jc3 : Regardless of the operational mode or the P3_LGTH, the unit |
-- sends 1 user-data byte coming from the WF_jtag_controller. |
-- The nanoFIP status is always sent regardless of the NOSTAT |
-- input. The MPS, LGTH, CTRL, PDU_TYPE bytes are as before. |
-- |
-- ______ _______ ______ ________ _______ _______ |
-- |_CTRL_||__PDU__|_LGTH_|_jc_tdo_|_nstat_|__MPS__|| |
-- |
-- |
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 04/01/2011 |
-- Version v0.05 |
-- Depends on WF_reset_unit |
-- WF_wb_controller |
-- WF_engine_control |
-- WF_prod_permit |
-- WF_status_bytes_gen |
-- WF_model_constr_dec |
-- WF_jtag_controller |
---------------- |
-- Last changes |
-- 06/2010 v0.02 EG subs_i is not sent in the RP_DAT frames |
-- signal s_wb_we includes the wb_stb_r_edge_p_i |
-- cleaner structure |
-- 06/2010 v0.03 EG signal s_mem_byte was not in sensitivity list in v0.01! by adding it |
-- changes were essential in the timing of the tx (WF_osc, WF_tx, |
-- WF_engine_control and the configuration of the memory needed changes) |
-- 11/2010 v0.04 EG for simplification, new unit Slone_Data_Sampler created |
-- 4/1/2011 v0.05 EG unit renamed from WF_prod_bytes_to_tx to WF_prod_bytes_retriever; |
-- input byte_being_sent_p_i added, so that the reseting of status bytes |
-- does not pass from the engine; clening-up+commenting |
-- 2/2011 v0.051 EG WF_prod_bytes_from_dati unit removed. |
-- 6/2011 v0.051 EG added jc var treatment. |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
......@@ -107,9 +119,7 @@ use work.WF_PACKAGE.all; -- definitions of types, constants, entities
-- Entity declaration for WF_prod_bytes_retriever
--=================================================================================================
entity WF_prod_bytes_retriever is
port (
entity WF_prod_bytes_retriever is port(
-- INPUTS
-- nanoFIP User Interface, General signals
uclk_i : in std_logic; -- 40 MHz clock
......@@ -139,9 +149,9 @@ entity WF_prod_bytes_retriever is
data_lgth_i : in std_logic_vector (7 downto 0); -- # bytes of the Conrol&Data fields
-- of the RP_DAT frame; includes:
-- 1 byte RP_DAT.Control,
-- 1 byte RP_DAT.CTRL,
-- 1 byte RP_DAT.Data.PDU_type,
-- 1 byte RP_DAT.Data.LENGTH
-- 1 byte RP_DAT.Data.LGTH
-- 2-124 bytes of RP_DAT.Data,
-- 1 byte RP_DAT.Data.MPS_status &
-- optionally 1 byte for the
......@@ -162,7 +172,8 @@ entity WF_prod_bytes_retriever is
model_id_dec_i : in std_logic_vector (7 downto 0); -- decoded model id settings
-- Signals from the WF_jtag_controller unit
jc_tdo_byte_i : in std_logic_vector (7 downto 0); -- 8 last JC_TDO bits
jc_tdo_byte_i : in std_logic_vector (7 downto 0); -- sampling of JC_TDO input
-- OUTPUTS
-- Signal to the WF_status_bytes_gen
......@@ -171,9 +182,8 @@ entity WF_prod_bytes_retriever is
-- the delivery of the last one (MPS)
-- Signal to the WF_tx_serializer
byte_o : out std_logic_vector (7 downto 0) -- output byte to be serialized
);
byte_o : out std_logic_vector (7 downto 0));-- output byte to be serialized
end entity WF_prod_bytes_retriever;
......@@ -182,14 +192,19 @@ end entity WF_prod_bytes_retriever;
--=================================================================================================
architecture rtl of WF_prod_bytes_retriever is
-- addressing the memory
signal s_base_addr, s_mem_addr_offset : unsigned (8 downto 0);
signal s_mem_addr_A : std_logic_vector (8 downto 0);
-- index of byte to be sent
signal s_byte_index_d1 : std_logic_vector (7 downto 0);
signal s_byte_index_d_aux : integer range 0 to 15;
-- data bytes
signal s_mem_byte, s_slone_byte : std_logic_vector (7 downto 0);
signal s_slone_bytes : std_logic_vector (15 downto 0);
-- Length byte
signal s_lgth_byte : std_logic_vector (7 downto 0);
--=================================================================================================
-- architecture begin
--=================================================================================================
......@@ -204,13 +219,8 @@ begin
-- Port A is used by the nanoFIP for the readings from the Produced RSM;
-- Port B is connected to the WISHBONE interface for the writings from the user.
Produced_Bytes_From_RAM: WF_DualClkRAM_clka_rd_clkb_wr
generic map (
g_ram_data_lgth => 8, -- 8 bits: length of data word
g_ram_addr_lgth => 9) -- 2^9: depth of Produced ram
-- first 2 bits : identification of memory block
-- remaining 7 : address of a byte inside the blck
port map (
Produced_Bytes_From_RAM: WF_dualram_512x8_clka_rd_clkb_wr
port map(
clk_porta_i => uclk_i, -- 40 MHz clock
addr_porta_i => s_mem_addr_A, -- address of byte to be read from memory
clk_portb_i => wb_clk_i, -- WISHBONE clock
......@@ -253,7 +263,7 @@ begin
---------------------------------------------------------------------------------------------------
-- Bytes Generation --
---------------------------------------------------------------------------------------------------
-- Combinatorial process Bytes_Generation: Generation of bytes for the Control and Data
-- Combinatorial process Bytes_Generation: Generation of bytes for the CTRL and Data
-- fields of an RP_DAT frame: If the variable requested in the ID_DAT is of "produced" type
-- (identification/ presence/ var3) the process prepares accordingly, one by one, bytes of data
-- to be sent. The pointer "s_byte_index_d1" (or "s_byte_index_d_aux") indicates which byte of the
......@@ -274,7 +284,7 @@ begin
-- case: presence variable
-- all the bytes for the RP_DAT.Control and RP_DAT.Data fields are predefined
-- all the bytes for the RP_DAT.CTRL and RP_DAT.Data fields are predefined
-- in the c_VARS_ARRAY matrix.
when var_presence =>
......@@ -309,7 +319,7 @@ begin
-- case: variable 3
-- For a var_3 there is a separation according to the operational mode (stand-alone or memory)
-- In general, few of the bytes are predefined in the c_VARS_ARRAY matrix, wereas the rest come
-- In general, few of the bytes are predefined in the c_VARS_ARRAY matrix, whereas the rest come
-- either from the memory/ DAT_I bus or from wf_status_bytes_generator unit.
when var_3 =>
......@@ -322,7 +332,7 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- The first (Control) and second (PDU_TYPE) bytes to be sent
-- The first (CTRL) and second (PDU_TYPE) bytes to be sent
-- are predefined in the c_VARS_ARRAY matrix of the WF_package
if unsigned(s_byte_index_d1) <= c_VARS_ARRAY(c_VAR_3_INDEX).array_lgth then -- less or eq
......@@ -366,7 +376,7 @@ begin
s_base_addr <= (others => '0'); -- no memory access needed
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- The first (Control) and second (PDU type) bytes to be sent
-- The first (CTRL) and second (PDU_TYPE) bytes to be sent
-- are predefined in the c_VARS_ARRAY matrix of the WF_package
if unsigned(s_byte_index_d1) <= c_VARS_ARRAY(c_VAR_3_INDEX).array_lgth then -- less or eq
......@@ -407,14 +417,17 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- case: jatg produced
-- For ..............
-- case: jtag variable 3
-- For a var_jc3 the 1 user-data byte comes from the wf_jtag_controller unit.
-- The nanoFIP status byte comes from the wf_status_bytes_gen and it is always sent regardless
-- of the NOSTAT input. The rest of the bytes come from the wf_package, wf_data_lgth_calc and
-- the wf_status_bytes_gen.
when var_jc3 =>
s_base_addr <= (others => '0'); -- no memory access needed
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- The first (Control) and second (PDU type) bytes to be sent
-- The first (CTRL) and second (PDU_TYPE) bytes to be sent
-- are predefined in the c_VARS_ARRAY matrix of the WF_package
if unsigned(s_byte_index_d1) <= c_VARS_ARRAY(c_VAR_JC3_INDEX).array_lgth then -- less or eq
......@@ -491,8 +504,8 @@ begin
s_mem_addr_A <= std_logic_vector (s_base_addr + s_mem_addr_offset - 1);
-- address of the byte to be read from memory: base_address(from WF_package) + byte_index_i - 1
-- (the -1 is because the byte_index_i counts also the Control byte, that is not part of the
-- memory; for example when byte_index_i is 3 which means that the Control, PDU_TYPE and Length
-- (the -1 is because the byte_index_i counts also the CTRL byte, that is not part of the
-- memory; for example when byte_index_i is 3 which means that the CTRL, PDU_TYPE and LGTH
-- bytes have preceded and a byte from the memory is now requested, the byte from the memory cell
-- 2 (00000010) has to be retrieved).
......@@ -505,12 +518,12 @@ begin
-- width of 15 bytes
s_lgth_byte <= std_logic_vector (resize((unsigned(data_lgth_i)-2),byte_o'length));
-- represents the RP_DAT.Data.LENGTH byte
-- represents the RP_DAT.Data.LGTH byte
-- it includes the # bytes of user-data
-- (P3_LGTH) plus 1 byte of MPS_status
-- plus 1 byte of nanoFIP_status, if
-- applicable. It does not include the
-- Control byte and itself.
-- CTRL byte and itself.
end architecture rtl;
......
wf_prod_data_lgth_calc.vhd
View file @ caddc235
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- --
-- WF_prod_data_lgth_calc --
-- --
-- |
-- WF_prod_data_lgth_calc |
-- |
---------------------------------------------------------------------------------------------------
-- File WF_prod_data_lgth_calc.vhd
--
-- Description Calculation of the number of bytes, after the FSS and before the FCS, that have
-- to be transferred when a variable is produced (var_pres, var_identif, var_3, var_jc3).
-- In detail the unit adds:
-- o 1 byte RP_DAT.Control,
-- o 1 byte RP_DAT.Data.PDU_TYPE,
-- o 1 byte RP_DAT.Data.Length,
-- o 2-124 bytes RP_DAT.Data.User_Data, defined by the "nanoFIP User Interface,
-- General signal" SLONE and the "nanoFIP WorldFIP Settings" input P3_LGTH
-- o 1 byte RP_DAT.Data.nanoFIP_status, only for a var_3, if the "nanoFIP User
-- Interface General signal" NOSTAT is negated
-- o 1 byte RP_DAT.Data.MPS_status, only for a var_3.
--
--
-- Reminder:
--
-- Produced RP_DAT frame structure :
-- ||--------------------- Data ---------------------||
-- ___________ ______ _______ ______ _________________ _______ _______ ___________ _______
-- |____FSS____|_Ctrl_||__PDU__|_LGTH_|__..User-Data..__|_nstat_|__MPS__||____FCS____|__FES__|
--
-- |-----P3_LGTH-----|
--
--
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
-- Date 09/12/2010
-- Version v0.02
-- Depends on WF_engine_control
----------------
-- Last changes
-- 12/2010 v0.02 EG code cleaned-up+commented
-- File WF_prod_data_lgth_calc.vhd |
-- |
-- Description Calculation of the number of bytes, after the FSS and before the FCS, that have to|
-- be transferred when a variable is produced (var_pres, var_identif, var_3, var_jc3)|
-- In detail, the unit adds-up: |
-- o 1 byte RP_DAT.CTRL, |
-- o 1 byte RP_DAT.Data.PDU_TYPE, |
-- o 1 byte RP_DAT.Data.LGTH, |
-- o 1-124 RP_DAT.Data.User_Data bytes according to the variable type: |
-- - var_pres: 5 bytes |
-- - var_pres: 8 bytes |
-- - var_jc3 : 1 byte |
-- - var_3 : 2-124 bytes defined by the "nanoFIP User Interface,General signal"|
-- SLONE and the "nanoFIP WorldFIP Settings" input P3_LGTH |
-- o 1 byte RP_DAT.Data.nanoFIP_status, always for a var_jc3 |
-- and for a var_3, if the "nanoFIP User |
-- Interface General signal" NOSTAT is negated|
-- o 1 byte RP_DAT.Data.MPS_status, for a var_jc3 and a var_3 |
-- |
-- |
-- Reminder: |
-- |
-- Produced RP_DAT frame structure : |
-- ||--------------------- Data ---------------------|| |
-- ___________ ______ _______ ______ _________________ _______ _______ ___________ _______ |
-- |____FSS____|_CTRL_||__PDU__|_LGTH_|__..User-Data..__|_nstat_|__MPS__||____FCS____|__FES__| |
-- |
-- |-----P3_LGTH-----| |
-- |
-- |
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 09/12/2010 |
-- Version v0.02 |
-- Depends on WF_engine_control |
---------------- |
-- Last changes |
-- 12/2010 v0.02 EG code cleaned-up+commented |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
......@@ -77,10 +82,14 @@ use work.WF_PACKAGE.all; -- definitions of types, constants, entities
-- Entity declaration for WF_prod_data_lgth_calc
--=================================================================================================
entity WF_prod_data_lgth_calc is
port (
entity WF_prod_data_lgth_calc is port(
-- INPUTS
-- nanoFIP User Interface, General signals
uclk_i : in std_logic; -- 40 MHz clock
-- Signal from the WF_reset_unit
nfip_rst_i : in std_logic; -- nanoFIP internal reset
-- nanoFIP WorldFIP Settings
p3_lgth_i : in std_logic_vector (2 downto 0); -- produced var user-data length
......@@ -94,8 +103,8 @@ entity WF_prod_data_lgth_calc is
-- OUTPUT
-- Signal to the WF_engine_control and WF_production units
prod_data_lgth_o : out std_logic_vector (7 downto 0)
);
prod_data_lgth_o : out std_logic_vector (7 downto 0));
end entity WF_prod_data_lgth_calc;
......@@ -143,16 +152,16 @@ begin
-- data length calculation according to the operational mode (memory or stand-alone)
-- in slone mode 2 bytes of user-data are produced (independently of P3_LGTH)
-- to these there should be added: 1 byte Control
-- to these there should be added: 1 byte CTRL
-- 1 byte PDU_TYPE
-- 1 byte Length
-- 1 byte LGTH
-- 1 byte MPS status
-- optionally 1 byte nFIP status
-- in memory mode the signal "s_p3_lgth_decoded" indicates the amount of user-data;
-- to these, there should be added 1 byte Control
-- to these, there should be added 1 byte CTRL
-- 1 byte PDU_TYPE
-- 1 byte Length
-- 1 byte LGTH
-- 1 byte MPS status
-- optionally 1 byte nFIP status
......@@ -180,9 +189,9 @@ begin
-- data length calculation regardless of the operational mode, the P3_LGTH and the NOSTAT
-- 1 byte of data from the JTAG_controller
-- to these there should be added: 1 byte Control
-- to these there should be added: 1 byte CTRL
-- 1 byte PDU_TYPE
-- 1 byte Length
-- 1 byte LGTH
-- 1 byte nFIP status (regardless of the NOSTAT input)
-- 1 byte MPS status
......@@ -198,10 +207,23 @@ begin
end case;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Concurrent signal assignment for the output
-- Registration of the output (coz of slack)
prod_data_lgth_o <= std_logic_vector (s_prod_data_lgth);
Prod_Data_Lgth_Reg: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
prod_data_lgth_o <= (others =>'0');
else
prod_data_lgth_o <= std_logic_vector (s_prod_data_lgth);
end if;
end if;
end process;
end architecture behavior;
......
wf_prod_permit.vhd
View file @ caddc235
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- --
-- WF_prod_permit --
-- --
-- |
-- WF_prod_permit |
-- |
---------------------------------------------------------------------------------------------------
-- File WF_prod_permit.vhd
--
-- Description Generation of the "nanoFIP User Interface, NON_WISHBONE" output signal VAR3_RDY,
-- according to the variable (var_i) that is being treated.
--
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
-- Date 14/1/2011
-- Version v0.01
-- Depends on WF_engine_control
-- WF_reset_unit
----------------
-- Last changes
-- 1/2011 v0.01 EG First version
-- File WF_prod_permit.vhd |
-- |
-- Description Generation of the "nanoFIP User Interface, NON_WISHBONE" output signal VAR3_RDY, |
-- according to the variable (var_i) that is being treated. |
-- |
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 14/1/2011 |
-- Version v0.01 |
-- Depends on WF_engine_control |
-- WF_reset_unit |
---------------- |
-- Last changes |
-- 1/2011 v0.01 EG First version |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
......@@ -58,9 +58,7 @@ use work.WF_PACKAGE.all; -- definitions of types, constants, entities
-- Entity declaration for WF_prod_permit
--=================================================================================================
entity WF_prod_permit is
port (
entity WF_prod_permit is port(
-- INPUTS
-- nanoFIP User Interface, General signals
uclk_i : in std_logic; -- 40 MHz clock
......@@ -74,8 +72,8 @@ entity WF_prod_permit is
-- OUTPUT
-- nanoFIP User Interface, NON-WISHBONE outputs
var3_rdy_o : out std_logic -- signals the user that data can safely be written
);
var3_rdy_o : out std_logic); -- signals the user that data can safely be written
end entity WF_prod_permit;
......@@ -99,9 +97,13 @@ begin
-- corresponding RP_DAT from nanoFIP.
-- Note: A correct ID_DAT frame along with the variable it contained is signaled by the var_i.
-- For produced variables, the signal var_i gets its value (var3, var_presence, var_identif)
-- after the reception of a correct ID_DAT frame (with correct FSS, Control, PDU_TYPE, Length, CRC
-- and FES bytes) and retains it until the end of the transmission of the corresponding RP_DAT.
-- For produced variables, the signal var_i gets its value after the reception of a correct ID_DAT
-- frame (with correct FSS, CTRL, PDU_TYPE, LGTH, CRC and FES bytes) and retains it until the end
-- of the transmission of the corresponding RP_DAT. An example follows:
--
-- frames : ___[ID_DAT,var_3]__[......RP_DAT......]______________[ID_DAT,var_3]___[.....RP_DAT..
-- var_i : var_whatever > < var_3 > < var_whatever > < var_3
-- VAR3_RDY: -------------------|__________________|--------------------------------|___________
VAR_RDY_Generation: process (uclk_i)
begin
......
wf_production.vhd
View file @ caddc235
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- --
-- WF_production --
-- --
-- |
-- WF_production |
-- |
---------------------------------------------------------------------------------------------------
-- File WF_production.vhd
--
-- Description The unit groups the main actions that regard data production.
-- It instantiates the units:
--
-- o WF_prod_bytes_retriever : that retrieves
-- o user-data bytes: from the Produced RAM or the
-- "nanoFIP User Interface, NON-WISHBONE" bus DAT_I,
-- o PDU,Ctrl bytes : from the WF_package
-- o MPS,nFIP status: from the WF_status_bytes_gen
-- o LGTH byte : from the WF_prod_data_lgth_calc
-- and following the signals from the external unit
-- WF_engine_control forwards them to the WF_fd_transmitter
--
-- o WF_status_bytes_gen : that receives information from the WF_consumption unit,
-- the "FIELDRIVE" and "User Interface,NON-WISHBONE" inputs
-- and outputs, and generates the nanoFIP and the MPS
-- status bytes
--
-- o WF_prod_permit : that signals the user that user-data bytes can safely
-- be written to the memory or the DAT_I bus
--
-- ___________________________________________________________
-- | WF_production |
-- | |
-- | _________________________________ |
-- | | | |
-- | | WF_prod_permit | |
-- | |_________________________________| |
-- | |
-- | _________________________________ ________________ |
-- | | | | | |
-- | | WF_prod_bytes_retriever | < | WF_status_bytes| |
-- | | | | _gen | |
-- | |_________________________________| |________________| |
-- |___________________________________________________________|
-- \/
-- ___________________________________________________________
-- | |
-- | WF_fd_transmitter |
-- |___________________________________________________________|
-- \/
-- ___________________________________________________________________
-- 0_____________________________FIELDBUS______________________________O
--
-- Note: In the entity declaration of this unit, below each input signal, we mark
-- which of the instantiated units needs it.
--
--
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
-- Date 11/01/2011
-- Version v0.02
-- Depends on WF_reset_unit
-- WF_consumption
-- WF_engine_control
-- WF_wb_controller
-- WF_model_constr_decoder
----------------
-- Last changes
-- 2/2011 v0.02 EG WF_serializer removed from this unit
-- File WF_production.vhd |
-- |
-- Description The unit groups the main actions that regard data production. |
-- It instantiates the units: |
-- |
-- o WF_prod_bytes_retriever: that retrieves |
-- o user-data bytes: from the Produced RAM or the |
-- "nanoFIP User Interface, NON-WISHBONE" bus DAT_I, |
-- o PDU,CTRL bytes : from the WF_package |
-- o MPS,nFIP status: from the WF_status_bytes_gen |
-- o LGTH byte : from the WF_prod_data_lgth_calc |
-- and following the signals from the external unit, |
-- WF_engine_control,forwards them to the WF_fd_transmitter|
-- |
-- o WF_status_bytes_gen : that receives information from the WF_consumption unit,|
-- the "FIELDRIVE" & "User Interface,NON-WISHBONE" inputs |
-- and outputs, and generates the nanoFIP and the MPS |
-- status bytes |
-- |
-- o WF_prod_permit : that signals the user that user-data bytes can safely |
-- be written to the memory or the DAT_I bus |
-- |
-- ___________________________________________________________ |
-- | WF_production | |
-- | | |
-- | _________________________________ | |
-- | | | | |
-- | | WF_prod_permit | | |
-- | |_________________________________| | |
-- | | |
-- | _________________________________ ________________ | |
-- | | | | | | |
-- | | WF_prod_bytes_retriever | < | WF_status_bytes| | |
-- | | | | _gen | | |
-- | |_________________________________| |________________| | |
-- |___________________________________________________________| |
-- \/ |
-- ___________________________________________________________ |
-- | | |
-- | WF_fd_transmitter | |
-- |___________________________________________________________| |
-- \/ |
-- ___________________________________________________________________ |
-- 0_____________________________FIELDBUS______________________________O |
-- |
-- Note: In the entity declaration of this unit, below each input signal, we mark |
-- which of the instantiated units needs it. |
-- |
-- |
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 6/2011 |
-- Version v0.03 |
-- Depends on WF_reset_unit |
-- WF_consumption |
-- WF_engine_control |
-- WF_wb_controller |
-- WF_model_constr_decoder |
-- WF_jtag_controller |
---------------- |
-- Last changes |
-- 2/2011 v0.02 EG WF_serializer removed from this unit |
-- 6/2011 v0.03 EG added WF_jtag_controller+handling |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
......@@ -105,9 +107,7 @@ use work.WF_PACKAGE.all; -- definitions of types, constants, entities
-- Entity declaration for WF_production
--=================================================================================================
entity WF_production is
port (
entity WF_production is port(
-- INPUTS
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- nanoFIP User Interface, General signals
......@@ -211,9 +211,8 @@ entity WF_production is
r_fcser_o : out std_logic;
u_pacer_o : out std_logic;
r_tler_o : out std_logic;
var3_rdy_o : out std_logic
var3_rdy_o : out std_logic);
);
end entity WF_production;
......@@ -226,6 +225,7 @@ architecture struc of WF_production is
signal s_rst_status_bytes_p : std_logic;
signal s_nfip_stat, s_mps : std_logic_vector (7 downto 0);
--=================================================================================================
-- architecture begin
--=================================================================================================
......@@ -239,7 +239,7 @@ begin
-- Instantiation of the WF_prod_permit unit
production_VAR3_RDY_generation: WF_prod_permit
port map (
port map(
uclk_i => uclk_i,
nfip_rst_i => nfip_rst_i,
var_i => var_i,
......@@ -256,7 +256,7 @@ begin
-- Instantiation of the WF_prod_bytes_retriever unit
production_bytes_retriever : WF_prod_bytes_retriever
port map (
port map(
uclk_i => uclk_i,
model_id_dec_i => model_id_dec_i,
constr_id_dec_i => constr_id_dec_i,
......@@ -290,7 +290,7 @@ begin
-- Instantiation of the WF_status_bytes_gen unit
production_status_bytes_generator : WF_status_bytes_gen
port map (
port map(
uclk_i => uclk_i,
nfip_rst_i => nfip_rst_i,
slone_i => slone_i,
......
wf_reset_unit.vhd
View file @ caddc235
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- --
-- WF_reset_unit --
-- --
-- |
-- WF_reset_unit |
-- |
---------------------------------------------------------------------------------------------------
-- File WF_reset_unit.vhd
--
-- Description The unit is responsible for the generation of the:
--
-- o nanoFIP internal reset: that resets all nanoFIP's logic, apart from the WISHBONE
-- It is asserted after a proper assertion of the "nanoFIP User Interface General
-- signal" RSTIN (synchronized to the uclk), or
-- after the reception of a valid var_rst with its 1st application-data byte
-- containing the station's address. In those cases, the signal stays active for
-- 2 uclk cycles.
-- It is also asserted during the activation of the "nanoFIP User Interface
-- General signal" RSTPON. In this case it stays active for as long as the
-- RSTPON is active.
-- __________
-- RSTIN | | \ \
-- ________| FSM |_______ \ \
-- | RSTIN | \ \
-- |__________| \ \
-- __________ | \
-- rst_nFIP_and_FD_p | | | | nFIP_rst
-- ________| FSM |________ |OR | _______________
-- | var_rst | | |
-- |__________| | /
-- / /
-- RSTPON / /
-- __________________________ / /
-- / /
--
--
-- o FIELDRIVE reset: nanoFIP FIELDRIVE output FD_RSTN
-- Same as the nanoFIP internal reset, it can be activated by the RSTIN,
-- a var_rst or the RSTPON. Regarding the activation time, for the first
-- two cases (RSTIN, var_rst) it stays asserted for 4 FD_TXCK cycles whereas in
-- the case of the RSTPON, it stays active for as long as the RSTPON is active.
--
-- __________
-- RSTIN | | \ \
-- ________| FSM |_______ \ \
-- | RSTIN | \ \
-- |__________| \ \
-- __________ | \
-- rst_nFIP_and_FD_p | | | | FD_RSTN
-- ________| FSM |________ |OR | _______________
-- | var_rst | | |
-- |__________| | /
-- / /
-- RSTPON / /
-- __________________________ / /
-- / /
--
-- o reset to the external logic: nanoFIP User Interface, General signal RSTON
-- It is asserted after the reception of a valid var_rst with its 2nd data byte
-- containing the station's address. It stays active for 8 uclk cycles.
-- _________
-- assert_RSTON_p | | RSTON
-- ________| FSM |_________________________________
-- | var_rst |
-- |__________|
--
--
-- o nanoFIP internal reset for the WISHBONE logic:
-- It is asserted after the assertion of the "nanoFIP User Interface, WISHBONE
-- Slave" input RST_I (not synchronized, to comply with with WISHBONE rule 3.15)
-- or of the "nanoFIP User Interface General signal" RSTPON.
-- It stays asserted for as long as the RST_I or RSTPON stay asserted.
--
-- RSTPON
-- __________________________ \ \
-- \ \ wb_rst
-- RST_I |OR|____________________
-- __________________________ / /
-- / /
--
--
-- o The input signal RSTIN is considered only if it has been active for >8 uclk cycles
-- o The pulses rst_nFIP_and_FD_p and assert_RSTON_p come from the WF_cons_outcome unit
-- only after the sucessful validation of the frame structure and of the application-
-- data bytes of a var_rst; in this unit they are used here directly,
-- without any handling.
-- o The Power On Reset signal is used directly, without any handling.
-- --->>Still missing the synchronization with the uclk and wb_clk of the falling edge
-- of RSTPON
--
-- The unit implements 2 state machines: one for resets coming from RSTIN
-- and one for resets coming from a var_rst.
--
--
-- Authors Erik van der Bij (Erik.van.der.Bij@cern.ch)
-- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
-- Date 21/01/2011
-- Version v0.03
-- Depends on WF_cons_bytes_processor
----------------
-- Last changes
-- 07/2009 v0.01 EB First version
-- 08/2010 v0.02 EG checking of bytes1 and 2 of reset var added
-- fd_rstn_o, nFIP_rst_o enabled only if rstin has been active for>4 uclk
-- 01/2011 v0.03 EG PoR added; signals assert_RSTON_p_i & rst_nFIP_and_FD_p_i are inputs
-- treated in the wf_cons_outcome; 2 state machines created; clean-up
-- PoR also for internal WISHBONE resets
-- 02/2011 v0.031 EG state nfip_off_fd_off added
-- File WF_reset_unit.vhd |
-- |
-- Description The unit is responsible for the generation of the: |
-- |
-- o nanoFIP internal reset: that resets all nanoFIP's logic, apart from WISHBONE. |
-- It is asserted after a proper assertion of the "nanoFIP User Interface General |
-- signal" RSTIN (synchronized to the uclk), or |
-- after the reception of a valid var_rst with its 1st application-data byte |
-- containing the station's address. In both cases, the signal stays active for |
-- 2 uclk cycles. |
-- It is also asserted during the activation of the "nanoFIP User Interface |
-- General signal" RSTPON. In this case it stays active for as long as the |
-- RSTPON is active. |
-- __________ |
-- RSTIN | | \ \ |
-- ________| FSM |_______ \ \ |
-- | RSTIN | \ \ |
-- |__________| \ \ |
-- __________ | \ |
-- rst_nFIP_and_FD_p | | | | nFIP_rst |
-- ________| FSM |________ |OR | _______________ |
-- | var_rst | | | |
-- |__________| | / |
-- / / |
-- RSTPON / / |
-- __________________________ / / |
-- / / |
-- |
-- |
-- o FIELDRIVE reset: nanoFIP FIELDRIVE output FD_RSTN |
-- Same as the nanoFIP internal reset, it can be activated by the RSTIN, |
-- the var_rst or the RSTPON. Regarding the activation time, for the first |
-- two cases (RSTIN, var_rst) it stays asserted for 4 FD_TXCK cycles whereas in |
-- the case of the RSTPON, it stays active for as long as the RSTPON is active. |
-- |
-- __________ |
-- RSTIN | | \ \ |
-- ________| FSM |_______ \ \ |
-- | RSTIN | \ \ |
-- |__________| \ \ |
-- __________ | \ |
-- rst_nFIP_and_FD_p | | | | FD_RSTN |
-- ________| FSM |________ |OR | _______________ |
-- | var_rst | | | |
-- |__________| | / |
-- / / |
-- RSTPON / / |
-- __________________________ / / |
-- / / |
-- |
-- o reset to the external logic: "nanoFIP User Interface, General signal" RSTON |
-- It is asserted after the reception of a valid var_rst with its 2nd data byte |
-- containing the station's address. It stays active for 8 uclk cycles. |
-- _________ |
-- assert_RSTON_p | | RSTON |
-- ________| FSM |_________________________________ |
-- | var_rst | |
-- |__________| |
-- |
-- o nanoFIP internal reset for the WISHBONE logic: |
-- It is asserted after the assertion of the "nanoFIP User Interface, WISHBONE |
-- Slave" input RST_I (not synchronized, to comply with with WISHBONE rule 3.15) |
-- or of the "nanoFIP User Interface General signal" RSTPON. |
-- It stays asserted for as long as the RST_I or RSTPON stay asserted. |
-- |
-- RSTPON |
-- __________________________ \ \ |
-- \ \ wb_rst |
-- RST_I |OR|____________________ |
-- __________________________ / / |
-- / / |
-- |
-- Notes: |
-- - The input signal RSTIN is considered only if it has been active for >8 uclk cycles|
-- - The pulses rst_nFIP_and_FD_p and assert_RSTON_p come from the WF_cons_outcome |
-- unit only after the sucessful validation of the frame structure and of the |
-- application-data bytes of a var_rst; in this unit they are used here directly, |
-- without any handling. |
-- - The RSTPON (Power On Reset generated with an RC circuit) removal is synchronized |
-- with both uclk and wb_clk. |
-- |
-- The unit implements 2 state machines: one for resets coming from RSTIN |
-- and one for resets coming from a var_rst. |
-- |
-- |
-- Authors Erik van der Bij (Erik.van.der.Bij@cern.ch) |
-- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 21/01/2011 |
-- Version v0.03 |
-- Depends on WF_cons_bytes_processor |
---------------- |
-- Last changes |
-- 07/2009 v0.01 EB First version |
-- 08/2010 v0.02 EG checking of bytes1 and 2 of reset var added |
-- fd_rstn_o, nFIP_rst_o enabled only if rstin has been active for>4 uclk |
-- 01/2011 v0.03 EG PoR added; signals assert_RSTON_p_i & rst_nFIP_and_FD_p_i are inputs |
-- treated in the wf_cons_outcome; 2 state machines created; clean-up |
-- PoR also for internal WISHBONE resets |
-- 02/2011 v0.031 EG state nfip_off_fd_off added |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
......@@ -145,8 +143,7 @@ use work.WF_PACKAGE.all; -- definitions of types, constants, entities
--=================================================================================================
-- Entity declaration for WF_reset_unit
--=================================================================================================
entity WF_reset_unit is
port (
entity WF_reset_unit is port(
-- INPUTS
-- nanoFIP User Interface General signals
uclk_i : in std_logic; -- 40 MHz clock
......@@ -180,8 +177,8 @@ entity WF_reset_unit is
rston_o : out std_logic; -- reset output, active low
-- nanoFIP FIELDRIVE output
fd_rstn_o : out std_logic -- FIELDRIVE reset, active low
);
fd_rstn_o : out std_logic); -- FIELDRIVE reset, active low
end entity WF_reset_unit;
......@@ -190,21 +187,30 @@ end entity WF_reset_unit;
--=================================================================================================
architecture rtl of WF_reset_unit is
-- RSTIN and RSTPON synchronizers
signal s_rsti_synch : std_logic_vector (2 downto 0);
signal s_wb_por_synch, s_u_por_synch : std_logic_vector (1 downto 0);
-- FSM for RSTIN
type rstin_st_t is (idle, rstin_eval, nfip_on_fd_on, nfip_off_fd_on, nfip_off_fd_off);
signal rstin_st, nx_rstin_st : rstin_st_t;
-- RSTIN counter
signal s_rstin_c, s_var_rst_c : unsigned (c_2_PERIODS_COUNTER_LGTH-1 downto 0);
signal s_rstin_c_reinit, s_rstin_c_is_four, s_rstin_c_is_ten, s_rstin_c_is_full : std_logic;
-- resets generated after a RSTIN
signal s_rstin_nfip, s_rstin_fd : std_logic;
-- FSM for var_rst
type var_rst_st_t is (var_rst_idle, var_rst_rston_on, var_rst_nfip_on_fd_on_rston_on,
var_rst_nfip_off_fd_on_rston_on, var_rst_nfip_on_fd_on,
var_rst_nfip_off_fd_on_rston_off);
signal var_rst_st, nx_var_rst_st : var_rst_st_t;
signal rstin_st, nx_rstin_st : rstin_st_t;
signal s_rstin_c, s_var_rst_c : unsigned (c_2_PERIODS_COUNTER_LGTH-1 downto 0);
signal s_rstin_c_reinit, s_rstin_c_is_four, s_rstin_c_is_ten, s_rstin_c_is_full : std_logic;
-- var_rst counter
signal s_var_rst_c_reinit, s_var_rst_c_is_two, s_var_rst_c_is_eight, s_var_rst_c_is_full : std_logic;
signal s_rstin_nfip, s_rstin_fd, s_var_rst_fd, s_var_rst_nfip, s_rston : std_logic;
-- resets generated after a var_rst
signal s_var_rst_fd, s_var_rst_nfip, s_rston : std_logic;
-- info needed to define the length of the FD_RSTN
signal s_transm_period : unsigned (c_PERIODS_COUNTER_LGTH - 1 downto 0);
signal s_txck_four_periods : unsigned (c_2_PERIODS_COUNTER_LGTH-1 downto 0);
signal s_u_por_ff1, s_u_por, s_wb_por_ff1, s_wb_por : std_logic;
signal s_rsti_synch : std_logic_vector (2 downto 0);
--=================================================================================================
-- architecture begin
......@@ -226,33 +232,29 @@ begin
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Synchronization of the de-assertion of the Power On reset, with the wb_clk.
-- Synchronization of the Power On Reset removal, with the wb_clk.
-- The second flip-flop is used to remove metastabilities.
PoR_wb_clk_Synchronizer: process (wb_clk_i, rstpon_a_i)
begin
if rstpon_a_i = '0' then
s_wb_por_ff1 <= '1';
s_wb_por <= '1';
s_wb_por_synch <= (others => '1');
elsif rising_edge (wb_clk_i) then
s_wb_por_ff1 <= '0';
s_wb_por <= s_wb_por_ff1;
s_wb_por_synch <= s_wb_por_synch(0) & '0';
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Synchronization of the de-assertion of the Power On reset, with the uclk.
-- Synchronization of the Power On Reset removal, with the uclk.
-- The second flip-flop is used to remove metastabilities.
PoR_uclk_Synchronizer: process (uclk_i, rstpon_a_i)
begin
if rstpon_a_i = '0' then
s_u_por_ff1 <= '1';
s_u_por <= '1';
s_u_por_synch <= (others => '1');
elsif rising_edge (uclk_i) then
s_u_por_ff1 <= '0';
s_u_por <= s_u_por_ff1;
s_u_por_synch <= s_u_por_synch(0) & '0';
end if;
end process;
......@@ -290,7 +292,7 @@ begin
RSTIN_FSM_Sync: process (uclk_i)
begin
if rising_edge (uclk_i) then
if s_u_por = '1' or rst_nFIP_and_FD_p_i = '1' then
if s_u_por_synch(1) = '1' or rst_nFIP_and_FD_p_i = '1' then
rstin_st <= idle;
else
rstin_st <= nx_rstin_st;
......@@ -433,8 +435,8 @@ begin
-- Instantiation of a WF_incr_counter: the counter counts from 0 to 4 FD_TXCK.
RSTIN_free_counter: WF_incr_counter
generic map (g_counter_lgth => c_2_PERIODS_COUNTER_LGTH)
port map (
generic map(g_counter_lgth => c_2_PERIODS_COUNTER_LGTH)
port map(
uclk_i => uclk_i,
reinit_counter_i => s_rstin_c_reinit,
incr_counter_i => '1',
......@@ -472,7 +474,7 @@ RSTIN_free_counter: WF_incr_counter
Resets_after_a_var_rst_synch: process (uclk_i)
begin
if rising_edge (uclk_i) then
if s_u_por = '1' or s_rstin_nfip = '1' then
if s_u_por_synch(1) = '1' or s_rstin_nfip = '1' then
var_rst_st <= var_rst_idle;
else
var_rst_st <= nx_var_rst_st;
......@@ -579,7 +581,7 @@ RSTIN_free_counter: WF_incr_counter
when var_rst_idle =>
s_var_rst_c_reinit <= '1'; -- counter initialized
s_rston <= '0';
s_rston <= '1';
s_var_rst_nfip <= '0';
s_var_rst_fd <= '0';
......@@ -588,7 +590,7 @@ RSTIN_free_counter: WF_incr_counter
s_var_rst_c_reinit <= '0'; -- counting 8 uclk cycles
-------------------------------------
s_rston <= '1'; -- RSTON active
s_rston <= '0'; -- RSTON active
-------------------------------------
s_var_rst_nfip <= '0';
s_var_rst_fd <= '0';
......@@ -598,7 +600,7 @@ RSTIN_free_counter: WF_incr_counter
s_var_rst_c_reinit <= '0'; -- counting 2 uclk cycles
-------------------------------------
s_rston <= '1'; -- RSTON active
s_rston <= '0'; -- RSTON active
s_var_rst_nfip <= '1'; -- nFIP internal active
s_var_rst_fd <= '1'; -- FIELDRIVE active
-------------------------------------
......@@ -609,7 +611,7 @@ RSTIN_free_counter: WF_incr_counter
s_var_rst_nfip <= '0';
-------------------------------------
s_rston <= '1'; -- RSTON active
s_rston <= '0'; -- RSTON active
s_var_rst_fd <= '1'; -- FIELDRIVE active
-------------------------------------
......@@ -617,7 +619,7 @@ RSTIN_free_counter: WF_incr_counter
when var_rst_nfip_on_fd_on =>
s_var_rst_c_reinit <= '0'; -- counting 2 uclk cycles
s_rston <= '0';
s_rston <= '1';
-------------------------------------
s_var_rst_nfip <= '1'; -- nFIP internal active
s_var_rst_fd <= '1'; -- FIELDRIVE active
......@@ -627,7 +629,7 @@ RSTIN_free_counter: WF_incr_counter
when var_rst_nfip_off_fd_on_rston_off =>
s_var_rst_c_reinit <= '0'; -- counting 4 FD_TXCK cycles
s_rston <= '0';
s_rston <= '1';
s_var_rst_nfip <= '0';
-------------------------------------
s_var_rst_fd <= '1'; -- FIELDRIVE active
......@@ -637,7 +639,7 @@ RSTIN_free_counter: WF_incr_counter
when others =>
s_var_rst_c_reinit <= '1'; -- no counting
s_rston <= '0';
s_rston <= '1';
s_var_rst_nfip <= '0';
s_var_rst_fd <= '0';
......@@ -653,8 +655,8 @@ RSTIN_free_counter: WF_incr_counter
-- from 0 to 4 * FD_TXCK, if rst_nFIP_and_FD_p has been activated.
free_counter: WF_incr_counter
generic map (g_counter_lgth => c_2_PERIODS_COUNTER_LGTH)
port map (
generic map(g_counter_lgth => c_2_PERIODS_COUNTER_LGTH)
port map(
uclk_i => uclk_i,
reinit_counter_i => s_var_rst_c_reinit,
incr_counter_i => '1',
......@@ -674,27 +676,33 @@ free_counter: WF_incr_counter
-- Output Signals --
---------------------------------------------------------------------------------------------------
wb_rst_o <= rst_i or s_wb_por;
nFIP_rst_o <= s_rstin_nfip or s_var_rst_nfip or s_u_por;
wb_rst_o <= rst_i or s_wb_por_synch(1);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
nFIP_rst_o <= s_rstin_nfip or s_var_rst_nfip or s_u_por_synch(1);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Flip-flop with asynchronous reset to be sure that whenever nanoFIP is reset the user is not
RSTON_Buffering: process (uclk_i, s_u_por, s_rstin_nfip, s_var_rst_nfip)
RSTON_Buffering: process (uclk_i, s_u_por_synch(1), s_rstin_nfip, s_var_rst_nfip)
begin
if s_rstin_nfip = '1' or s_var_rst_nfip = '1' or s_u_por = '1' then
if s_rstin_nfip = '1' or s_var_rst_nfip = '1' or s_u_por_synch(1) = '1' then
rston_o <= '1';
elsif rising_edge (uclk_i) then
rston_o <= not s_rston;
rston_o <= s_rston;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- FIELDRIVE reset
FD_RST_Buffering: process (uclk_i)
begin
if rising_edge (uclk_i) then
fd_rstn_o <= not (s_rstin_fd or s_var_rst_fd or s_u_por);
fd_rstn_o <= not (s_rstin_fd or s_var_rst_fd or s_u_por_synch(1));
end if;
end process;
end architecture rtl;
--=================================================================================================
-- architecture end
......
wf_rx_deglitcher.vhd
View file @ caddc235
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- --
-- WF_rx_deglitcher --
-- --
-- |
-- WF_rx_deglitcher |
-- |
---------------------------------------------------------------------------------------------------
-- File WF_rx_deglitcher.vhd
--
-- Description The unit applies a glitch filter to the nanoFIP FIELDRIVE input FD_RXD.
-- It is capable of cleaning glitches up to c_DEGLITCH_THRESHOLD uclk ticks long.
--
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
-- Date 14/02/2011
-- Version v0.03
-- Depends on WF_reset_unit
----------------
-- Last changes
-- 07/08/2009 v0.01 PAS Entity Ports added, start of architecture content
-- 23/08/2010 v0.02 EG code cleaned-up+commented
-- 14/02/2011 v0.03 EG complete change, no dependency on osc;
-- fd_rxd deglitched right at reception
-- File WF_rx_deglitcher.vhd |
-- |
-- Description The unit applies a glitch filter to the nanoFIP FIELDRIVE input FD_RXD. |
-- It is capable of cleaning glitches up to c_DEGLITCH_THRESHOLD uclk ticks long. |
-- |
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 14/02/2011 |
-- Version v0.03 |
-- Depends on WF_reset_unit |
---------------- |
-- Last changes |
-- 07/08/2009 v0.01 PAS Entity Ports added, start of architecture content |
-- 23/08/2010 v0.02 EG code cleaned-up+commented |
-- 14/02/2011 v0.03 EG complete change, no dependency on osc; |
-- fd_rxd deglitched right at reception |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
......@@ -60,9 +60,7 @@ use work.WF_PACKAGE.all; -- definitions of types, constants, entities
-- Entity declaration for WF_rx_deglitcher
--=================================================================================================
entity WF_rx_deglitcher is
port(
entity WF_rx_deglitcher is port(
-- INPUTS
-- nanoFIP User Interface general signal
uclk_i : in std_logic; -- 40 MHz clock
......@@ -78,8 +76,8 @@ entity WF_rx_deglitcher is
-- Signals to the WF_rx_deserializer unit
fd_rxd_filt_o : out std_logic; -- filtered output signal
fd_rxd_filt_edge_p_o : out std_logic; -- indicates an edge on the filtered signal
fd_rxd_filt_f_edge_p_o : out std_logic -- indicates a falling edge on the filtered signal
);
fd_rxd_filt_f_edge_p_o : out std_logic);-- indicates a falling edge on the filtered signal
end WF_rx_deglitcher;
......@@ -94,13 +92,17 @@ architecture rtl of WF_rx_deglitcher is
signal s_fd_rxd_filt_r_edge_p, s_fd_rxd_filt_f_edge_p : std_logic;
signal s_filt_c : unsigned (3 downto 0);
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
---------------------------------------------------------------------------------------------------
-- FD_RXD synchronization --
---------------------------------------------------------------------------------------------------
-- Synchronous process FD_RXD_synchronizer: Synchronization of the nanoFIP FIELDRIVE input
-- FD_RXD to the uclk, using a set of 2 registers.
......@@ -117,7 +119,12 @@ begin
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
---------------------------------------------------------------------------------------------------
-- Deglitching --
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- Synchronous process FD_RXD_deglitcher: the output signal s_fd_rxd_filt is updated only
-- after the accumulation of a sufficient (c_DEGLITCH_THRESHOLD + 1) amount of identical bits.
-- The signal is therefore cleaned of any glitches up to c_DEGLITCH_THRESHOLD uclk ticks long.
......@@ -157,7 +164,6 @@ begin
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- Concurrent signal assignments
......
wf_rx_deserializer.vhd
View file @ caddc235
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- --
-- WF_rx_deserializer --
-- --
-- |
-- WF_rx_deserializer |
-- |
---------------------------------------------------------------------------------------------------
-- File WF_rx_deserializer.vhd
--
-- Description De-serialization of the "nanoFIP FIELDRIVE" input signal FD_RXD and construction
-- of bytes of data to be provided to:
-- o the WF_engine_control unit, for the contents of ID_DAT frames
-- o the WF_cons_bytes_processor unit, for the contents of consumed RP_DAT frames.
-- The unit is also responsible for the identification of the FSS and FES fields of
-- ID_DAT and RP_DAT frames and the verification of their FCS.
-- At the end of a frame (FES detection) either the fss_crc_fes_ok_p_o pulse
-- is assserted, indicating a frame with with correct FSS, CRC and FES
-- or the pulse crc_wrong_p_o is asserted indicating an error on the CRC.
-- After the reception of an ID_DAT frame asking for a variable to be produced, the
-- wf_engine_control keeps the unit reset until the end of the production. Moreover,
-- if a FES is not detected after the reception of more than 8 bytes for an ID_DAT
-- or more than 133 bytes for a RP_DAT the unit is reset by the wf_engine_control.
--
-- Remark: We refer to
-- o a significant edge : for the edge of a manch. encoded bit
-- (bit 0: _|-, bit 1: -|_).
--
-- o a transition : for the moment in between two adjacent bits, that
-- may or may not result in an edge (eg. a 0 followed by a 0 will give an edge
-- _|-|_|-, but a 0 followed by a 1 will not _|--|_ ).
--
-- o the sampling of a manch. bit : for the moments when a manch. encoded bit should
-- be sampled, before and after a significant edge.
--
-- o the sampling of a bit : for the sampling of only the 1st part,
-- before the transition.
--
-- Example:
-- bits : 0 1
-- manch. encoded : _|- -|_
-- significant edge : ^ ^
-- transition : ^
-- sample_manch_bit_p : ^ ^ ^ ^
-- sample_bit_p : ^ ^ (this sampling will give the 0 and the 1)
--
--
-- Reminder of the consumed RP_DAT frame structure:
-- _______ _______ ______ _______ ______ ________________ _______ ___________ _______
-- |__PRE__|__FSD__|_Ctrl_||__PDU__|_LGTH_|_..ApplicData.._|__MPS__||____FCS____|__FES__|
--
--
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
-- Date 15/02/2011
-- Version v0.05
-- Depends on WF_reset_unit
-- WF_rx_osc
-- WF_rx_deglitcher
-- WF_engine_control
----------------
-- Last changes
-- 09/2009 v0.01 PAS First version
-- 10/2010 v0.02 EG state switch_to_deglitched added;
-- output signal rx_osc_rst_o added; signals renamed;
-- state machine rewritten (moore style);
-- units WF_rx_manch_code_check and Incoming_Bits_Index created;
-- each manch bit of FES checked (bf was just each bit, so any D5 was FES)
-- code cleaned-up + commented.
-- 12/2010 v0.03 EG CRC_ok pulse transfered 16 bits later to match the FES;
-- like this we confirm that the CRC_ok_p arrived just before the FES,
-- and any 2 bytes that could by chanche be seen as CRC, are neglected.
-- FSM data_field_byte state: redundant code removed:
-- "s_fes_wrong_bit = '1' and s_manch_code_viol_p = '1' then idle"
-- code(more!)cleaned-up
-- 01/2011 v0.04 EG changed way of detecting the FES to be able to detect a FES even if
-- bytes with size different than 8 have preceeded.
-- crc_wrong_p_o replaced the crc_wrong_p_o.
-- 02/2011 v0.05 EG changed crc pulse transfer; removed switch to deglitch state
-- s_fes_detected removed and s_byte_ready_p_d1; if bytes arrive with
-- bits not x8, the fss_crc_fes_ok_p_o stays 0 (bc of s_byte_ready_p_d1)
-- and the crc_wrong_p_o is asserted (bc of s_sample_manch_bit_p_d1);
-- unit reset during production;
-- check for code vilations completely removed!
-- File WF_rx_deserializer.vhd |
-- |
-- Description De-serialization of the deglitched "nanoFIP FIELDRIVE" input signal FD_RXD and |
-- construction of bytes of data to be provided to: |
-- o the WF_engine_control unit, for the contents of ID_DAT frames |
-- o the WF_consumption unit, for the contents of consumed RP_DAT frames. |
-- The unit is also responsible for the identification of the FSS and FES fields of |
-- ID_DAT and RP_DAT frames and the verification of their CRC. |
-- At the end of a frame (FES detection) either the fss_crc_fes_ok_p_o pulse |
-- is assserted, indicating a frame with with correct FSS, CRC and FES |
-- or the pulse crc_wrong_p_o is asserted indicating an error on the CRC. |
-- If a FES is not detected after the reception of more than 8 bytes for an ID_DAT |
-- or more than 133 bytes for a RP_DAT the unit is reset by the wf_engine_control. |
-- The unit also remains reset during data production. |
-- |
-- Remark: We refer to |
-- o a significant edge : for the edge of a manch. encoded bit |
-- (bit 0: _|-, bit 1: -|_). |
-- |
-- o a transition : for the moment in between two adjacent bits, that|
-- may or may not result in an edge (eg. a 0 followed by a 0 will give an edge: |
-- _|-|_|-, but a 0 followed by a 1 will not: _|--|_ ). |
-- |
-- o the sampling of a manch. bit: for the moments when a manch. encoded bit should |
-- be sampled, before and after a significant edge. |
-- |
-- o the sampling of a bit : for the sampling of only the 1st part, |
-- before the transition. |
-- |
-- Example: |
-- bits : 0 1 |
-- manch. encoded : _|- -|_ |
-- significant edge : ^ ^ |
-- transition : ^ |
-- sample_manch_bit_p: ^ ^ ^ ^ |
-- sample_bit_p : ^ ^ (this sampling will give the 0 and the 1) |
-- |
-- |
-- Reminder of the consumed RP_DAT frame structure: |
-- _______ _______ ______ _______ ______ ________________ _______ ___________ _______ |
-- |__PRE__|__FSD__|_CTRL_||__PDU__|_LGTH_|_..ApplicData.._|__MPS__||____FCS____|__FES__| |
-- |
-- |
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 15/02/2011 |
-- Version v0.05 |
-- Depends on WF_reset_unit |
-- WF_rx_osc |
-- WF_rx_deglitcher |
-- WF_engine_control |
---------------- |
-- Last changes |
-- 09/2009 v0.01 PAS First version |
-- 10/2010 v0.02 EG state switch_to_deglitched added; |
-- output signal rx_osc_rst_o added; signals renamed; |
-- state machine rewritten (moore style); |
-- units WF_rx_manch_code_check and Incoming_Bits_Index created; |
-- each manch bit of FES checked (bf was just each bit, so any D5 was FES) |
-- code cleaned-up + commented. |
-- 12/2010 v0.03 EG CRC_ok pulse transfered 16 bits later to match the FES; |
-- like this we confirm that the CRC_ok_p arrived just before the FES, |
-- and any 2 bytes that could by chanche be seen as CRC, are neglected. |
-- FSM data_field_byte state: redundant code removed: |
-- "s_fes_wrong_bit = '1' and s_manch_code_viol_p = '1' then idle" |
-- code(more!)cleaned-up |
-- 01/2011 v0.04 EG changed way of detecting the FES to be able to detect a FES even if |
-- bytes with size different than 8 have preceeded. |
-- crc_wrong_p_o replaced the crc_wrong_p_o. |
-- 02/2011 v0.05 EG changed crc pulse transfer; removed switch to deglitch state |
-- s_fes_detected removed and s_byte_ready_p_d1; if bytes arrive with |
-- bits not x8, the fss_crc_fes_ok_p_o stays 0 (bc of s_byte_ready_p_d1) |
-- and the crc_wrong_p_o is asserted (bc of s_sample_manch_bit_p_d1); |
-- unit reset during production; |
-- check for code vilations completely removed! |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
......@@ -120,9 +119,7 @@ use work.WF_PACKAGE.all; -- definitions of types, constants, entities
-- Entity declaration for WF_rx_deserializer
--=================================================================================================
entity WF_rx_deserializer is
port (
entity WF_rx_deserializer is port(
-- INPUTS
-- nanoFIP User Interface general signal
uclk_i : in std_logic; -- 40 MHz clock
......@@ -137,7 +134,7 @@ entity WF_rx_deserializer is
-- Signals from the WF_rx_deglitcher
fd_rxd_f_edge_p_i : in std_logic; -- indicates a falling edge on the deglitched FD_RXD
fd_rxd_r_edge_p_i : in std_logic; -- indicates a rising edge on the deglitched FD_RXD
fd_rxd_r_edge_p_i : in std_logic; -- indicates a rising edge on the deglitched FD_RXD
fd_rxd_i : in std_logic; -- deglitched FD_RXD
-- Signals from the WF_rx_osc unit
......@@ -163,8 +160,8 @@ entity WF_rx_deserializer is
fss_received_p_o : out std_logic; -- pulse upon reception of a correct FSS (ID/RP)
-- Signal to the WF_rx_osc unit
rx_osc_rst_o : out std_logic -- resets the clk recovery procedure
);
rx_osc_rst_o : out std_logic);-- resets the clk recovery procedure
end entity WF_rx_deserializer;
......@@ -187,6 +184,7 @@ architecture rtl of WF_rx_deserializer is
signal s_byte : std_logic_vector (7 downto 0);
signal s_arriving_fes : std_logic_vector (15 downto 0);
--=================================================================================================
-- architecture begin
--=================================================================================================
......@@ -228,14 +226,14 @@ begin
begin
-- During the PRE, the WF_rx_osc is trying to synchronize to the transmitter's clock and every
-- edge detected in the deglitched FD_RXD is taken into account. At this phase, the unit uses
-- the WF_rx_osc signals adjac_bits_window_i and signif_edge_window_i and if edges are found
-- edge detected in the FD_RXD is taken into account. At this phase, the unit uses
-- the WF_rx_osc signals: adjac_bits_window_i and signif_edge_window_i and if edges are found
-- outside those windows the unit goes back to idle and the WF_rx_osc is reset.
-- For the rest of the frame, the unit is just sampling the deglitched FD_RXD on the moments
-- specified by the WF_rx_osc signals sample_manch_bit_p_i and sample_bit_p_i.
-- specified by the WF_rx_osc signals: sample_manch_bit_p_i and sample_bit_p_i.
-- nanoFIP can receive ID_DATs of a predefined length of 8 bytes and RP_DATs of any length
-- (not predefined) up to 133 bytes (FSS+Ctrl+PDU_TYPE+LGTH+124 application_data+MPS+FCS+FES).
-- (not predefined) up to 133 bytes (FSS+CTRL+PDU_TYPE+LGTH+124 application_data+MPS+FCS+FES).
-- The WF_engine_control unit is following the amount of bytes being received and in case
-- their number exceeds the expected one, it activates the signal rx_rst_i.
-- Moreover, an extra more robust protection, that depends only on the system clock, has been
......@@ -265,7 +263,7 @@ begin
if (rx_rst_i = '1') or (s_session_timedout = '1') then
nx_rx_st <= idle;
elsif s_manch_r_edge_p = '1' then -- arrival of a "manch."
elsif s_manch_r_edge_p = '1' then -- arrival of a manch.
nx_rx_st <= pre_field_r_edge; -- rising edge
elsif s_edge_out_manch_window_p = '1' then -- arrival of any other edge
......@@ -313,9 +311,9 @@ begin
end if;
-- For the monitoring of the FSD, the unit is sampling each manch. bit of the incoming
-- filtered FD_RXD and it is comparing it to the nominal bit of the FSD (through the signal
-- s_fsd_wrong_bit). If a wrong bit is received, the state machine jumps back to idle,
-- whereas if the complete byte is correctly received, it jumps to the ctrl_data_fcs_fes_fields
-- FD_RXD and it is comparing it to the nominal bit of the FSD; the signal s_fsd_wrong_bit
-- is doing this comparison. If a wrong bit is received, the state machine jumps back to idle,
-- whereas if the complete byte is correctly received, it jumps to the ctrl_data_fcs_fes_fields.
when fsd_field =>
if (rx_rst_i = '1') or (s_session_timedout = '1') then
......@@ -419,7 +417,7 @@ begin
---------------------------------------------------------------------------------------------------
-- Synchronous process Append_Bit_To_Byte: Creation of bytes of data.
-- A new bit of the deglitched FD_RXD is appended to the output byte that is being formed when the
-- A new bit of the FD_RXD is appended to the output byte that is being formed when the
-- Deserializer's FSM is in the "ctrl_data_fcs_fes_fields" state, on the "sample_bit_p_i" moments.
Append_Bit_To_Byte: process (uclk_i)
......@@ -448,17 +446,13 @@ begin
---------------------------------------------------------------------------------------------------
-- FSD detection --
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Instantiation of a counter that manages the position of an incoming deglitched FD_RXD bit
-- inside a manch. encoded byte (16 bits).
-- Instantiation of a counter that manages the position of an incoming FD_RXD bit inside a manch.
-- encoded byte (16 bits).
Incoming_Bits_Index: WF_decr_counter
generic map (g_counter_lgth => 4)
port map (
generic map(g_counter_lgth => 4)
port map(
uclk_i => uclk_i,
nfip_rst_i => nfip_rst_i,
counter_top => s_manch_bit_index_top,
......@@ -469,50 +463,29 @@ begin
counter_is_zero_o => s_manch_bit_index_is_zero);
---------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
s_manch_bit_index_top <= to_unsigned (c_FSD'left-2, s_manch_bit_index_top'length) when s_receiving_pre = '1' else
to_unsigned (15, s_manch_bit_index_top'length) when s_receiving_bytes ='1' else
to_unsigned (0, s_manch_bit_index_top'length);
s_manch_bit_index_load_p <= '1' when (s_idle ='1') else
s_manch_bit_index_is_zero and sample_manch_bit_p_i when (s_receiving_pre = '1') or (s_receiving_bytes = '1') else --reloading for every new byte
'0';
s_manch_bit_index_decr_p <= sample_manch_bit_p_i when (s_receiving_fsd = '1') or (s_receiving_bytes = '1') else '0';
---------------------------------------------------------------------------------------------------
-- FSD detection --
---------------------------------------------------------------------------------------------------
-- FSD aux signals concurrent assignments:
s_fsd_bit <= s_receiving_fsd and c_FSD (to_integer(s_manch_bit_index));
s_fsd_last_bit <= s_manch_bit_index_is_zero and sample_manch_bit_p_i;
s_fsd_wrong_bit <= (s_fsd_bit xor fd_rxd_i) and sample_manch_bit_p_i;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Combinatorial process that according to the state of the FSM sets values to the
-- Incoming_Bits_Index inputs.
Bit_Index: process (s_idle,s_receiving_pre, s_receiving_fsd, s_receiving_bytes,
s_manch_bit_index_is_zero,sample_manch_bit_p_i)
begin
if s_idle ='1' then -- counter re-initialization after a reception
s_manch_bit_index_top <= to_unsigned (0, s_manch_bit_index_top'length);
s_manch_bit_index_load_p <= '1';
s_manch_bit_index_decr_p <= '0';
elsif s_receiving_pre = '1' then -- preparation for the FSD byte
s_manch_bit_index_top <= to_unsigned(c_FSD'left-2,s_manch_bit_index_top'length);
-- FSD'left-2: bc the 1st bit of the FSD has been covered at the state PRE_field_f_edge
s_manch_bit_index_load_p <= s_manch_bit_index_is_zero and sample_manch_bit_p_i;
s_manch_bit_index_decr_p <= '0';
elsif s_receiving_fsd = '1' then -- counting FSD manch. encoded bits
s_manch_bit_index_top <= to_unsigned (0, s_manch_bit_index_top'length);
s_manch_bit_index_load_p <= '0';
s_manch_bit_index_decr_p <= sample_manch_bit_p_i;
elsif s_receiving_bytes = '1' then -- counting manch. encoded data bits
s_manch_bit_index_top <= to_unsigned (15, s_manch_bit_index_top'length);
s_manch_bit_index_load_p <= s_manch_bit_index_is_zero and sample_manch_bit_p_i;
s_manch_bit_index_decr_p <= sample_manch_bit_p_i;
else
s_manch_bit_index_top <= to_unsigned (0, s_manch_bit_index_top'length);
s_manch_bit_index_load_p <= '0';
s_manch_bit_index_decr_p <= '0';
end if;
end process;
---------------------------------------------------------------------------------------------------
......@@ -537,7 +510,7 @@ begin
end process;
-- -- -- -- -- -- -- -- -- -- --
s_fes_detected <= '1' when (s_arriving_fes = c_FES) else '0';
s_fes_detected <= '1' when s_arriving_fes = c_FES else '0';
......@@ -549,7 +522,7 @@ begin
-- Instantiation of the CRC calculator unit that verifies the received FCS field.
CRC_Verification : WF_crc
port map (
port map(
uclk_i => uclk_i,
nfip_rst_i => nfip_rst_i,
start_crc_p_i => s_receiving_fsd,
......@@ -602,8 +575,8 @@ begin
-- is defined using the slowest bit rate and considering reception of the upper limit of 134 bytes.
Session_Timeout_Counter: WF_decr_counter
generic map (g_counter_lgth => 21)
port map (
generic map(g_counter_lgth => 21)
port map(
uclk_i => uclk_i,
nfip_rst_i => nfip_rst_i,
counter_top => (others => '1'),
......
wf_rx_osc.vhd
View file @ caddc235
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- --
-- WF_rx_osc --
-- --
-- |
-- WF_rx_osc |
-- |
---------------------------------------------------------------------------------------------------
-- File WF_rx_osc.vhd
--
-- Description Generation of the clock signals needed for the FIELDRIVE reception
--
-- Even if the bit rate of the communication is known, jitter is expected to affect the
-- arriving time of the incoming signal. The main idea of the unit is to recalculate
-- the expected arrival time of the next incoming bit, based on the arrival of the
-- previous one, so that drifts are not accumulated. The clock recovery is based on the
-- Manchester 2 coding which ensures that there is one edge (transition) for each bit.
--
-- In this unit, we refer to
-- o a significant edge : for the edge of a manch. encoded bit (bit 0: _|-, bit 1: -|_)
-- o a transition : for the moment in between two adjacent bits, that may or
-- may not result in an edge (eg. a 0 followed by a 0 will give an edge _|-|_|-,
-- but a 0 followed by a 1 will not _|--|_ ).
--
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
-- Date 14/02/2011
-- Version v0.04
-- Depends on WF_reset_unit
-- WF_deglitcher
-- WF_rx_deserializer
----------------
-- Last changes
-- 08/2009 v0.01 PS Entity Ports added, start of architecture content
-- 07/2010 v0.02 EG rx counter changed from 20 bits signed, to 11 bits unsigned;
-- rx clk generation depends on edge detection;code cleanedup+commented
-- rst_rx_osc signal clearified
-- 12/2010 v0.03 EG code cleaned-up
-- 01/2011 v0.031 EG rxd_edge_i became fd_rxd_edge_p_i; small correctiond on comments
-- 02/2011 v0.04 EG 2 units WF_rx_osc and WF_tx_osc; process replaced by WF_incr_counter
-- check for code violations removed completely
-- File WF_rx_osc.vhd |
-- |
-- Description Generation of the clock signals needed for the FIELDRIVE reception |
-- |
-- Even if the bit rate of the communication is known, jitter is expected to affect |
-- the arriving time of the incoming signal. The main idea of the unit is to |
-- recalculate the expected arrival time of the next incoming bit, based on the |
-- arrival of the previous one, so that drifts are not accumulated. The clock |
-- recovery is based on the Manchester 2 coding which ensures that there is one edge |
-- (transition) for each bit. |
-- |
-- In this unit, we refer to |
-- o a significant edge: for the edge of a manch. encoded bit (bit 0:_|-, bit 1: -|_)|
-- o a transition : for the moment in between two adjacent bits, that may or |
-- may not result in an edge (eg. a 0 followed by a 0 will give an edge _|-|_|-, |
-- but a 0 followed by a 1 will not _|--|_ ). |
-- |
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 14/02/2011 |
-- Version v0.04 |
-- Depends on WF_reset_unit |
-- WF_deglitcher |
-- WF_rx_deserializer |
------------------ |
-- Last changes |
-- 08/2009 v0.01 PS Entity Ports added, start of architecture content |
-- 07/2010 v0.02 EG rx counter changed from 20 bits signed, to 11 bits unsigned; |
-- rx clk generation depends on edge detection;code cleanedup+commented |
-- rst_rx_osc signal clearified |
-- 12/2010 v0.03 EG code cleaned-up |
-- 01/2011 v0.031 EG rxd_edge_i became fd_rxd_edge_p_i; small correctiond on comments |
-- 02/2011 v0.04 EG 2 units WF_rx_osc and WF_tx_osc; process replaced by WF_incr_counter |
-- check for code violations removed completely |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
......@@ -77,8 +78,7 @@ use work.WF_PACKAGE.all; -- definitions of types, constants, entities
-- Entity declaration for WF_rx_osc
--=================================================================================================
entity WF_rx_osc is
port (
entity WF_rx_osc is port(
-- INPUTS
-- nanoFIP User Interface, General signals
uclk_i : in std_logic; -- 40 MHz clock
......@@ -107,9 +107,8 @@ entity WF_rx_osc is
rx_signif_edge_window_o : out std_logic; -- time window where a significant edge is expected
rx_adjac_bits_window_o : out std_logic -- time window where a transition between adjacent
rx_adjac_bits_window_o : out std_logic); -- time window where a transition between adjacent
-- bits is expected
);
end entity WF_rx_osc;
......@@ -119,26 +118,36 @@ end entity WF_rx_osc;
--=================================================================================================
architecture rtl of WF_rx_osc is
-- reception period counter
signal s_period_c, s_period, s_margin : unsigned (c_PERIODS_COUNTER_LGTH-1 downto 0);
signal s_half_period : unsigned (c_PERIODS_COUNTER_LGTH-1 downto 0);
signal s_period_c_reinit, s_period_c_is_full : std_logic;
-- windows formed, based on the counter
signal s_adjac_bits_window, s_signif_edge_window : std_logic;
-- fd_rxd signal combined with the windows
signal s_adjac_bits_edge_found, s_signif_edge_found : std_logic;
-- clocks
signal s_bit_clk, s_bit_clk_d1, s_manch_clk, s_manch_clk_d1 : std_logic;
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
---------------------------------------------------------------------------------------------------
-- Generation of windows where edges/ transitions are expected --
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- # uclock ticks for a bit period, defined by the WorldFIP bit rate
s_period <= c_BIT_RATE_UCLK_TICKS(to_integer(unsigned(rate_i)));
s_half_period <= s_period srl 1; -- 1/2 s_period
s_margin <= s_period srl 3; -- margin for jitter defined as 1/8 of the period
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Instantiation of a WF_incr_counter unit : the rx_counter starts counting after the
-- release of the reset signal rx_osc_rst_i. This takes place after a falling edge on the
-- filtered FD_RXD; this edge should be representing the 1st Manchester (manch.) encoded bit '1'
......@@ -150,8 +159,8 @@ begin
-- is reinitialialized through the rx_osc_rst_i signal from the WF_rx_deserializer.
rx_periods_count: WF_incr_counter
generic map (g_counter_lgth => c_PERIODS_COUNTER_LGTH)
port map (
generic map(g_counter_lgth => c_PERIODS_COUNTER_LGTH)
port map(
uclk_i => uclk_i,
reinit_counter_i => s_period_c_reinit,
incr_counter_i => '1',
......@@ -163,25 +172,44 @@ begin
s_period_c_is_full <= '1' when s_period_c = s_period -1 else '0'; -- counter full indicator
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- counter reinitialized : if nfip_rst_i is active or
-- if rx_osc_rst_i is active or
-- if an edge is detected in the expected window or
-- if it fills up
-- counter reinitialized: if nfip_rst_i is active or
-- if rx_osc_rst_i is active or
-- if an edge is detected in the expected window or
-- if it fills up
s_period_c_reinit <= nfip_rst_i or rx_osc_rst_i or (s_signif_edge_window and fd_rxd_edge_p_i)
or s_period_c_is_full;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Concurrent signal assignments: creation of the windows where
-- "significant edges" and "adjacent bits transitions" are expected on the input signal.
-- o s_signif_edge_window: extends s_margin uclk ticks before and s_margin uclk ticks after
-- the completion of a period, where significant edges are expected.
-- o s_adjac_bits_window : extends s_margin uclk ticks before and s_margin uclk ticks after
-- the middle of a period, where transitions between adjacent bits are expected.
s_signif_edge_window <= '1' when ((s_period_c < s_margin) or
(s_period_c > s_period-1 - s_margin-1)) else '0';
s_adjac_bits_window <= '1' when ((s_period_c >= s_half_period-s_margin-1) and
(s_period_c < s_half_period+s_margin)) else '0';
---------------------------------------------------------------------------------------------------
-- Clocks Generation --
---------------------------------------------------------------------------------------------------
-- Synchronous process rx_clks: the process rx_clk is following the edges that appear on the
-- nanoFIP FIELDRIVE input fd_rxd and constructs two clock signals: rx_manch_clk & rx_bit_clk.
-- In detail, the process is looking for moments :
-- In detail, the process is looking for moments:
-- o of significant edges
-- o between boundary bits
-- The signal rx_manch_clk : is inverted on each significant edge, as well as between adjacent bits
-- The signal rx_bit_clk : is inverted only between adjacent bits
-- The signal rx_manch_clk: is inverted on each significant edge, as well as between adjacent bits
-- The signal rx_bit_clk : is inverted only between adjacent bits
-- The significant edges are normally expected inside the signif_edge_window. In the cases of a
-- code violation (V+ or V-) no edge will arrive in this window. In this situation rx_manch_clk
......@@ -263,25 +291,8 @@ begin
---------------------------------------------------------------------------------------------------
-- Concurrent signal assignments: creation of the windows where
-- "significant edges" and "adjacent bits transitions" are expected on the input signal.
-- o s_signif_edge_window : extends s_margin uclk ticks before and s_margin uclk ticks after
-- the completion of a period, where significant edges are expected.
-- o s_adjac_bits_window : extends s_margin uclk ticks before and s_margin uclk ticks after
-- the middle of a period, where transitions between adjacent bits are expected.
s_signif_edge_window <= '1' when ((s_period_c < s_margin) or
(s_period_c > s_period-1 - s_margin-1))
else '0';
s_adjac_bits_window <= '1' when ((s_period_c >= s_half_period-s_margin-1) and
(s_period_c < s_half_period+s_margin))
else '0';
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Output signals concurrent assignments
-- Concurrent signal assignments --
---------------------------------------------------------------------------------------------------
rx_manch_clk_p_o <= s_manch_clk_d1 xor s_manch_clk; -- a 1 uclk-wide pulse, after
-- o a significant edge
......
wf_status_bytes_gen.vhd
View file @ caddc235
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- --
-- WF_status_bytes_gen --
-- --
-- |
-- WF_status_bytes_gen |
-- |
---------------------------------------------------------------------------------------------------
-- File WF_status_bytes_gen.vhd
--
-- Description Generation of the nanoFIP status and MPS status bytes.
-- The unit is also responsible for outputting the "nanoFIP User Interface,
-- NON_WISHBONE" signals U_CACER, U_PACER, R_TLER, R_FCSER, that correspond to nanoFIP
-- status bits 2 to 5.
--
-- The information contained in the nanoFIP status byte is coming from :
-- o the WF_consumption unit, for the bits 4 and 5
-- o the "nanoFIP FIELDRIVE" inputs FD_WDGN and FD_TXER, for the bits 6 and 7
-- o the "nanoFIP User Interface, NON_WISHBONE" inputs (VAR_ACC) and outputs
-- (VAR_RDY), for the bits 2 and 3.
--
-- For the MPS byte, in memory mode, the refreshment and significance bits are set to
-- 1 if the user has updated the produced variable var3 since its last transmission;
-- the signal "nanoFIP User Interface, NON_WISHBONE" input VAR3_ACC, is used for this.
-- In stand-alone mode the refreshment and the significance are set to 1.
-- Also, regardless of the mode, for the consumed variable jc_var3 the refreshment
-- and significance are set to 1.
--
-- The MPS and the nanoFIP status byte are reset after having been sent or after a
-- nanoFIP internal reset.
--
-- Reminder:
-- ______________________ __________ ____________________________________________
-- | nanoFIP STATUS BIT | NAME | CONTENTS |
-- |______________________|__________|____________________________________________|
-- | 0 | r1 | reserved |
-- |______________________|__________|____________________________________________|
-- | 1 | r2 | reserved |
-- |______________________|__________|____________________________________________|
-- | 2 | u_cacer | user cons var access error |
-- |______________________|__________|____________________________________________|
-- | 3 | u_pacer | user prod var access error |
-- |______________________|__________|____________________________________________|
-- | 4 | r_tler | received Control, PDU_TYPE or Length error |
-- |______________________|__________|____________________________________________|
-- | 5 | r_fcser | received FCS or bit number error |
-- |______________________|__________|____________________________________________|
-- | 6 | t_txer | transmit error (FIELDRIVE) |
-- |______________________|__________|____________________________________________|
-- | 7 | t_wder | watchdog error (FIELDRIVE) |
-- |______________________|__________|____________________________________________|
--
-- ---------------------------------------------------------------------------
-- __________________ ______________ ______________
-- | MPS STATUS BIT | NAME | CONTENTS |
-- |__________________|______________|______________|
-- | 0 | refreshment | 1/0 |
-- |__________________|______________|______________|
-- | 1 | | 0 |
-- |__________________|______________|______________|
-- | 2 | significance | 1/0 |
-- |__________________|______________|______________|
-- | 3 | | 0 |
-- |__________________|_____________ |______________|
-- | 4-7 | | 000 |
-- |__________________|_____________ |______________|
--
--
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
-- Date 06/2011
-- Version v0.04
-- Depends on WF_reset_unit
-- WF_consumption
-- WF_prod_bytes_retriever
-- WF_prod_permit
----------------
-- Last changes
-- 07/07/2009 v0.01 PA First version
-- 08/2010 v0.02 EG Internal extention of the var_rdy signals to avoid nanoFIP status
-- errors few cycles after var_rdy deactivation
-- 01/2011 v0.03 EG u_cacer,pacer etc outputs added; new input nfip_status_r_tler_p_i
-- for nanoFIP status bit 4; var_i input not needed as the signals
-- nfip_status_r_fcser_p_i and nfip_status_r_tler_p_i check the var
-- 06/2011 v0.04 EG all bits of nanoFIP status byte are reset upon rst_status_bytes_p_i
-- var_i added for the jtag_var1 treatment;
-- r_fcser, r_tler_o considered only for a cons variable (bf a wrong
-- crc on an id-dat could give r_fcser)
-- File WF_status_bytes_gen.vhd |
-- |
-- Description Generation of the nanoFIP status and MPS status bytes. |
-- The unit is also responsible for outputting the "nanoFIP User Interface, |
-- NON_WISHBONE" signals U_CACER, U_PACER, R_TLER, R_FCSER, that correspond to |
-- nanoFIP status bits 2 to 5. |
-- |
-- The information contained in the nanoFIP status byte is coming from : |
-- o the WF_consumption unit, for the bits 4 and 5 |
-- o the "nanoFIP FIELDRIVE" inputs FD_WDGN and FD_TXER, for the bits 6 and 7 |
-- o the "nanoFIP User Interface, NON_WISHBONE" inputs (VAR_ACC) and outputs |
-- (VAR_RDY), for the bits 2 and 3. |
-- |
-- For the MPS byte, in memory mode, the refreshment and significance bits are set to|
-- 1 if the user has updated the produced variable var3 since its last transmission; |
-- the signal "nanoFIP User Interface, NON_WISHBONE" input VAR3_ACC,is used for this.|
-- In stand-alone mode the refreshment and the significance are set to 1. |
-- Also, regardless of the mode, for the consumed variable jc_var3 the refreshment |
-- and significance are set to 1. |
-- |
-- The MPS and the nanoFIP status byte are reset after having been sent or after a |
-- nanoFIP internal reset. |
-- |
-- Reminder: |
-- ______________________ __________ ____________________________________________ |
-- | nanoFIP STATUS BIT | NAME | CONTENTS | |
-- |______________________|__________|____________________________________________| |
-- | 0 | r1 | reserved | |
-- |______________________|__________|____________________________________________| |
-- | 1 | r2 | reserved | |
-- |______________________|__________|____________________________________________| |
-- | 2 | u_cacer | user cons var access error | |
-- |______________________|__________|____________________________________________| |
-- | 3 | u_pacer | user prod var access error | |
-- |______________________|__________|____________________________________________| |
-- | 4 | r_tler | received CTRL, PDU_TYPE or LGTH error | |
-- |______________________|__________|____________________________________________| |
-- | 5 | r_fcser | received FCS or bit number error | |
-- |______________________|__________|____________________________________________| |
-- | 6 | t_txer | transmit error (FIELDRIVE) | |
-- |______________________|__________|____________________________________________| |
-- | 7 | t_wder | watchdog error (FIELDRIVE) | |
-- |______________________|__________|____________________________________________| |
-- |
-- --------------------------------------------------------------------------- |
-- __________________ ______________ ______________ |
-- | MPS STATUS BIT | NAME | CONTENTS | |
-- |__________________|______________|______________| |
-- | 0 | refreshment | 1/0 | |
-- |__________________|______________|______________| |
-- | 1 | | 0 | |
-- |__________________|______________|______________| |
-- | 2 | significance | 1/0 | |
-- |__________________|______________|______________| |
-- | 3 | | 0 | |
-- |__________________|_____________ |______________| |
-- | 4-7 | | 000 | |
-- |__________________|_____________ |______________| |
-- |
-- |
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 06/2011 |
-- Version v0.04 |
-- Depends on WF_reset_unit |
-- WF_consumption |
-- WF_prod_bytes_retriever |
-- WF_prod_permit |
---------------- |
-- Last changes |
-- 07/07/2009 v0.01 PA First version |
-- 08/2010 v0.02 EG Internal extention of the var_rdy signals to avoid nanoFIP status |
-- errors few cycles after var_rdy deactivation |
-- 01/2011 v0.03 EG u_cacer,pacer etc outputs added; new input nfip_status_r_tler_p_i |
-- for nanoFIP status bit 4; var_i input not needed as the signals |
-- nfip_status_r_fcser_p_i and nfip_status_r_tler_p_i check the var |
-- 06/2011 v0.04 EG all bits of nanoFIP status byte are reset upon rst_status_bytes_p_i |
-- var_i added for the jtag_var1 treatment; |
-- r_fcser, r_tler_o considered only for a cons variable (bf a wrong |
-- crc on an id-dat could give r_fcser) |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
......@@ -123,9 +123,7 @@ use work.WF_PACKAGE.all; -- definitions of types, constants, entities
--=================================================================================================
-- Entity declaration for WF_status_bytes_gen
--=================================================================================================
entity WF_status_bytes_gen is
port (
entity WF_status_bytes_gen is port(
-- INPUTS
-- nanoFIP User Interface, General signals
uclk_i : in std_logic; -- 40 MHz Clock
......@@ -145,7 +143,7 @@ port (
-- Signals from the WF_consumption unit
nfip_status_r_fcser_p_i : in std_logic; -- wrong CRC bytes received
nfip_status_r_tler_p_i : in std_logic; -- wrong PDU_TYPE, Control or Length bytes received
nfip_status_r_tler_p_i : in std_logic; -- wrong PDU_TYPE, CTRL or LGTH bytes received
var1_rdy_i : in std_logic; -- variable 1 ready
var2_rdy_i : in std_logic; -- variable 2 ready
......@@ -169,8 +167,8 @@ port (
-- Signal to the WF_prod_bytes_retriever
mps_status_byte_o : out std_logic_vector (7 downto 0); -- MPS status byte
nFIP_status_byte_o : out std_logic_vector (7 downto 0) -- nanoFIP status byte
);
nFIP_status_byte_o : out std_logic_vector (7 downto 0));-- nanoFIP status byte
end entity WF_status_bytes_gen;
--=================================================================================================
......@@ -178,14 +176,19 @@ end entity WF_status_bytes_gen;
--=================================================================================================
architecture rtl of WF_status_bytes_gen is
-- synchronizers
signal s_fd_txer_synch, s_fd_wdg_synch, s_var1_acc_synch : std_logic_vector (2 downto 0);
signal s_var2_acc_synch, s_var3_acc_synch : std_logic_vector (2 downto 0);
-- MPS refreshment/ significance bit
signal s_refreshment : std_logic;
-- nanoFIP status byte
signal s_nFIP_status_byte : std_logic_vector (7 downto 0);
-- extension of var_rdy signals
signal s_var1_rdy_c, s_var2_rdy_c, s_var3_rdy_c : unsigned (3 downto 0);
signal s_var1_rdy_c_incr,s_var1_rdy_c_reinit,s_var1_rdy_extended : std_logic;
signal s_var2_rdy_c_incr,s_var2_rdy_c_reinit,s_var2_rdy_extended : std_logic;
signal s_var3_rdy_c_incr,s_var3_rdy_c_reinit,s_var3_rdy_extended : std_logic;
signal s_refreshment : std_logic;
signal s_nFIP_status_byte : std_logic_vector (7 downto 0);
signal s_fd_txer_synch, s_fd_wdg_synch, s_var1_acc_synch : std_logic_vector (2 downto 0);
signal s_var2_acc_synch, s_var3_acc_synch : std_logic_vector (2 downto 0);
--=================================================================================================
-- architecture begin
......@@ -196,6 +199,7 @@ begin
---------------------------------------------------------------------------------------------------
-- FD_TXER, FD_WDGN, VARx_ACC Synchronizers --
---------------------------------------------------------------------------------------------------
FIELDRIVE_inputs_synchronizer: process (uclk_i)
begin
if rising_edge (uclk_i) then
......@@ -234,6 +238,7 @@ begin
---------------------------------------------------------------------------------------------------
-- MPS status byte --
---------------------------------------------------------------------------------------------------
-- Synchronous process Refreshment_bit_Creation: Creation of the refreshment bit (used in
-- the MPS status byte). The bit is set to 1 if the user has updated the produced variable since
-- its last transmission. The process is checking if the signal VAR3_ACC has been asserted since
......@@ -258,7 +263,7 @@ begin
end process;
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Combinatorial process MPS_byte_Generation: Creation of the MPS byte (Table 2, functional specs)
MPS_byte_Generation: process (slone_i, s_refreshment, var_i)
......@@ -283,6 +288,7 @@ begin
---------------------------------------------------------------------------------------------------
-- nanoFIP status byte --
---------------------------------------------------------------------------------------------------
-- Synchronous process nFIP_status_byte_Generation: Creation of the nanoFIP status byte (Table 8,
-- functional specs)
......@@ -339,7 +345,7 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--r_tler -- PDU_TYPE or length error on a consumed var
--r_tler -- PDU_TYPE or LGTH error on a consumed var
if (nfip_status_r_tler_p_i = '1' and ((var_i = var_1) or (var_i = var_2) or (var_i = var_jc1) or (var_i = var_rst))) then
s_nFIP_status_byte(c_R_TLER_INDEX) <= '1';
end if;
......@@ -358,14 +364,14 @@ begin
end process;
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Instantiation of 3 WF_incr_counters used for the internal extension of each one of the
-- signals VAR1_RDY, VAR2_RDY, VAR3_RDY for 15 uclk cycles.
-- Enabled VAR_ACC during this period will not trigger a nanoFIP status byte error.
Extend_VAR1_RDY: WF_incr_counter -- VAR1_RDY : __|---...---|___________________
generic map (g_counter_lgth => 4) -- s_var1_rdy_extended : __|---...------------------|____
port map (
Extend_VAR1_RDY: WF_incr_counter -- VAR1_RDY : __|---...---|___________________
generic map(g_counter_lgth => 4) -- s_var1_rdy_extended: __|---...------------------|____
port map( -- --> VAR_ACC here is OK! <--
uclk_i => uclk_i,
reinit_counter_i => s_var1_rdy_c_reinit,
incr_counter_i => s_var1_rdy_c_incr,
......@@ -380,8 +386,8 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Extend_VAR2_RDY: WF_incr_counter
generic map (g_counter_lgth => 4)
port map (
generic map(g_counter_lgth => 4)
port map(
uclk_i => uclk_i,
reinit_counter_i => s_var2_rdy_c_reinit,
incr_counter_i => s_var2_rdy_c_incr,
......@@ -396,8 +402,8 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Extend_VAR3_RDY: WF_incr_counter
generic map (g_counter_lgth => 4)
port map (
generic map(g_counter_lgth => 4)
port map(
uclk_i => uclk_i,
reinit_counter_i => s_var3_rdy_c_reinit,
incr_counter_i => s_var3_rdy_c_incr,
......
wf_tx_osc.vhd
View file @ caddc235
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- --
-- WF_tx_osc --
-- --
-- |
-- WF_tx_osc |
-- |
---------------------------------------------------------------------------------------------------
-- File WF_tx_osc.vhd
--
-- Description Generation of the clock signals needed for the FIELDRIVE transmission
--
-- The unit generates the nanoFIP FIELDRIVE output FD_TXCK (line driver half bit clock)
-- and the nanoFIP internal signal tx_sched_p_buff:
--
-- uclk : _|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_
-- FD_TXCK : _____|--------...--------|________...________|--------...----
-- tx_sched_p_buff(3) : 0 0 0 1 0 0 0 1
-- tx_sched_p_buff(2) : 0 0 1 0 0 0 1 0
-- tx_sched_p_buff(1) : 0 1 0 0 0 1 0 0
-- tx_sched_p_buff(0) : 1 0 0 0 1 0 0 0
--
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
-- Date 14/02/2011
-- Version v0.04
-- Depends on WF_reset_unit
----------------
-- Last changes
-- 08/2009 v0.01 PS Entity Ports added, start of architecture content
-- 07/2010 v0.02 EG tx counter changed from 20 bits signed, to 11 bits unsigned;
-- c_TX_SCHED_BUFF_LGTH got 1 bit more
-- 12/2010 v0.03 EG code cleaned-up
-- File WF_tx_osc.vhd |
-- |
-- Description Generation of the clock signals needed for the FIELDRIVE transmission. |
-- |
-- The unit generates the nanoFIP FIELDRIVE output FD_TXCK (line driver half bit |
-- clock) and the nanoFIP internal signal tx_sched_p_buff: |
-- |
-- uclk : _|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-| |
-- FD_TXCK : _____|--------...--------|________...________|--------...--- |
-- tx_sched_p_buff(3): 0 0 0 1 0 0 0 1 |
-- tx_sched_p_buff(2): 0 0 1 0 0 0 1 0 |
-- tx_sched_p_buff(1): 0 1 0 0 0 1 0 0 |
-- tx_sched_p_buff(0): 1 0 0 0 1 0 0 0 |
-- |
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 14/02/2011 |
-- Version v0.04 |
-- Depends on WF_reset_unit |
---------------- |
-- Last changes |
-- 08/2009 v0.01 PS Entity Ports added, start of architecture content |
-- 07/2010 v0.02 EG tx counter changed from 20 bits signed, to 11 bits unsigned; |
-- c_TX_SCHED_BUFF_LGTH got 1 bit more |
-- 12/2010 v0.03 EG code cleaned-up |
-- 01/2011 v0.04 EG WF_tx_osc as different unit; use of WF_incr_counter;added tx_osc_rst_p_i
---------------------------------------------------------------------------------------------------
......@@ -89,10 +89,9 @@ entity WF_tx_osc is
tx_clk_o : out std_logic; -- line driver half bit clock
-- Signal to the WF_tx_serializer unit
tx_sched_p_buff_o : out std_logic_vector (c_TX_SCHED_BUFF_LGTH -1 downto 0)
tx_sched_p_buff_o : out std_logic_vector (c_TX_SCHED_BUFF_LGTH -1 downto 0));
-- buffer of pulses used for the scheduling
-- of the actions of the WF_tx_serializer
);
end entity WF_tx_osc;
......@@ -101,10 +100,14 @@ end entity WF_tx_osc;
--=================================================================================================
architecture rtl of WF_tx_osc is
-- transmission periods counter
signal s_period_c, s_period : unsigned (c_PERIODS_COUNTER_LGTH -1 downto 0);
signal s_one_forth_period : unsigned (c_PERIODS_COUNTER_LGTH -1 downto 0);
signal s_period_c_is_full, s_period_c_reinit : std_logic;
-- clocks
signal s_tx_clk_d1, s_tx_clk, s_tx_clk_p : std_logic;
signal s_tx_sched_p_buff : std_logic_vector (c_TX_SCHED_BUFF_LGTH-1 downto 0);
signal s_tx_clk_d1, s_tx_clk, s_tx_clk_p, s_period_c_is_full, s_period_c_reinit : std_logic;
--=================================================================================================
-- architecture begin
......@@ -112,19 +115,24 @@ architecture rtl of WF_tx_osc is
begin
---------------------------------------------------------------------------------------------------
-- Periods Counter --
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
s_period <= c_BIT_RATE_UCLK_TICKS(to_integer(unsigned(rate_i)));-- # uclk ticks for a
-- transmission period
s_one_forth_period <= s_period srl 2; -- 1/4 s_period
s_period_c_is_full <= '1' when s_period_c = s_period -1 else '0'; -- counter full
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Instantiation of a WF_incr_counter counting transmission periods.
tx_periods_count: WF_incr_counter
generic map (g_counter_lgth => c_PERIODS_COUNTER_LGTH)
port map (
generic map(g_counter_lgth => c_PERIODS_COUNTER_LGTH)
port map(
uclk_i => uclk_i,
reinit_counter_i => s_period_c_reinit,
incr_counter_i => '1',
......@@ -133,34 +141,39 @@ begin
counter_o => s_period_c);
------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- counter reinitialized : if the nfip_rst_i is active or
-- if the tx_osc_rst_p_i is active or
-- if it fills up
s_period_c_reinit <= nfip_rst_i or tx_osc_rst_p_i or s_period_c_is_full;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- counter reinitialized : if the nfip_rst_i is active or
-- if the tx_osc_rst_p_i is active or
-- if it fills up
s_period_c_reinit <= nfip_rst_i or tx_osc_rst_p_i or s_period_c_is_full;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Clocks Constraction: Concurrent signals assignments and a synchronous process that use
---------------------------------------------------------------------------------------------------
-- Clocks Construction --
---------------------------------------------------------------------------------------------------
-- Concurrent signals assignments and a synchronous process that use
-- the s_period_c to construct the tx_clk_o clock and the buffer of pulses tx_sched_p_buff_o.
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Creation of the clock for the transmitter with period: 1/2 transmission period
s_tx_clk <= '1' when ((s_period_c < s_one_forth_period) or
((s_period_c > (2*s_one_forth_period)-1) and
(s_period_c < 3*s_one_forth_period)))
else '0';
-- transm. period : _|----------|__________|--
-- tx_counter : 0 1/4 1/2 3/4 1
-- s_tx_clk : _|----|_____|----|_____|--
-- transm. period : _|-----------|___________|--
-- tx_counter : 0 1/4 1/2 3/4 1
-- s_tx_clk : _|-----|_____|-----|_____|--
-- Creation of a pulse starting 1 uclk period before tx_clk_o
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Edge detector for s_tx_clk
s_tx_clk_p <= s_tx_clk and (not s_tx_clk_d1);
-- s_tx_clk : __|-----|_____|-----|_____
-- tx_clk_o/ s_tx_clk_d1 : ____|-----|_____|-----|___
-- not s_tx_clk_d1 : ----|_____|-----|_____|---
-- s_tx_clk_p : __|-|___|-|___|-|___|-|___
-- s_tx_clk : _|-----|_____|-----|_____
-- tx_clk_o/ s_tx_clk_d1: ___|-----|_____|-----|___
-- not s_tx_clk_d1 : ---|_____|-----|_____|---
-- s_tx_clk_p : _|-|___|-|___|-|___|-|___
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
......@@ -179,10 +192,8 @@ begin
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Output signals assignments
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Output signals
tx_clk_o <= s_tx_clk_d1;
tx_sched_p_buff_o <= s_tx_sched_p_buff;
......
wf_tx_serializer.vhd
View file @ caddc235
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- --
-- WF_tx_serializer --
-- --
-- |
-- WF_tx_serializer |
-- |
---------------------------------------------------------------------------------------------------
-- File WF_tx_serializer.vhd
--
-- Description The unit is generating the nanoFIP FIELDRIVE outputs FD_TXD and FD_TXENA. It is
-- retreiving bytes of data from:
-- o the WF_production (from the Ctrl until the MPS)
-- o WF_package (FSS, FES)
-- o and the WF_CRC (CRC bytes).
-- It encodes the bytes to the Manchester 2 scheme and outputs one by one the encoded
-- bits on the moments indicated by the tx_sched_p_buff signal.
-- After the delivery of a byte, it is requesting from the WF_engine_control for a new
-- one; the WF_engine_control is updating the signal byte_index, input to the
-- WF_prod_bytes_retriever that indicates which byte to be retrieved from the memory or
-- the DAT_I bus, and when the new byte becomes available asserts the signal
-- byte_request_accept_p_i. When the byte_index reaches the expected amount of bytes to
-- be transmitted, the WF_engine_control asserts the last_byte_p_i which signals the
-- unit to proceed with the transmission of the CRC bytes and the FES.
--
-- Reminder of the Produced RP_DAT frame structure :
-- ___________ ______ _______ ______ _________________ _______ _______ ___________ _______
-- |____FSS____|_Ctrl_||__PDU__|_LGTH_|__..User-Data..__|_nstat_|__MPS__||____FCS____|__FES__|
--
-- |------------- Bytes from the WF_production -------------|
--
--
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
-- Date 21/01/2011
-- Version v0.04
-- Depends on WF_engine_control
-- WF_production
-- WF_tx_osc
-- WF_reset_unit
----------------
-- Last changes
-- v0.02 2009 PAS Entity Ports added, start of architecture content
-- v0.03 07/2010 EG timing changes; tx_sched_p_buff_i got 1 more bit
-- briefly byte_index_i needed to arrive 1 clock tick earlier
-- renamed from tx to tx_serializer;
-- stop_transmission state added for the synch of txena
-- v0.04 01/2011 EG sync_to_txck state added to start always with the bits 1,2,3 of the
-- clock buffer available(tx_start_p_i may arrive at any time)
-- tx_completed_p_o signal added
-- File WF_tx_serializer.vhd |
-- |
-- Description The unit is generating the nanoFIP FIELDRIVE outputs FD_TXD and FD_TXENA. |
-- It is retreiving bytes of data from: |
-- o the WF_production (from the CTRL byte until the MPS) |
-- o WF_package (FSS and FES bytes) |
-- o and the WF_CRC (FCS bytes). |
-- |
-- It encodes the bytes to the Manchester 2 scheme and outputs one by one the |
-- encoded bits on the moments indicated by the WF_tx_osc unit. |
-- |
-- Reminder of the Produced RP_DAT frame structure : |
-- ___________ ______ _______ ______ _________________ _______ _______ ___________ _______ |
-- |____FSS____|_CTRL_||__PDU__|_LGTH_|__..User-Data..__|_nstat_|__MPS__||____FCS____|__FES__| |
-- |
-- |------------- Bytes from the WF_production -------------| |
-- |
-- |
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 07/2011 |
-- Version v0.05 |
-- Depends on WF_engine_control |
-- WF_production |
-- WF_tx_osc |
-- WF_reset_unit |
---------------- |
-- Last changes |
-- v0.02 2009 PAS Entity Ports added, start of architecture content |
-- v0.03 07/2010 EG timing changes; tx_sched_p_buff_i got 1 more bit |
-- briefly byte_index_i needed to arrive 1 clock tick earlier |
-- renamed from tx to tx_serializer; |
-- stop_transmission state added for the synch of txena |
-- v0.04 01/2011 EG sync_to_txck state added to start always with the bits 1,2,3 of the |
-- clock buffer available(tx_start_p_i may arrive at any time) |
-- tx_completed_p_o signal added |
-- v0.05 07/2011 EG bits_to_txd unit removed |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
......@@ -85,8 +80,7 @@ use work.WF_PACKAGE.all; -- definitions of types, constants, entities
--=================================================================================================
-- Entity declaration for WF_tx_serializer
--=================================================================================================
entity WF_tx_serializer is
port (
entity WF_tx_serializer is port(
-- INPUTS
-- nanoFIP User Interface, General signals
uclk_i : in std_logic; -- 40 MHz clock
......@@ -111,16 +105,15 @@ entity WF_tx_serializer is
-- OUTPUTS
-- Signal to the WF_engine_control unit
tx_byte_request_p_o : out std_logic;
tx_completed_p_o : out std_logic;
tx_byte_request_p_o : out std_logic; -- request for a new byte
tx_completed_p_o : out std_logic; -- pulse upon the end of transmission
-- Signal to the WF_tx_osc unit
tx_osc_rst_p_o : out std_logic;
tx_osc_rst_p_o : out std_logic; -- oscillator reset after a transmission error
-- nanoFIP FIELDRIVE outputs
tx_data_o : out std_logic; -- transmitter serial data
tx_enable_o : out std_logic -- transmitter enable
);
tx_enable_o : out std_logic);-- transmitter enable
end entity WF_tx_serializer;
......@@ -131,37 +124,50 @@ end entity WF_tx_serializer;
--=================================================================================================
architecture rtl of WF_tx_serializer is
type tx_state_t is (idle, sync_to_txck, send_fss, send_data_byte, send_crc_bytes,
send_fes, stop_transmission);
-- FSM
type tx_st_t is (idle, sync_to_txck, send_fss, send_data_byte,
send_crc_bytes, send_fes, stop_transmission);
signal tx_st, nx_tx_st : tx_st_t;
signal s_prepare_to_produce, s_sending_fss, s_sending_data : std_logic;
signal s_sending_crc, s_sending_fes, s_stop_transmission : std_logic;
-- bits counter
signal s_bit_index_decr_p,s_bit_index_load, s_bit_index_is_zero : std_logic;
signal s_bit_index, s_bit_index_top : unsigned (4 downto 0);
-- transmitter output
signal s_txd : std_logic;
-- byte to be transmitted
signal s_data_byte : std_logic_vector (7 downto 0);
signal s_data_byte_manch : std_logic_vector (15 downto 0);
-- CRC calculations
signal s_start_crc_p, s_data_bit_to_crc_p : std_logic;
signal s_crc_bytes : std_logic_vector (15 downto 0);
signal s_crc_bytes_manch : std_logic_vector (31 downto 0);
-- independant timeout counter
signal s_session_timedout : std_logic;
signal tx_state, nx_tx_state : tx_state_t;
signal s_session_timedout : std_logic;
signal s_prepare_to_produce, s_sending_fss, s_sending_data, s_sending_crc : std_logic;
signal s_sending_fes, s_stop_transmission, s_start_crc_p, s_data_bit_to_crc_p : std_logic;
signal s_txd, s_decr_index_p, s_bit_index_load, s_bit_index_is_zero : std_logic;
signal s_bit_index, s_bit_index_top : unsigned (4 downto 0);
signal s_byte : std_logic_vector (7 downto 0);
signal s_crc_bytes_manch : std_logic_vector (31 downto 0);
signal s_crc_bytes, s_data_byte_manch : std_logic_vector (15 downto 0);
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
-- The signal tx_sched_p_buff_i is used for the synchronization of the state transitions of the
-- machine as well as of the actions on the output signals.
-- The signal tx_sched_p_buff_i is used for the scheduling of the state transitions of the machine
-- as well as of the actions on the output signals.
-- The following drawing shows the transitions of the signal tx_sched_p_buff_i with respect to
-- the nanoFIP FIELDRIVE output FD_TXCK (line driver half bit clock).
-- FD_TXCK : _________|-------...---------|________...________|-------...---------|_____
-- tx_sched_p_buff(3) : |0|0|0|1 |0|0|0|1
-- tx_sched_p_buff(2) : |0|0|1|0 |0|0|1|0
-- tx_sched_p_buff(1) : |0|1|0|0 |0|1|0|0
-- tx_sched_p_buff(0) : |1|0|0|0 |1|0|0|0
-- FD_TXCK : _________|-------...---------|________...________|-------...---------|____
-- tx_sched_p_buff(3): |0|0|0|1 |0|0|0|1
-- tx_sched_p_buff(2): |0|0|1|0 |0|0|1|0
-- tx_sched_p_buff(1): |0|1|0|0 |0|1|0|0
-- tx_sched_p_buff(0): |1|0|0|0 |1|0|0|0
----------------------
-- new byte request : ^
-- new byte ready : . . ^
-- 1st bit of new . . . . . . . . . . . . . . . . . .^
-- byte delivery :
-- bit counter : [ 15 . . .][ 14
-- A new bit is delivered after the assertion of tx_sched_p_buff (1).
......@@ -169,15 +175,25 @@ begin
-- the delivery of the bit, after the tx_sched_p_buff (3) assertion. The counter is ahead of the
-- bit being sent.
-- In the sending_bytes state, where the unit is expecting data bytes from the
-- WF_prod_bytes_retriever, the unit delivers a request for a new byte after the tx_sched_p_buff (0)
-- assertion, when the Outgoing_Bits_Index counter is empty (which means that the last bit of a
-- previous byte is now being delivered).
-- The WF_engine_control responds to the request by sending a new address to the
-- WF_prod_bytes_retriever for the retreival of a byte from the memory or the stand-alone bus.
-- In the sending_bytes state, where the unit is expecting data bytes from the WF_production,
-- the unit delivers a request for a new byte after the tx_sched_p_buff (0) assertion,
-- and when the Outgoing_Bits_Index counter is empty (which means that the last bit of a previous
-- byte is now being delivered).
-- The WF_engine_control responds to the request by sending a new address to the WF_production
-- for the retreival of a byte from the memory or the stand-alone bus.
-- The byte becomes available at the byte_request_accept_p_i pulse, 2 cycles after the request,
-- and starts being transmitted at the tx_sched_p_buff (1) of the next FD_TXCK cycle.
-- The WF_engine_control is the one keeping track of the amount of bytes delivered and asserts
-- the last_byte_p_i signal accordingly; after the arrival of this signal the serializer's FSM
-- proceeds with the transmission of the CRC and the FES bytes and then goes back to idle.
-- To add a rubust layer of protection to the FSM, we have added a counter, dependant only on the
-- system clock, that from any state can bring the FSM back to idle. At any bit rate the
-- transmission of the longest RP_DAT should not last more than 35ms. Hence, we have generated a
-- 21 bits counter that will bring the machine back to idle if more than 52ms (complete 21 bit
-- counter) have passed since it has left this idle state.
---------------------------------------------------------------------------------------------------
-- Serializer's FSM --
---------------------------------------------------------------------------------------------------
......@@ -193,9 +209,9 @@ begin
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
tx_state <= idle;
tx_st <= idle;
else
tx_state <= nx_tx_state;
tx_st <= nx_tx_st;
end if;
end if;
end process;
......@@ -203,97 +219,99 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Combinatorial process Serializer_FSM_Comb_State_Transitions
Serializer_FSM_Comb_State_Transitions: process (tx_state, last_byte_p_i, s_bit_index_is_zero,
Serializer_FSM_Comb_State_Transitions: process (tx_st, last_byte_p_i, s_bit_index_is_zero,
s_session_timedout,tx_start_p_i, tx_sched_p_buff_i)
begin
nx_tx_state <= idle;
nx_tx_st <= idle;
case tx_state is
case tx_st is
when idle =>
if tx_start_p_i = '1' then
nx_tx_state <= sync_to_txck;
if tx_start_p_i = '1' then -- trigger from wf_engine_control
nx_tx_st <= sync_to_txck;
else
nx_tx_state <= idle;
nx_tx_st <= idle;
end if;
when sync_to_txck =>
when sync_to_txck => -- synch to the free running FD_TXTCK
if s_session_timedout = '1' then
nx_tx_state <= idle;
nx_tx_st <= idle;
elsif tx_sched_p_buff_i(c_TX_SCHED_BUFF_LGTH-4) = '1' then
nx_tx_state <= send_fss;
nx_tx_st <= send_fss;
else
nx_tx_state <= sync_to_txck;
nx_tx_st <= sync_to_txck;
end if;
when send_fss =>
when send_fss => -- delivery of 2 FSS bytes
if s_session_timedout = '1' then
nx_tx_state <= idle;
nx_tx_st <= idle;
elsif (s_bit_index_is_zero = '1') and (tx_sched_p_buff_i(c_TX_SCHED_BUFF_LGTH-1) = '1') then
nx_tx_state <= send_data_byte;
nx_tx_st <= send_data_byte;
else
nx_tx_state <= send_fss;
nx_tx_st <= send_fss;
end if;
when send_data_byte =>
when send_data_byte => -- delivery of several data bytes
-- until the last_byte_p_i notification
if s_session_timedout = '1' then
nx_tx_state <= idle;
nx_tx_st <= idle;
elsif last_byte_p_i = '1' then
nx_tx_state <= send_crc_bytes;
nx_tx_st <= send_crc_bytes;
else
nx_tx_state <= send_data_byte;
nx_tx_st <= send_data_byte;
end if;
when send_crc_bytes =>
when send_crc_bytes => -- delivery of 2 CRC bytes
if s_session_timedout = '1' then
nx_tx_state <= idle;
nx_tx_st <= idle;
elsif (s_bit_index_is_zero = '1') and (tx_sched_p_buff_i(c_TX_SCHED_BUFF_LGTH-2) = '1') then
nx_tx_state <= send_fes; -- state change early enough (tx_sched_p_buff_i(2))
nx_tx_st <= send_fes; -- state change early enough (tx_sched_p_buff_i(2))
-- for the Outgoing_Bits_Index, that is loaded on
-- tx_sched_p_buff_i(3), to get the 31 as top value
else
nx_tx_state <= send_crc_bytes;
nx_tx_st <= send_crc_bytes;
end if;
when send_fes =>
when send_fes => -- delivery of 1 FES byte
if s_session_timedout = '1' then
nx_tx_state <= idle;
nx_tx_st <= idle;
elsif (s_bit_index_is_zero = '1') and (tx_sched_p_buff_i(c_TX_SCHED_BUFF_LGTH-2) = '1') then
nx_tx_state <= stop_transmission; -- state change early enough (tx_sched_p_buff_i(2))
-- for the Outgoing_Bits_Index that is loaded on
-- tx_sched_p_buff_i(3) to get the 15 as top value
nx_tx_st <= stop_transmission; -- state change early enough (tx_sched_p_buff_i(2))
-- for the Outgoing_Bits_Index that is loaded on
-- tx_sched_p_buff_i(3) to get the 15 as top value
else
nx_tx_state <= send_fes;
nx_tx_st <= send_fes;
end if;
when stop_transmission =>
if tx_sched_p_buff_i(c_TX_SCHED_BUFF_LGTH-2) = '1' then
nx_tx_state <= idle;
--
if s_session_timedout = '1' then
nx_tx_st <= idle;
elsif s_session_timedout = '1' then
nx_tx_state <= idle;
elsif tx_sched_p_buff_i(c_TX_SCHED_BUFF_LGTH-2) = '1' then
nx_tx_st <= idle;
else
nx_tx_state <= stop_transmission;
end if;
else
nx_tx_st <= stop_transmission;
end if;
when others =>
nx_tx_state <= idle;
nx_tx_st <= idle;
end case;
end process;
......@@ -301,10 +319,10 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Combinatorial process Serializer_FSM_Comb_Output_Signals
Serializer_FSM_Comb_Output_Signals: process ( tx_state )
Serializer_FSM_Comb_Output_Signals: process ( tx_st )
begin
case tx_state is
case tx_st is
when idle | sync_to_txck =>
......@@ -387,6 +405,7 @@ begin
s_sending_fes <= '0';
s_stop_transmission <= '0';
end case;
end process;
......@@ -400,12 +419,11 @@ Input_Byte_Retrieval: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
s_byte <= (others => '0');
s_data_byte <= (others => '0');
else
if byte_request_accept_p_i = '1' then
s_byte <= byte_i;
s_data_byte <= byte_i;
end if;
end if;
......@@ -418,7 +436,7 @@ Input_Byte_Retrieval: process (uclk_i)
-- Manchester Encoding --
---------------------------------------------------------------------------------------------------
s_data_byte_manch <= f_manch_encoder (s_byte);
s_data_byte_manch <= f_manch_encoder (s_data_byte);
s_crc_bytes_manch <= f_manch_encoder (s_crc_bytes);
......@@ -431,7 +449,7 @@ Input_Byte_Retrieval: process (uclk_i)
-- Instantiation of the CRC unit
crc_generation: WF_crc
port map (
port map(
uclk_i => uclk_i,
nfip_rst_i => nfip_rst_i,
start_crc_p_i => s_start_crc_p,
......@@ -454,97 +472,117 @@ Input_Byte_Retrieval: process (uclk_i)
---------------------------------------------------------------------------------------------------
-- Bits delivery --
-- Bits counter --
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Managment of the pointer that indicates which bit of a manchester encoded byte is to be
-- delivered. According to the state of the FSM, a byte may be a FSS one, or a data byte or a
-- CRC or a FES byte.
Outgoing_Bits_Index: WF_decr_counter
generic map (g_counter_lgth => 5)
port map (
generic map(g_counter_lgth => 5)
port map(
uclk_i => uclk_i,
nfip_rst_i => nfip_rst_i,
counter_top => s_bit_index_top,
counter_load_i => s_bit_index_load,
counter_decr_p_i => s_decr_index_p,
counter_decr_p_i => s_bit_index_decr_p,
-----------------------------------------------
counter_o => s_bit_index,
counter_is_zero_o => s_bit_index_is_zero);
-----------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
s_bit_index_top <= to_unsigned (15, s_bit_index'length) when s_sending_fss = '1' or s_sending_data = '1' else
to_unsigned (s_crc_bytes_manch'length-1, s_bit_index'length) when s_sending_crc = '1' else
to_unsigned (c_FES'length - 1, s_bit_index'length) when s_sending_fes = '1' else
to_unsigned (c_FSS'length - 1, s_bit_index'length);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Combinatorial process that according to the state of the FSM sets the values to the
-- Outgoing_Bits_Index inputs.
s_bit_index_load <= (s_bit_index_is_zero and tx_sched_p_buff_i(c_TX_SCHED_BUFF_LGTH-1)) when
(s_sending_fss = '1' or s_sending_data = '1' or s_sending_crc = '1' or s_sending_fes = '1') else
'1' when s_prepare_to_produce ='1' else
'0';
Bit_Index: process (s_prepare_to_produce,s_sending_fss, s_sending_data, s_sending_crc,
s_sending_fes, s_bit_index_is_zero,tx_sched_p_buff_i)
begin
s_bit_index_decr_p <= tx_sched_p_buff_i(c_TX_SCHED_BUFF_LGTH-1) when
(s_sending_fss = '1' or s_sending_data = '1' or s_sending_crc = '1' or s_sending_fes = '1') else '0';
if s_prepare_to_produce ='1' then
s_bit_index_top <= to_unsigned (c_FSS'length - 1, s_bit_index'length);
s_bit_index_load <= '1';
s_decr_index_p <= '0';
elsif s_sending_fss = '1' then -- sending the 16 FSS manch. bits
s_bit_index_top <= to_unsigned (15, s_bit_index'length);
s_bit_index_load <= s_bit_index_is_zero and tx_sched_p_buff_i(c_TX_SCHED_BUFF_LGTH-1);
s_decr_index_p <= tx_sched_p_buff_i(c_TX_SCHED_BUFF_LGTH-1);
---------------------------------------------------------------------------------------------------
-- Bits delivery --
---------------------------------------------------------------------------------------------------
-- Synchronous process Bits_Delivery: handling of nanoFIP output signal FD_TXD by
-- placing bits of data according to the state of WF_tx_serializer's state machine and to the
-- counter s_bit_index. The delivery takes place upon a tx_sched_p_buff_i(c_TX_SCHED_BUFF_LGTH-3)
-- pulse.
elsif s_sending_data = '1' then -- sending bytes of 16 manch. bits (several loops here)
s_bit_index_top <= to_unsigned (15, s_bit_index'length);
s_bit_index_load <= s_bit_index_is_zero and tx_sched_p_buff_i(c_TX_SCHED_BUFF_LGTH-1);
s_decr_index_p <= tx_sched_p_buff_i(c_TX_SCHED_BUFF_LGTH-1);
Bits_Delivery: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
s_txd <= '0';
else
if tx_sched_p_buff_i(c_TX_SCHED_BUFF_LGTH-3) = '1' then
elsif s_sending_crc = '1' then -- sending the 32 manch. CRC bits
s_bit_index_top <= to_unsigned (s_crc_bytes_manch'length-1, s_bit_index'length);
s_bit_index_load <= s_bit_index_is_zero and tx_sched_p_buff_i(c_TX_SCHED_BUFF_LGTH-1);
s_decr_index_p <= tx_sched_p_buff_i(c_TX_SCHED_BUFF_LGTH-1);
if s_sending_fss = '1' then
s_txd <= c_FSS (to_integer (s_bit_index)); -- FSS: 2 bytes long (no need to resize)
elsif s_sending_data = '1' then
s_txd <= s_data_byte_manch (to_integer (resize(s_bit_index, 4))); -- 1 data-byte at a time
elsif s_sending_fes = '1' then -- sending the 16 manch. FSS
s_bit_index_top <= to_unsigned (c_FES'length - 1, s_bit_index'length);
s_bit_index_load <= s_bit_index_is_zero and tx_sched_p_buff_i(c_TX_SCHED_BUFF_LGTH-1);
s_decr_index_p <= tx_sched_p_buff_i(c_TX_SCHED_BUFF_LGTH-1);
elsif s_sending_crc = '1' then
s_txd <= s_crc_bytes_manch (to_integer (s_bit_index)); -- CRC: 2 bytes long
elsif s_sending_fes = '1' then
s_txd <= c_FES(to_integer (resize(s_bit_index,4))); -- FES: 1 byte
else
s_bit_index_top <= to_unsigned (c_FSS'length - 1, s_bit_index'length);
s_bit_index_load <= '0';
s_decr_index_p <= '0';
else
s_txd <= '0';
end if;
end if;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Instantiation of the unit that according to the state of the FSM and the
-- bits index counter, outputs FSS, data, CRC or FES manchester encoded bits to the txd_o.
-- The unit also generates the tx_enable_o signal.
bits_to_txd: WF_bits_to_txd
port map (
uclk_i => uclk_i,
nfip_rst_i => nfip_rst_i,
txd_bit_index_i => s_bit_index,
data_byte_manch_i => s_data_byte_manch,
crc_byte_manch_i => s_crc_bytes_manch,
sending_fss_i => s_sending_fss,
sending_data_i => s_sending_data,
sending_crc_i => s_sending_crc,
sending_fes_i => s_sending_fes,
stop_transmission_i => s_stop_transmission,
tx_clk_p_i => tx_sched_p_buff_i(c_TX_SCHED_BUFF_LGTH-3),
---------------------------------------------
txd_o => s_txd,
tx_enable_o => tx_enable_o);
---------------------------------------------
---------------------------------------------------------------------------------------------------
-- TXENA generation --
---------------------------------------------------------------------------------------------------
-- Synchronous process FD_TXENA_Generator: The nanoFIP output FD_TXENA is activated at the
-- same moment as the first bit of the PRE starts being delivered and stays asserted until the
-- end of the delivery of the last FES bit.
FD_TXENA_Generator: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
tx_enable_o <= '0';
else
if ((s_sending_fss = '1') or (s_sending_data = '1') or -- tx sending bits
(s_sending_crc = '1') or (s_sending_fes = '1') or (s_stop_transmission = '1')) then
if tx_sched_p_buff_i(c_TX_SCHED_BUFF_LGTH-3) = '1' then
-- in order to synchronise the
tx_enable_o <= '1'; -- activation of tx_enable with the
-- the delivery of the 1st FSS bit
end if; -- FD_TXD (FSS) :________|-----|___________|--------
-- tx_sched_p_buff(1):______|-|___|-|___|-|___|-|___|-|__
-- sending_FSS :___|-------------------------------
-- FD_TXENA :________|--------------------------
else
tx_enable_o <= '0';
end if;
end if;
end if;
end process;
......@@ -557,8 +595,8 @@ Input_Byte_Retrieval: process (uclk_i)
-- way to go back to Idle state, in case any other logic is being stuck.
Session_Timeout_Counter: WF_decr_counter
generic map (g_counter_lgth => 21)
port map (
generic map(g_counter_lgth => 21)
port map(
uclk_i => uclk_i,
nfip_rst_i => nfip_rst_i,
counter_top => (others => '1'),
......@@ -585,6 +623,7 @@ Input_Byte_Retrieval: process (uclk_i)
-- request for a new byte from the WF_prod_bytes_retriever unit (passing from WF_engine_control)
end architecture rtl;
--=================================================================================================
-- architecture end
......
wf_wb_controller.vhd
View file @ caddc235
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- --
-- WF_wb_controller --
-- --
-- |
-- WF_wb_controller |
-- |
---------------------------------------------------------------------------------------------------
-- File WF_wb_controller.vhd
--
-- Description The unit generates the "User Interface WISHBONE" signal ACK, nanoFIP's answer to
-- the user's STBs.
--
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
-- Date 21/01/2011
-- Version v0.01
-- Depends on WF_production
----------------
-- Last changes
-- 21/01/2011 v0.011 EG changed registering
-- File WF_wb_controller.vhd |
-- |
-- Description The unit generates the "User Interface WISHBONE" signal ACK, nanoFIP's answer to |
-- the user's STBs. |
-- |
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 21/01/2011 |
-- Version v0.01 |
-- Depends on WF_production |
---------------- |
-- Last changes |
-- 21/01/2011 v0.011 EG changed registering |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
......@@ -57,9 +57,7 @@ use work.WF_PACKAGE.all; -- definitions of types, constants, entities
-- Entity declaration for WF_wb_controller
--=================================================================================================
entity WF_wb_controller is
port (
entity WF_wb_controller is port(
-- INPUTS
-- nanoFIP User Interface, WISHBONE Slave
wb_clk_i : in std_logic; -- WISHBONE clock
......@@ -71,15 +69,12 @@ entity WF_wb_controller is
-- OUTPUTS
-- Signal from the WF_production_unit
wb_ack_prod_p_o : out std_logic; -- response to a write cycle
-- latching moment of wb_dat_i
-- nanoFIP User Interface, WISHBONE Slave output
wb_ack_p_o : out std_logic -- WISHBONE acknowledge
wb_ack_p_o : out std_logic); -- WISHBONE acknowledge
);
end entity WF_wb_controller;
......@@ -92,6 +87,7 @@ architecture rtl of WF_wb_controller is
signal s_wb_we_synch, s_wb_cyc_synch : std_logic_vector (2 downto 0);
signal s_wb_stb_synch : std_logic_vector (3 downto 0);
--=================================================================================================
-- architecture begin
--=================================================================================================
......@@ -99,7 +95,10 @@ begin
---------------------------------------------------------------------------------------------------
-- Triple buffering of the WISHBONE control signals: stb, cyc, we.
-- Input Synchronizers --
---------------------------------------------------------------------------------------------------
-- Synchronization of the WISHBONE control signals: stb, cyc, we.
WISHBONE_inputs_synchronization: process (wb_clk_i)
begin
......@@ -121,34 +120,35 @@ begin
s_wb_stb_r_edge_p <= (not s_wb_stb_synch(3)) and s_wb_stb_synch(2);
---------------------------------------------------------------------------------------------------
-- Generate_wb_ack_write_p_o: Generation of the wb_ack_write_p signal
-- (acknowledgement from WISHBONE Slave of the write cycle, as a response to the master's storbe).
-- The 1 wb_clk-wide pulse is generated if the wb_cyc and wb_we are asserted and the WISHBONE input
-- address corresponds to an address in the Produced memory block.
Generate_wb_ack_write_p_o: s_wb_ack_write_p <= '1' when ((s_wb_stb_r_edge_p = '1') and
(s_wb_we_synch (2) = '1') and
(s_wb_cyc_synch(2) = '1') and
(wb_adr_id_i = "010"))
else '0';
---------------------------------------------------------------------------------------------------
-- Generate_wb_ack_read_p: Generation of the wb_ack_read_p signal
-- (acknowledgement from WISHBONE Slave of the read cycle, as a response to the master's strobe).
-- The 1 wb_clk-wide pulse is generated if the wb_cyc is asserted, the wb_we is deasserted and the
-- WISHBONE input address corresponds to an address in the Consumed memory block.
Generate_wb_ack_read_p_o: s_wb_ack_read_p <= '1' when ((s_wb_stb_r_edge_p = '1') and
(s_wb_cyc_synch(2) = '1') and
(s_wb_we_synch(2) = '0') and
(wb_adr_id_i(2 downto 1) = "00"))
else '0';
-- ACK outputs Generation --
---------------------------------------------------------------------------------------------------
-- Output Registrer
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Generation of the wb_ack_write_p signal (acknowledgement from WISHBONE Slave of the write cycle,
-- as a response to the master's storbe). The 1 wb_clk-wide pulse is generated if the wb_cyc and
-- wb_we are asserted and the WISHBONE input address corresponds to an address in the Produced
-- memory block.
s_wb_ack_write_p <= '1' when ((s_wb_stb_r_edge_p = '1') and
(s_wb_we_synch (2) = '1') and
(s_wb_cyc_synch(2) = '1') and
(wb_adr_id_i = "010")) else '0';
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Generation of the wb_ack_read_p signal (acknowledgement from WISHBONE Slave of the read cycle,
-- as a response to the master's strobe). The 1 wb_clk-wide pulse is generated if the wb_cyc is
-- asserted, the wb_we is deasserted and the WISHBONE input address corresponds to an address in
-- the Consumed memory block.
s_wb_ack_read_p <= '1' when ((s_wb_stb_r_edge_p = '1') and
(s_wb_cyc_synch(2) = '1') and
(s_wb_we_synch(2) = '0') and
(wb_adr_id_i(2 downto 1) = "00")) else '0';
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Output registrers
WB_ACK_Output_Reg: process (wb_clk_i)
begin
......
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