Commit caddc235 authored by egousiou's avatar egousiou

headers changed; dualClkRAM renamed to dualclkram_512x8.vhd; wf_bits_to_txd unit removed

git-svn-id: http://svn.ohwr.org/cern-fip/trunk/hdl/design@232 7f0067c9-7624-46c7-bd39-3fb5400c0213
parent a1350268
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- --
-- DualClkRAM --
-- --
-- |
-- dualram_512x8 |
-- |
---------------------------------------------------------------------------------------------------
-- File DualClkRAM.vhd
--
-- Description Instantiation of a template ProAsic3 RAM4K9 memory component with
-- o word width : 8 bits and
-- o depth : 512 bytes.
--
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
-- Date 15/12/2010
-- Version v0.02
-- Depends on ProASIC3 lib
----------------
-- Last changes
-- 08/2010 v0.01 EG pepeline not used! data appears in output 1 clock cycle after the
-- address is given (otherwise it was 2 clock cycles later) slack
-- checked and is ok! code cleaned-up and commented
-- 15/12/2010 v0.02 EG comments for BLKA, BLKB; cleaning-up
--
-- File dualram_512x8.vhd |
-- |
-- Description Instantiation of a template ProAsic3 RAM4K9 memory component with |
-- o word width: 8 bits and |
-- o depth : 512 bytes. |
-- |
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 15/12/2010 |
-- Version v0.02 |
-- Depends on ProASIC3 lib |
---------------- |
-- Last changes |
-- 08/2010 v0.01 EG pepeline not used! data appears in output 1 clock cycle after the |
-- address is given (otherwise it was 2 clock cycles later) slack |
-- checked and is ok! code cleaned-up and commented |
-- 15/12/2010 v0.02 EG comments for BLKA, BLKB; cleaning-up |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
......@@ -59,11 +58,10 @@ use PROASIC3.all;
--=================================================================================================
-- Entity declaration for DualClkRAM
-- Entity declaration for dualram_512x8
--=================================================================================================
entity DualClkRAM is
port(
entity dualram_512x8 is port(
-- INPUTS
-- Inputs concerning port A
CLKA : in std_logic; -- clock A for synchronous read/ write operations
......@@ -86,15 +84,14 @@ entity DualClkRAM is
DOUTA : out std_logic_vector (7 downto 0); -- data out A
-- Output concerning port B
DOUTB : out std_logic_vector (7 downto 0) -- data out B
);
end DualClkRAM;
DOUTB : out std_logic_vector (7 downto 0));-- data out B
end dualram_512x8;
--=================================================================================================
-- architecture declaration
--=================================================================================================
architecture RAM4K9 of DualClkRAM is
architecture RAM4K9 of dualram_512x8 is
---------------------------------------------------------------------------------------------------
-- General information concerning RAM4K9: a fully synchronous, true dual-port RAM with an optional
......@@ -142,10 +139,10 @@ architecture RAM4K9 of DualClkRAM is
WENA, WENB,
CLKA, CLKB,
RESET : in std_logic := 'U';
----------------------------------------------------
DOUTA8, DOUTA7, DOUTA6, DOUTA5, DOUTA4, DOUTA3, DOUTA2, DOUTA1, DOUTA0,
DOUTB8, DOUTB7, DOUTB6, DOUTB5, DOUTB4, DOUTB3, DOUTB2, DOUTB1, DOUTB0 : out std_logic
);
DOUTB8, DOUTB7, DOUTB6, DOUTB5, DOUTB4, DOUTB3, DOUTB2, DOUTB1, DOUTB0 : out std_logic);
----------------------------------------------------
end component;
---------------------------------------------------------------------------------------------------
......@@ -172,8 +169,8 @@ architecture RAM4K9 of DualClkRAM is
begin
power_supply_signal : VCC port map (Y => POWER);
ground_signal : GND port map (Y => GROUND);
power_supply_signal : VCC port map(Y => POWER);
ground_signal : GND port map(Y => GROUND);
---------------------------------------------------------------------------------------------------
-- Instantiation of the component RAM4K9.
......@@ -186,7 +183,7 @@ begin
-- o WMODEA, WMODEB : GND (in write mode the output retains the data from the previous read)
A9D8DualClkRAM_R0C0 : RAM4K9
port map (
port map(
-- INPUTS
-- inputs concerning port A
-- data in A (1 byte, (7 downto 0))
......
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--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- --
-- WF_crc --
-- --
-- |
-- WF_crc |
-- |
---------------------------------------------------------------------------------------------------
-- File WF_crc.vhd
-- Description The unit creates the modules for:
-- o the generation of the CRC of serial data,
-- o the verification of an incoming CRC syndrome.
--
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Date 23/02/2011
-- Version v0.04
-- Depends on WF_reset_unit
-- WF_rx_deserializer
-- WF_tx_serializer
----------------
-- Last changes
-- 07/08/2009 v0.02 PAS Entity Ports added, start of architecture content
-- 08/2010 v0.03 EG Data_FCS_select and crc_ready_p_o signals removed,
-- variable v_q_check_mask replaced with a signal,
-- code cleaned-up+commented
-- 02/2011 v0.04 EG s_q_check_mask was not in Syndrome_Verification sensitivity list!
-- xor replaced with if(Syndrome_Verification); processes rewritten;
-- delay on data_bit_ready_p_i removed.
-- File WF_crc.vhd |
-- |
-- Description The unit creates the modules for: |
-- o the generation of the CRC of serial data, |
-- o the verification of an incoming CRC syndrome. |
-- |
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) |
-- Date 23/02/2011 |
-- Version v0.04 |
-- Depends on WF_reset_unit |
-- WF_rx_deserializer |
-- WF_tx_serializer |
---------------- |
-- Last changes |
-- 07/08/2009 v0.02 PAS Entity Ports added, start of architecture content |
-- 08/2010 v0.03 EG Data_FCS_select and crc_ready_p_o signals removed, |
-- variable v_q_check_mask replaced with a signal, |
-- code cleaned-up+commented |
-- 02/2011 v0.04 EG s_q_check_mask was not in Syndrome_Verification sensitivity list! |
-- xor replaced with if(Syndrome_Verification); processes rewritten; |
-- delay on data_bit_ready_p_i removed. |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
......@@ -63,8 +64,7 @@ use work.WF_PACKAGE.all; -- definitions of types, constants, entities
--=================================================================================================
-- Entity declaration for WF_crc
--=================================================================================================
entity WF_crc is
port (
entity WF_crc is port(
-- INPUTS
-- nanoFIP User Interface, General signals
uclk_i : in std_logic; -- 40 MHz clock
......@@ -83,8 +83,7 @@ entity WF_crc is
crc_ok_p_o : out std_logic; -- signals a correct received CRC syndrome
-- Signal to the WF_tx_serializer unit
crc_o : out std_logic_vector (c_CRC_POLY_LGTH-1 downto 0) -- calculated CRC
);
crc_o : out std_logic_vector (c_CRC_POLY_LGTH-1 downto 0)); -- calculated CRC
end entity WF_crc;
......@@ -96,13 +95,17 @@ architecture rtl of WF_crc is
signal s_q, s_q_nx : std_logic_vector (c_CRC_POLY_LGTH - 1 downto 0);
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
---------------------------------------------------------------------------------------------------
-- CRC Calculation --
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- The Gen_16_bit_Register_and_Interconnections generator, follows the scheme of figure A.1
-- of the Annex A 61158-4-7 IEC:2007 and constructs a register of 16 master-slave flip-flops which
-- are interconnected as a linear feedback shift register.
......@@ -116,8 +119,7 @@ begin
end generate;
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Synchronous process CRC_calculation: the process "moves" the shift register described
-- above, for the calculation of the CRC.
......@@ -146,25 +148,18 @@ begin
crc_o <= not s_q;
---------------------------------------------------------------------------------------------------
-- Combinatorial process Syndrome_Verification: On the reception, the CRC is being
-- calculated as data is arriving (same as in the transmission) and it is being compared to the
-- predefined c_CRC_VERIF_POLY. When the CRC calculated from the received data matches the
-- c_CRC_VERIF_POLY, it is implied that a correct CRC word has been received for the preceded
-- data and the signal crc_ok_p_o gives a 1 uclk-wide pulse.
Syndrome_Verification: process (s_q, data_bit_ready_p_i)
begin
if s_q = not c_CRC_VERIF_POLY then
---------------------------------------------------------------------------------------------------
-- CRC Verification --
---------------------------------------------------------------------------------------------------
crc_ok_p_o <= data_bit_ready_p_i;
-- During reception, the CRC is being calculated as data is arriving (same as in the transmission)
-- and it is being compared to the predefined c_CRC_VERIF_POLY. When the CRC calculated from the
-- received data matches the c_CRC_VERIF_POLY, it is implied that a correct CRC word has been
-- received for the preceded data and the signal crc_ok_p_o gives a 1 uclk-wide pulse.
else
crc_ok_p_o <= '0';
crc_ok_p_o <= data_bit_ready_p_i when s_q = not c_CRC_VERIF_POLY else '0';
end if;
end process;
end architecture rtl;
......
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- --
-- WF_decr_counter --
-- --
-- |
-- WF_decr_counter |
-- |
---------------------------------------------------------------------------------------------------
-- File WF_decr_counter.vhd
-- Description Decreasing counter with synchronous reset, load enable and decrease enable
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
-- Date 10/2010
-- Version v0.01
-- Depends on WF_reset_unit
----------------
-- Last changes
-- 10/2010 EG v0.01 first version
-- File WF_decr_counter.vhd |
-- Description Decreasing counter with synchronous reset, load enable and decrease enable |
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 10/2010 |
-- Version v0.01 |
-- Depends on WF_reset_unit |
---------------- |
-- Last changes |
-- 10/2010 EG v0.01 first version |
-- 10/2010 EG v0.01b initial value after reset is all '1' not all '0' |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
......@@ -55,8 +56,8 @@ use work.WF_PACKAGE.all; -- definitions of types, constants, entities
--=================================================================================================
entity WF_decr_counter is
generic (g_counter_lgth : natural := 4); -- default length
port (
generic(g_counter_lgth : natural := 4); -- default length
port(
-- INPUTS
-- nanoFIP User Interface general signal
uclk_i : in std_logic; -- 40 MHz clock
......@@ -73,8 +74,8 @@ entity WF_decr_counter is
-- OUTPUTS
-- Signal to any unit
counter_o : out unsigned (g_counter_lgth-1 downto 0); -- counter
counter_is_zero_o : out std_logic -- empty counter indication
);
counter_is_zero_o : out std_logic); -- empty counter indication
end entity WF_decr_counter;
......@@ -83,8 +84,8 @@ end entity WF_decr_counter;
--=================================================================================================
architecture rtl of WF_decr_counter is
signal s_counter_is_zero : std_logic;
signal s_counter : unsigned (g_counter_lgth-1 downto 0);
signal s_counter : unsigned (g_counter_lgth-1 downto 0);
--=================================================================================================
-- architecture begin
......@@ -100,7 +101,7 @@ begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
s_counter <= (others => '0');
s_counter <= (others => '1');
else
if counter_load_i = '1' then
......@@ -110,19 +111,14 @@ begin
s_counter <= s_counter - 1;
end if;
counter_is_zero_o <= s_counter_is_zero; -- for slack reasons, especially for the
-- 21 bits "session_timeout" counters
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Concurrent assignments
counter_o <= s_counter;
s_counter_is_zero <= '1' when s_counter = to_unsigned(0,s_counter'length) else '0';
counter_is_zero_o <= '1' when s_counter = to_unsigned(0, s_counter'length) else '0';
end architecture rtl;
......
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--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- --
-- WF_incr_counter --
-- --
-- |
-- WF_incr_counter |
-- |
---------------------------------------------------------------------------------------------------
-- File WF_incr_counter.vhd
-- Description Increasing counter with synchronous reset, reinitialise and increase enable
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
-- Date 01/2011
-- Version v0.011
----------------
-- Last changes
-- 10/2010 EG v0.01 first version
-- 01/2011 EG v0.011 counter_full became a constant
-- File WF_incr_counter.vhd |
-- Description Increasing counter with synchronous reset, reinitialise and increase enable |
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 01/2011 |
-- Version v0.011 |
---------------- |
-- Last changes |
-- 10/2010 EG v0.01 first version |
-- 01/2011 EG v0.011 counter_full became a constant |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
......@@ -55,8 +55,8 @@ use work.WF_PACKAGE.all; -- definitions of types, constants, entities
--=================================================================================================
entity WF_incr_counter is
generic (g_counter_lgth : natural := 4); -- default length
port (
generic(g_counter_lgth : natural := 4); -- default length
port(
-- INPUTS
-- nanoFIP User Interface general signal
uclk_i : in std_logic; -- 40 MHz clock
......@@ -69,9 +69,8 @@ entity WF_incr_counter is
-- OUTPUT
-- Signal to any unit
counter_o : out unsigned (g_counter_lgth-1 downto 0); -- counter
counter_is_full_o : out std_logic -- counter full indication
); -- (all bits to '1')
counter_is_full_o : out std_logic); -- counter full indication
-- (all bits to '1')
end entity WF_incr_counter;
......@@ -83,6 +82,7 @@ architecture rtl of WF_incr_counter is
constant c_COUNTER_FULL : unsigned (g_counter_lgth-1 downto 0) := (others => '1');
signal s_counter : unsigned (g_counter_lgth-1 downto 0);
--=================================================================================================
-- architecture begin
--=================================================================================================
......@@ -96,18 +96,16 @@ begin
begin
if rising_edge (uclk_i) then
if reinit_counter_i = '1' then
s_counter <= (others => '0');
s_counter <= (others => '0');
elsif incr_counter_i = '1' then
s_counter <= s_counter + 1;
s_counter <= s_counter + 1;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Concurrent assignments for output signals
counter_o <= s_counter;
counter_is_full_o <= '1' when s_counter = c_COUNTER_FULL else '0';
......
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--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- --
-- WF_model_constr_decoder --
-- --
-- |
-- WF_model_constr_decoder |
-- |
---------------------------------------------------------------------------------------------------
-- File WF_model_constr_decoder.vhd
--
-- Description Generation of the nanoFIP output S_ID and decoding of the inputs C_ID and M_ID.
-- The output S_ID0 is a clock with period the double of uclk's period and the S_ID1
-- is the opposite clock (it is '0' when S_ID0 is '1' and '1' when S_ID0 is '0').
-- Each one of the 4 pins of the M_ID and C_ID can be connected to either Vcc, Gnd,
-- S_ID1 or S_ID0. Like this (after 2 uclk periods) the 8 bits of the Model and
-- Constructor words take a value, according to the table: Gnd 00
-- S_ID0 01
-- S_ID1 10
-- Vcc 11
--
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
-- Date 21/01/2011
-- Version v0.03
-- Depends on WF_reset_unit
----------------
-- Last changes
-- 11/09/2009 v0.01 PAS First version
-- 20/08/2010 v0.02 EG S_ID corrected so that S_ID0 is always the opposite of S_ID1
-- "for" loop replaced with signals concatenation;
-- Counter is of c_RELOAD_MID_CID bits; Code cleaned-up
-- 06/10/2010 v0.03 EG generic c_RELOAD_MID_CID removed;
-- counter unit instantiated
-- 01/2011 v0.031 EG loading aftern the 2nd cycle (no need for 3)
-- File WF_model_constr_decoder.vhd |
-- |
-- Description Generation of the nanoFIP output S_ID and decoding of the inputs C_ID and M_ID. |
-- The output S_ID0 is a clock with period the double of uclk's period and the S_ID1 |
-- is the opposite clock (it is '0' when S_ID0 is '1' and '1' when S_ID0 is '0'). |
-- Each one of the 4 pins of the M_ID and C_ID can be connected to either Vcc, Gnd, |
-- S_ID1 or S_ID0. Like this (after 2 uclk periods) the 8 bits of the Model and |
-- Constructor words take a value, according to the table: Gnd 00 |
-- S_ID0 01 |
-- S_ID1 10 |
-- Vcc 11 |
-- |
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 21/01/2011 |
-- Version v0.03 |
-- Depends on WF_reset_unit |
---------------- |
-- Last changes |
-- 11/09/2009 v0.01 PAS First version |
-- 20/08/2010 v0.02 EG S_ID corrected so that S_ID0 is always the opposite of S_ID1 |
-- "for" loop replaced with signals concatenation; |
-- Counter is of c_RELOAD_MID_CID bits; Code cleaned-up |
-- 06/10/2010 v0.03 EG generic c_RELOAD_MID_CID removed; |
-- counter unit instantiated |
-- 01/2011 v0.031 EG loading aftern the 2nd cycle (no need for 3) |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
......@@ -69,9 +69,7 @@ use work.WF_PACKAGE.all; -- definitions of types, constants, entities
--=================================================================================================
-- Entity declaration for WF_model_constr_decoder
--=================================================================================================
entity WF_model_constr_decoder is
port (
entity WF_model_constr_decoder is port(
-- INPUTS
-- nanoFIP User Interface general signal
uclk_i : in std_logic; -- 40 Mhz clock
......@@ -86,12 +84,11 @@ entity WF_model_constr_decoder is
-- OUTPUTS
-- nanoFIP WorldFIP Settings output
select_id_o : out std_logic_vector (1 downto 0); -- Identification selection
s_id_o : out std_logic_vector (1 downto 0); -- Identification selection
-- Signal to the WF_prod_bytes_retriever unit
constr_id_dec_o : out std_logic_vector (7 downto 0); -- Constructor identification decoded
model_id_dec_o : out std_logic_vector (7 downto 0) -- Model identification decoded
);
model_id_dec_o : out std_logic_vector (7 downto 0));-- Model identification decoded
end entity WF_model_constr_decoder;
......@@ -119,7 +116,7 @@ begin
-- and on the second uclk tick, the values of the odd bits move to the registers s_model_stage2/
-- s_constr_stage2, giving place to all the even bits to be loaded to the s_model_stage1/
-- s_constr_stage1. The loaded odd and even values are combined after the 2 periods to give the
-- decoded outputs model_id_dec_o & constr_id_dec_o.
-- decoded outputs model_id_dec_o & constr_id_dec_o.
Model_Constructor_Decoder: process (uclk_i)
begin
......@@ -163,8 +160,8 @@ begin
-- Instantiation of a counter WF_incr_counter
Free_Counter: WF_incr_counter
generic map (g_counter_lgth => 2)
port map (
generic map(g_counter_lgth => 2)
port map(
uclk_i => uclk_i,
reinit_counter_i => nfip_rst_i,
incr_counter_i => '1',
......@@ -175,13 +172,13 @@ begin
---------------------------------------------------------------------------------------------------
-- Concurrent signal assignment for the output select_id_o
-- Concurrent signal assignment for the output s_id_o
select_id_o <= ((not s_counter(0)) & s_counter(0));-- 2 opposite clocks generated using
-- the LSB of the counter
-- uclk_i: |-|__|-|__|-|__|-|__|-|__|-|_
-- S_ID0 : |----|____|----|____|----|___
-- S_ID1 : |____|----|____|----|____|---
s_id_o <= ((not s_counter(0)) & s_counter(0)); -- 2 opposite clocks generated using
-- the LSB of the counter
-- uclk_i: |-|__|-|__|-|__|-|__|-|__|-|_
-- S_ID0 : |----|____|----|____|----|___
-- S_ID1 : |____|----|____|----|____|---
end architecture rtl;
......
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--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- --
-- WF_prod_permit --
-- --
-- |
-- WF_prod_permit |
-- |
---------------------------------------------------------------------------------------------------
-- File WF_prod_permit.vhd
--
-- Description Generation of the "nanoFIP User Interface, NON_WISHBONE" output signal VAR3_RDY,
-- according to the variable (var_i) that is being treated.
--
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
-- Date 14/1/2011
-- Version v0.01
-- Depends on WF_engine_control
-- WF_reset_unit
----------------
-- Last changes
-- 1/2011 v0.01 EG First version
-- File WF_prod_permit.vhd |
-- |
-- Description Generation of the "nanoFIP User Interface, NON_WISHBONE" output signal VAR3_RDY, |
-- according to the variable (var_i) that is being treated. |
-- |
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 14/1/2011 |
-- Version v0.01 |
-- Depends on WF_engine_control |
-- WF_reset_unit |
---------------- |
-- Last changes |
-- 1/2011 v0.01 EG First version |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
......@@ -58,9 +58,7 @@ use work.WF_PACKAGE.all; -- definitions of types, constants, entities
-- Entity declaration for WF_prod_permit
--=================================================================================================
entity WF_prod_permit is
port (
entity WF_prod_permit is port(
-- INPUTS
-- nanoFIP User Interface, General signals
uclk_i : in std_logic; -- 40 MHz clock
......@@ -74,8 +72,8 @@ entity WF_prod_permit is
-- OUTPUT
-- nanoFIP User Interface, NON-WISHBONE outputs
var3_rdy_o : out std_logic -- signals the user that data can safely be written
);
var3_rdy_o : out std_logic); -- signals the user that data can safely be written
end entity WF_prod_permit;
......@@ -99,9 +97,13 @@ begin
-- corresponding RP_DAT from nanoFIP.
-- Note: A correct ID_DAT frame along with the variable it contained is signaled by the var_i.
-- For produced variables, the signal var_i gets its value (var3, var_presence, var_identif)
-- after the reception of a correct ID_DAT frame (with correct FSS, Control, PDU_TYPE, Length, CRC
-- and FES bytes) and retains it until the end of the transmission of the corresponding RP_DAT.
-- For produced variables, the signal var_i gets its value after the reception of a correct ID_DAT
-- frame (with correct FSS, CTRL, PDU_TYPE, LGTH, CRC and FES bytes) and retains it until the end
-- of the transmission of the corresponding RP_DAT. An example follows:
--
-- frames : ___[ID_DAT,var_3]__[......RP_DAT......]______________[ID_DAT,var_3]___[.....RP_DAT..
-- var_i : var_whatever > < var_3 > < var_whatever > < var_3
-- VAR3_RDY: -------------------|__________________|--------------------------------|___________
VAR_RDY_Generation: process (uclk_i)
begin
......
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