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Mock Turtle
Commit 24c843cd authored by Federico Vaga's avatar Federico Vaga
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Merge remote-tracking branch 'ohwr/proposed_master' into develop

parents 42759da3 f8575c46
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.gitmodules
View file @ 24c843cd
[submodule "hdl/ip_cores/general-cores"]
path = hdl/ip_cores/general-cores
url = git://ohwr.org/hdl-core-lib/general-cores.git
url = https://ohwr.org/project/general-cores.git
[submodule "hdl/ip_cores/wr-cores"]
path = hdl/ip_cores/wr-cores
url = git://ohwr.org/hdl-core-lib/wr-cores.git
url = https://ohwr.org/project/wr-cores.git
[submodule "hdl/ip_cores/vme64x-core"]
path = hdl/ip_cores/vme64x-core
url = git://ohwr.org/hdl-core-lib/vme64x-core.git
url = https://ohwr.org/project/vme64x-core.git
[submodule "hdl/ip_cores/gn4124-core"]
path = hdl/ip_cores/gn4124-core
url = git://ohwr.org/hdl-core-lib/gn4124-core.git
url = https://ohwr.org/project/gn4124-core.git
[submodule "hdl/ip_cores/urv-core"]
path = hdl/ip_cores/urv-core
url = git://ohwr.org/hdl-core-lib/urv-core.git
url = https://ohwr.org/project/urv-core.git
general-cores @ 4e5f7bad
Subproject commit a50772ea3d4687226fbb6339bd951137946c7ad5
Subproject commit 4e5f7badf0b72f51bdb01c63fcdc6d69afb4b750
gn4124-core @ 3899b6ae
Subproject commit 5ffe9f5344e22262d1badeef21b8426d20948368
Subproject commit 3899b6ae77e00dbbe216de94336ca1496c44b040
urv-core @ 193f15db
Subproject commit 5c7e906ceb6b15f53830061c9087cce0befef13a
Subproject commit 193f15dbf7516fa1e0163156bbf41168c1f3044a
wr-cores @ d702dc9e
Subproject commit 7a42cf8e9a39f72955c3fde2126c0b126037eaae
Subproject commit d702dc9ec20a05d29c7ef6de991c2bdd92f6dc29
hdl/rtl/cpu/mt_cpu_cb.vhd
View file @ 24c843cd
......@@ -385,6 +385,7 @@ begin -- arch
U_Local_Interconnect : xwb_crossbar
generic map (
g_VERBOSE => FALSE,
g_NUM_MASTERS => 1,
g_NUM_SLAVES => c_SLAVE_NUM,
g_REGISTERED => TRUE,
......
hdl/rtl/cpu/mt_urv_wrapper.vhd
View file @ 24c843cd
......@@ -58,7 +58,7 @@ architecture arch of mt_urv_wrapper is
if( x(i) = 'U' or x(i) = 'Z' or x(i) = 'X' ) then
found_undef := true;
end if;
if x(i) = '1' or x(i) = 'H' then
tmp(i) := '1';
else
......@@ -70,7 +70,7 @@ architecture arch of mt_urv_wrapper is
if found_undef then
report "Undefined data value read from memory" severity warning;
end if;
-- synthesis translate_on
return x;
end function f_x_to_zero;
......@@ -98,9 +98,9 @@ architecture arch of mt_urv_wrapper is
signal im_addr_muxed : std_logic_vector(31 downto 0);
signal dm_addr, dm_data_s, dm_data_l : std_logic_vector(31 downto 0);
signal dm_data_select : std_logic_vector(3 downto 0);
signal dm_load, dm_store, dm_load_done, dm_store_done, dm_ready : std_logic;
signal dm_addr, dm_data_s, dm_data_l : std_logic_vector(31 downto 0);
signal dm_data_select : std_logic_vector(3 downto 0);
signal dm_load, dm_store, dm_load_done, dm_store_done : std_logic;
signal dm_cycle_in_progress, dm_is_wishbone : std_logic;
......@@ -134,7 +134,6 @@ begin
dm_data_s_o => dm_data_s,
dm_data_l_i => dm_data_l,
dm_data_select_o => dm_data_select,
dm_ready_i => dm_ready,
dm_store_o => dm_store,
dm_load_o => dm_load,
dm_load_done_i => dm_load_done,
......@@ -148,6 +147,9 @@ begin
dbg_mbx_write_i => cpu_csr_i.dbg_mbx_wr_o,
dbg_mbx_data_o => cpu_csr_o.dbg_mbx_i);
-- 1st MByte of the mem is the IRAM
dm_is_wishbone <= '1' when dm_addr(31 downto 20) /= x"000" else '0';
dm_data_write <= not dm_is_wishbone and dm_store;
U_iram : generic_dpram
......@@ -199,9 +201,6 @@ begin
end if;
end process p_iram_host_access;
-- 1st MByte of the mem is the IRAM
dm_is_wishbone <= '1' when dm_addr(31 downto 20) /= x"000" else '0';
-- Wishbone bus arbitration / internal RAM access
p_wishbone_master : process(clk_sys_i)
begin
......@@ -218,21 +217,19 @@ begin
dm_store_done <= '0';
dm_select_wb <= '0';
else
if dm_cycle_in_progress = '0' then -- access to internal memory
if dm_cycle_in_progress = '0' then
if dm_is_wishbone = '0' then
-- access to internal memory
dm_select_wb <= '0';
if dm_store = '1' then
dm_load_done <= '0';
dm_store_done <= '1';
dm_select_wb <= '0';
elsif dm_load = '1' then
dm_load_done <= '1';
dm_store_done <= '0';
dm_select_wb <= '0';
else
dm_store_done <= '0';
dm_load_done <= '0';
dm_select_wb <= '0';
end if;
else
if dm_load = '1' or dm_store = '1' then
......@@ -281,7 +278,6 @@ begin
dm_data_write <= not dm_is_wishbone and dm_store;
dm_data_l <= dm_wb_rdata when dm_select_wb = '1' else dm_mem_rdata;
im_addr_muxed <= ha_im_addr when cpu_rst = '1' else im_addr;
dm_ready <= '1';
p_dbg_insn : process(clk_sys_i)
begin
......
hdl/rtl/endpoint/mt_ethernet_tx_framer.vhd
View file @ 24c843cd
......@@ -64,6 +64,8 @@ begin -- arch
if rst_n_i = '0' then
state <= IDLE;
src_o.valid <= '0';
src_o.last <= '0';
src_o.data <= (others => '0');
else
case state is
when IDLE =>
......@@ -135,7 +137,9 @@ begin -- arch
end if;
end process p_fsm;
-- src_o.tag <= "00";
src_o.error <= '0';
src_o.hdr <= '0';
snk_o.pkt_ready <= '0';
end architecture arch;
hdl/rtl/endpoint/mt_rmq_rx_deframer.vhd
View file @ 24c843cd
......@@ -93,8 +93,11 @@ begin
src_o.error <= snk_i.error;
src_o.valid <= snk_i.valid;
src_o.data <= snk_i.data;
src_o.hdr <= is_header;
-- src_o.tag <= c_MT_STREAM_TAG_HEADER when valid_mask = '0' else c_MT_STREAM_TAG_PAYLOAD;
src_o.hdr <= is_header;
snk_o.pkt_ready <= '0';
p_udp_length_o <= (others => '0');
p_fsm : process(clk_i)
variable next_state : t_state;
......
hdl/rtl/endpoint/mt_rmq_stream_register.vhd
View file @ 24c843cd
......@@ -121,4 +121,6 @@ begin
src_o <= src_out;
snk_o.ready <= ready_reg;
snk_o.pkt_ready <= '0';
end arch;
hdl/rtl/endpoint/mt_wr_sink.vhd
View file @ 24c843cd
......@@ -143,12 +143,13 @@ begin -- arch
almost_full_o => full,
q_valid_o => q_valid);
post_data <= fout(15 downto 0);
src_o.data(15 downto 0) <= post_data;
post_addr <= fout(17 downto 16);
-- src_o.tag <= post_addr;
src_o.last <= q_valid and fout(18);
src_o.error <= '0'; -- fixme
src_o.valid <= q_valid;
post_data <= fout(15 downto 0);
src_o.data(31 downto 16) <= (others => '0');
src_o.data(15 downto 0) <= post_data;
post_addr <= fout(17 downto 16);
src_o.last <= q_valid and fout(18);
src_o.error <= '0'; -- fixme
src_o.valid <= q_valid;
src_o.hdr <= '0';
end arch;
hdl/rtl/endpoint/mt_wr_source.vhd
View file @ 24c843cd
......@@ -72,6 +72,8 @@ begin -- arch
snk_o.ready <= not full;
snk_o.pkt_ready <= '0';
rd <= (not src_i.stall) and status_sent;
we <= (snk_i.valid or snk_i.error) and (not full);
......
hdl/rtl/mock_turtle_core.vhd
View file @ 24c843cd
......@@ -275,6 +275,7 @@ begin -- arch
U_Host_Access_CB : xwb_crossbar
generic map (
g_VERBOSE => FALSE,
g_NUM_MASTERS => 1,
g_NUM_SLAVES => c_HAC_WISHBONE_MASTERS,
g_REGISTERED => TRUE,
......@@ -291,6 +292,7 @@ begin -- arch
U_Shared_Interconnect : xwb_crossbar
generic map (
g_VERBOSE => FALSE,
g_NUM_MASTERS => c_SI_WISHBONE_SLAVES,
g_NUM_SLAVES => c_SI_WISHBONE_MASTERS,
g_REGISTERED => TRUE,
......
hdl/syn/spec_mt_demo/.gitignore
View file @ 24c843cd
......@@ -2,3 +2,4 @@
!.gitignore
!Manifest.py
!spec_mt_demo.ucf
!syn_extra_steps.tcl
hdl/syn/spec_mt_demo/Manifest.py
View file @ 24c843cd
......@@ -11,9 +11,12 @@ syn_project = "spec_mt_demo.xise"
top_module = "spec_mt_demo"
syn_tool = "ise"
syn_post_project_cmd = "$(TCL_INTERPRETER) " + \
fetchto + "/general-cores/tools/sdb_desc_gen.tcl " + \
syn_tool + " $(PROJECT_FILE)"
syn_post_project_cmd = (
"$(TCL_INTERPRETER) " + \
fetchto + "/general-cores/tools/sdb_desc_gen.tcl " + \
syn_tool + " $(PROJECT_FILE);" \
"$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
)
files = [
"spec_mt_demo.ucf",
......
hdl/syn/spec_mt_demo/spec_mt_demo.ucf
View file @ 24c843cd
......@@ -149,14 +149,65 @@ NET "brd_button_i[0]" IOSTANDARD = "LVCMOS18";
NET "brd_button_i[1]" LOC = D21;
NET "brd_button_i[1]" IOSTANDARD = "LVCMOS18";
NET "gn_rst_n_i" TIG;
#----------------------------------------
# IOBs
#----------------------------------------
INST "cmp_gn4124_core/cmp_wrapped_gn4124/cmp_sync_l2p_rdy/sync0" IOB = FALSE;
#===============================================================================
# Timing constraints and exceptions
#===============================================================================
# All input clocks
NET "gn_p2l_clk_p_i" TNM_NET = p2l_clk_p_i;
TIMESPEC TS_p2l_clk_p_i = PERIOD "p2l_clk_p_i" 5 ns HIGH 50%;
NET "gn_p2l_clk_n_i" TNM_NET = p2l_clk_n_i;
TIMESPEC TS_p2l_clk_n_i = PERIOD "p2l_clk_n_i" 5 ns HIGH 50%;
NET "clk_125m_pllref_p_i" TNM_NET = clk_125m_pllref_p_i;
TIMESPEC TS_clk_125m_pllref_p_i = PERIOD "clk_125m_pllref_p_i" 8 ns HIGH 50%;
NET "clk_125m_pllref_n_i" TNM_NET = clk_125m_pllref_n_i;
TIMESPEC TS_clk_125m_pllref_n_i = PERIOD "clk_125m_pllref_n_i" 8 ns HIGH 50%;
#----------------------------------------
# Asynchronous resets
#----------------------------------------
# GN4124
NET "gn_rst_n_i" TIG;
NET "cmp_gn4124_core/cmp_wrapped_gn4124/rst_*" TIG;
# Ignore async reset inputs to reset synchronisers
NET "*/gc_reset_async_in" TIG;
#----------------------------------------
# Cross-clock domain sync
#----------------------------------------
# Declaration of domains
NET "clk_sys" TNM_NET = sys_clk_62_5;
NET "clk_125m_pllref" TNM_NET = clk_125m_pllref;
TIMEGRP "sys_clk" = "sys_clk_62_5" "clk_125m_pllref";
NET "cmp_gn4124_core/cmp_wrapped_gn4124/sys_clk" TNM_NET = pci_sys_clk;
NET "cmp_gn4124_core/cmp_wrapped_gn4124/io_clk" TNM_NET = pci_io_clk;
TIMEGRP "pci_clk" = "pci_sys_clk" "pci_io_clk";
# Exceptions for crossings via gc_sync_ffs
NET "*/gc_sync_ffs_in" TNM_NET = "sync_ffs";
TIMEGRP "pci_sync_ffs" = "sync_ffs" EXCEPT "pci_clk";
TIMEGRP "sys_sync_ffs" = "sync_ffs" EXCEPT "sys_clk";
TIMESPEC TS_pci_sync_ffs = FROM pci_clk TO "pci_sync_ffs" TIG;
TIMESPEC TS_sys_sync_ffs = FROM sys_clk TO "sys_sync_ffs" TIG;
# Exceptions for crossings via gc_sync_register
NET "*/gc_sync_register_in[*]" TNM_NET = "sync_reg";
TIMEGRP "pci_sync_reg" = "sync_reg" EXCEPT "pci_clk";
TIMEGRP "sys_sync_reg" = "sync_reg" EXCEPT "sys_clk";
TIMESPEC TS_pci_sync_reg = FROM pci_clk TO "pci_sync_reg" 5ns DATAPATHONLY;
TIMESPEC TS_sys_62m5_sync_reg = FROM sys_clk_62_5 TO "sys_sync_reg" 16ns DATAPATHONLY;
TIMESPEC TS_sys_125m_sync_reg = FROM clk_125m_pllref TO "sys_sync_reg" 8ns DATAPATHONLY;
hdl/syn/spec_mt_demo/syn_extra_steps.tcl 0 → 100644
View file @ 24c843cd
# get project file from 1st command-line argument
set project_file [lindex $argv 0]
if {![file exists $project_file]} {
report ERROR "Missing file $project_file, exiting."
exit -1
}
xilinx::project open $project_file
# Some of these are not respected by ISE when passed through hdlmake,
# so we add them all ourselves after creating the project
#
# Not respected by ISE when passed through hdlmake:
# 1. Pack I/O Registers/Latches into IOBs
# 2. Register Duplication Map
xilinx::project set "Enable Multi-Threading" "2" -process "Map"
xilinx::project set "Enable Multi-Threading" "4" -process "Place & Route"
xilinx::project set "Pack I/O Registers into IOBs" "Yes"
xilinx::project set "Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs"
xilinx::project set "Register Balancing" "Yes"
#xilinx::project set "Register Duplication Map" "On"
#xilinx::project set "Placer Extra Effort Map" "Normal"
#xilinx::project set "Extra Effort (Highest PAR level only)" "Normal"
xilinx::project save
xilinx::project close
hdl/testbench/include/mock_turtle_driver.svh
View file @ 24c843cd
......@@ -27,7 +27,6 @@
`define __MOCK_TURTLE_DRIVER_INCLUDED
`include "simdrv_defs.svh"
`include "if_wishbone_accessor.svh"
`include "mt_cpu_csr_driver.svh"
`include "mt_queue_message.svh"
`include "mt_hmq_driver.svh"
......@@ -58,16 +57,16 @@ typedef virtual IMockTurtleIRQ vIMockTurtleIRQ;
// The main class, to monitor and drive the complete MT
class MockTurtleDriver;
protected string name;
protected CWishboneAccessor acc;
protected CBusAccessor acc;
protected uint64_t base;
protected uint32_t core_count;
protected MTCPUControl csr;
protected MQueueHost hmq[];
protected MTConfigRom rom;
protected vIMockTurtleIRQ irq;
MTConfigRom rom;
MDebug dbg;
function new ( CWishboneAccessor acc, uint64_t base,
function new ( CBusAccessor acc, uint64_t base,
vIMockTurtleIRQ irq, string name = "" );
this.name = name;
this.acc = acc;
......@@ -84,9 +83,8 @@ class MockTurtleDriver;
$display (tmp);
endtask // mdisplay
task init ( wb_cycle_type_t mode = PIPELINED );
task init ( );
uint32_t slot_count;
wb_set_mode ( mode );
// first init the config ROM, to be able to get core count etc.
rom = new ( acc, base + 'he000 );
rom.init();
......@@ -126,10 +124,6 @@ class MockTurtleDriver;
rom.dump();
endtask // cfg_rom_dump
task wb_set_mode ( wb_cycle_type_t mode );
acc.set_mode ( mode );
endtask // wb_set_mode
task enable_console_irq ( int core, int enable );
csr.uart_int_enable ( core, enable );
endtask // enable_console_irq
......@@ -152,6 +146,15 @@ class MockTurtleDriver;
acc.write (base + 32'h1_0000 + offset, val);
endtask // smem_write
function bit pending_cpu_notifications (uint32_t core);
return ( csr.notify_queue[core].size() != 0 );
endfunction // pending_cpu_notification
task get_single_cpu_notification (int core, ref uint32_t val);
if ( pending_cpu_notifications (core) )
val = csr.notify_queue[core].pop_front();
endtask // get_single_cpu_notification
task get_cpu_notifications (int core, ref t_notify_queue ntf);
ntf = csr.notify_queue[core];
csr.notify_queue[core] = {};
......@@ -161,6 +164,10 @@ class MockTurtleDriver;
msg = hmq[msg.core].receive_message (msg.slot);
endtask // hmq_receive_message
task hmq_peek_message (ref MQueueMsg msg);
msg = hmq[msg.core].peek_message (msg.slot);
endtask // hmq_peek_message
task hmq_send_message (input MQueueMsg msg);
hmq[msg.core].send_message (msg.slot, msg);
endtask // hmq_send_message
......
hdl/testbench/include/mt_config_rom_driver.svh
View file @ 24c843cd
......@@ -28,6 +28,22 @@
`include "simdrv_defs.svh"
`define TRTL_CONFIG_ROM_MQ_ENTRIES_SHIFT 16
`define TRTL_CONFIG_ROM_MQ_ENTRIES_MASK 32'h00FF0000
`define TRTL_CONFIG_ROM_MQ_PAYLOAD_SHIFT 8
`define TRTL_CONFIG_ROM_MQ_PAYLOAD_MASK 32'h0000FF00
`define TRTL_CONFIG_ROM_MQ_HEADER_SHIFT 0
`define TRTL_CONFIG_ROM_MQ_HEADER_MASK 32'h000000FF
`define TRTL_CONFIG_ROM_MQ_SIZE_ENTRIES(_size) (1 << ((_size & `TRTL_CONFIG_ROM_MQ_ENTRIES_MASK) >> \
`TRTL_CONFIG_ROM_MQ_ENTRIES_SHIFT))
`define TRTL_CONFIG_ROM_MQ_SIZE_PAYLOAD(_size) (1 << ((_size & `TRTL_CONFIG_ROM_MQ_PAYLOAD_MASK) >> \
`TRTL_CONFIG_ROM_MQ_PAYLOAD_SHIFT))
`define TRTL_CONFIG_ROM_MQ_SIZE_HEADER(_size) (1 << ((_size & `TRTL_CONFIG_ROM_MQ_HEADER_MASK) >> \
`TRTL_CONFIG_ROM_MQ_HEADER_SHIFT))
class MTConfigRom;
protected CBusAccessor m_acc;
protected uint64_t m_base;
......@@ -72,10 +88,26 @@ class MTConfigRom;
return read(16 + core);
endfunction // getHmqSlotCount
function uint32_t getHmqDimensions(int core, int hmq);
return read(128 + 16 * core + 2 * hmq);
endfunction // getHmqDimensions
function uint32_t getHmqEndpoint(int core, int hmq);
return read(128 + 16 * core + 2 * hmq + 1);
endfunction // getHmqEndpoint
function uint32_t getRmqSlotCount(int core);
return read(24 + core);
endfunction // getRmqSlotCount
function uint32_t getRmqDimensions(int core, int rmq);
return read(256 + 16 * core + 2 * rmq);
endfunction // getRmqDimensions
function uint32_t getRmqEndpoint(int core, int rmq);
return read(256 + 16 * core + 2 * rmq + 1);
endfunction // getRmqEndpoint
task dump ();
int i;
......@@ -109,23 +141,23 @@ class MTConfigRom;
begin
uint32_t val;
$display ( " HMQ #%0d", j );
val = read(128 + 16 * i + 2 * j);
$display ( " Entries bits : %0d", (val & 'h00ff0000) >> 16 );
$display ( " Width bits : %0d", (val & 'h0000ff00) >> 8 );
$display ( " Header bits : %0d", (val & 'h000000ff) );
val = read(128 + 16 * i + 2 * j + 1);
val = getHmqDimensions(i, j);
$display ( " Entries bits : %0d", `TRTL_CONFIG_ROM_MQ_SIZE_ENTRIES(val));
$display ( " Width bits : %0d", `TRTL_CONFIG_ROM_MQ_SIZE_PAYLOAD(val));
$display ( " Header bits : %0d", `TRTL_CONFIG_ROM_MQ_SIZE_HEADER(val));
val = getHmqEndpoint(i, j);
$display ( " Endpoint ID : %0x", val );
end
$display ( " RMQ slots : %0d", rmq_slots );
for ( j = 0; j < hmq_slots; j++ )
for ( j = 0; j < rmq_slots; j++ )
begin
uint32_t val;
$display ( " RMQ #%0d", j );
val = read(256 + 16 * i + 2 * j);
$display ( " Entries bits : %0d", (val & 'h00ff0000) >> 16 );
$display ( " Width bits : %0d", (val & 'h0000ff00) >> 8 );
$display ( " Header bits : %0d", (val & 'h000000ff) );
val = read(256 + 16 * i + 2 * j + 1);
val = getRmqDimensions(i, j);
$display ( " Entries bits : %0d", `TRTL_CONFIG_ROM_MQ_SIZE_ENTRIES(val));
$display ( " Width bits : %0d", `TRTL_CONFIG_ROM_MQ_SIZE_PAYLOAD(val));
$display ( " Header bits : %0d", `TRTL_CONFIG_ROM_MQ_SIZE_HEADER(val));
val = getRmqEndpoint(i, j);
$display ( " Endpoint ID : %0x", val );
end
end
......
hdl/testbench/include/mt_cpu_csr_driver.svh
View file @ 24c843cd
......@@ -37,6 +37,16 @@
`define SMEM_OP_FLIP 5
`define SMEM_OP_TEST_AND_SET 6
`define TRTL_CPU_NOTIFY_APPLICATION_MAX 64
enum {
TRTL_CPU_NOTIFY_APPLICATION = `TRTL_CPU_NOTIFY_APPLICATION_MAX,
TRTL_CPU_NOTIFY_INIT,
TRTL_CPU_NOTIFY_MAIN,
TRTL_CPU_NOTIFY_EXIT,
TRTL_CPU_NOTIFY_ERR
} trtl_cpu_notification;
typedef uint32_t t_notify_queue[$];
class MTCPUControl;
......
hdl/testbench/include/mt_hmq_driver.svh
View file @ 24c843cd
......@@ -189,6 +189,11 @@ class MQueueHost;
return ret;
endfunction // receive_message
function MQueueMsg peek_message (int slot);
MQueueMsg ret = slots_in[slot][$];
return ret;
endfunction // peek_message
function void send_message (int slot, MQueueMsg msg);
slots_out[slot].push_front(msg);
endfunction // send_message
......
hdl/testbench/include/mt_queue_message.svh
View file @ 24c843cd
......@@ -26,6 +26,10 @@
`ifndef __MT_MQUEUE_MSG_INCLUDED
`define __MT_MQUEUE_MSG_INCLUDED
`define TRTL_HMQ_HEADER_FLAG_SYNC (1 << 0)
`define TRTL_HMQ_HEADER_FLAG_ACK (1 << 1)
`define TRTL_HMQ_HEADER_FLAG_RPC (1 << 2)
typedef uint32_t u32_queue[$];
typedef struct {
......
hdl/testbench/mock_turtle_core/main.sv
View file @ 24c843cd
......@@ -152,13 +152,19 @@ module main;
$finish;
endtask // check_final_result
CWishboneAccessor acc;
initial begin
acc = Host.get_accessor();
acc.set_mode (PIPELINED);
$timeformat (-6, 3, "us", 10);
#10us;
drv = new (Host.get_accessor(), mt_base, IrqMonitor);
drv = new (acc, mt_base, IrqMonitor);
drv.init();
......
hdl/testbench/mt_eth_ep/main.sv
View file @ 24c843cd
......@@ -154,15 +154,22 @@ module main;
MockTurtleDriver drv;
CWishboneAccessor acc;
initial begin
automatic WBPacketSink sink = new(U_wrf_sink.get_accessor());
automatic WBPacketSource src = new(U_wrf_source.get_accessor());
$timeformat (-6, 3, "us", 10);
acc = Host.get_accessor();
acc.set_mode (PIPELINED);
#10us;
drv = new (Host.get_accessor(), mt_base, IrqMonitor);
drv = new (acc, mt_base, IrqMonitor);
drv.init();
......
hdl/testbench/spec_mt_demo/.gitignore
View file @ 24c843cd
......@@ -3,3 +3,4 @@ Makefile
modelsim.ini
transcript*
*.wlf
NullFile
hdl/testbench/spec_mt_demo/Manifest.py
View file @ 24c843cd
......@@ -15,6 +15,7 @@ include_dirs = [
"../include/regs/",
"../../ip_cores/general-cores/sim/",
"../../ip_cores/urv-core/rtl/",
"../../ip_cores//gn4124-core/hdl/gn4124core/sim/gn4124_bfm",
]
files = [
......
hdl/testbench/spec_mt_demo/main.sv
View file @ 24c843cd
......@@ -22,23 +22,22 @@
// and limitations under the License.
//------------------------------------------------------------------------------
`include "mock_turtle_driver.svh"
`include "vhd_wishbone_master.svh"
`timescale 1ns/1ps
`include "gn4124_bfm.svh"
`include "mock_turtle_driver.svh"
module main;
IGN4124PCIMaster Host ();
reg clk_125m = 0;
always #4ns clk_125m <= ~clk_125m;
// the Device Under Test
spec_mt_demo #
(
.g_sim_bypass_pcie(1)
)
DUT
spec_mt_demo
DUT
(
.clk_125m_pllref_p_i (clk_125m),
.clk_125m_pllref_n_i (~clk_125m),
......@@ -46,36 +45,29 @@ module main;
.fp_led_red_o (),
.brd_button_i (),
.brd_led_o (),
.sim_wb_i (Host.out),
.sim_wb_o (Host.in),
.gn_rst_n_i (),
.gn_p2l_clk_n_i (),
.gn_p2l_clk_p_i (),
.gn_p2l_rdy_o (),
.gn_p2l_dframe_i (),
.gn_p2l_valid_i (),
.gn_p2l_data_i (),
.gn_p_wr_req_i (),
.gn_p_wr_rdy_o (),
.gn_rx_error_o (),
.gn_l2p_clkn_o (),
.gn_l2p_clkp_o (),
.gn_l2p_dframe_o (),
.gn_l2p_valid_o (),
.gn_l2p_edb_o (),
.gn_l2p_data_o (),
.gn_l2p_rdy_i (),
.gn_l_wr_rdy_i (),
.gn_p_rd_d_rdy_i (),
.gn_tx_error_i (),
.gn_vc_rdy_i (),
.gn_rst_n_i (Host.rst_n),
.gn_p2l_clk_n_i (Host.p2l_clk_n),
.gn_p2l_clk_p_i (Host.p2l_clk_p),
.gn_p2l_rdy_o (Host.p2l_rdy),
.gn_p2l_dframe_i (Host.p2l_dframe),
.gn_p2l_valid_i (Host.p2l_valid),
.gn_p2l_data_i (Host.p2l_data),
.gn_p_wr_req_i (Host.p_wr_req),
.gn_p_wr_rdy_o (Host.p_wr_rdy),
.gn_rx_error_o (Host.rx_error),
.gn_l2p_clkn_o (Host.l2p_clk_n),
.gn_l2p_clkp_o (Host.l2p_clk_p),
.gn_l2p_dframe_o (Host.l2p_dframe),
.gn_l2p_valid_o (Host.l2p_valid),
.gn_l2p_edb_o (Host.l2p_edb),
.gn_l2p_data_o (Host.l2p_data),
.gn_l2p_rdy_i (Host.l2p_rdy),
.gn_l_wr_rdy_i (Host.l_wr_rdy),
.gn_p_rd_d_rdy_i (Host.p_rd_d_rdy),
.gn_tx_error_i (Host.tx_error),
.gn_vc_rdy_i (Host.vc_rdy),
.gn_gpio_b ());
IVHDWishboneMaster Host
(
.clk_i (DUT.clk_sys),
.rst_n_i (DUT.rst_sys_n));
IMockTurtleIRQ IrqMonitor (`MT_ATTACH_IRQ(DUT.U_Mock_Turtle));
string fw = "../../../demos/hello_world/firmware/fw-01/fw-hello.bin";
......@@ -84,14 +76,17 @@ module main;
MockTurtleDriver drv;
CBusAccessor acc;
initial begin
$timeformat (-6, 3, "us", 10);
@(posedge DUT.rst_sys_n);
@(posedge DUT.clk_sys);
wait (Host.ready == 1'b1);
acc = Host.get_accessor();
drv = new (Host.get_accessor(), mt_base, IrqMonitor);
drv = new (acc, mt_base, IrqMonitor);
drv.init();
......
hdl/testbench/svec_mt_demo/main.sv
View file @ 24c843cd
......@@ -99,14 +99,20 @@ module main;
MockTurtleDriver drv;
CWishboneAccessor acc;
initial begin
acc = Host.get_accessor();
acc.set_mode (PIPELINED);
$timeformat (-6, 3, "us", 10);
@(posedge DUT.rst_n_sys);
@(posedge DUT.clk_sys);
drv = new (Host.get_accessor(), mt_base, IrqMonitor);
drv = new (acc, mt_base, IrqMonitor);
drv.init();
......
hdl/top/spec_mt_demo/spec_mt_demo.vhd
View file @ 24c843cd
......@@ -41,9 +41,6 @@ library unisim;
use unisim.vcomponents.all;
entity spec_mt_demo is
generic (
-- Bypass PCIE core, useful only in simulation
g_SIM_BYPASS_PCIE : boolean := FALSE);
port (
-- resets and clocks
clk_125m_pllref_p_i : in std_logic;
......@@ -54,11 +51,6 @@ entity spec_mt_demo is
-- SPEC board LEDs and buttons
brd_button_i : in std_logic_vector(1 downto 0);
brd_led_o : out std_logic_vector(3 downto 0);
-- Bypass PCIE core, useful only in simulation
-- synthesis translate_off
sim_wb_i : in t_wishbone_slave_in := cc_dummy_slave_in;
sim_wb_o : out t_wishbone_slave_out;
-- synthesis translate_on
-- Gennum PCI interface
gn_rst_n_i : in std_logic;
gn_p2l_clk_n_i : in std_logic;
......@@ -133,11 +125,9 @@ architecture arch of spec_mt_demo is
signal clk_sys : std_logic;
signal clk_sys_locked : std_logic;
signal rst_sys_n : std_logic;
signal rstlogic_arst_n : std_logic;
signal gn_rst_n_p : std_logic;
signal gn_wbadr : std_logic_vector(31 downto 0);
signal rst_sys_n : std_logic;
signal rstlogic_arst : std_logic;
signal gn_rst_n_p : std_logic;
signal pllout_clk_sys : std_logic;
signal pllout_clk_fb_pllref : std_logic;
......@@ -192,7 +182,7 @@ begin -- architecture arch
I => pllout_clk_sys);
-- Detect when gn_rst_n_i goes high (end of reset) and use this edge to
-- generate rstlogic_arst_n. This is needed to connect optional PCIe
-- generate rstlogic_arst. This is needed to connect optional PCIe
-- reset. When board runs standalone, we need to ignore PCIe reset being
-- constantly low.
cmp_arst_edge: gc_sync_ffs
......@@ -204,19 +194,17 @@ begin -- architecture arch
data_i => gn_rst_n_i,
npulse_o => gn_rst_n_p);
-- logic AND of all (possibly) async reset sources (active low)
rstlogic_arst_n <= clk_sys_locked and (not gn_rst_n_p);
-- logic AND of all (possibly) async reset sources (active high)
rstlogic_arst <= (not clk_sys_locked) and gn_rst_n_p;
cmp_rstlogic_reset : gc_reset
cmp_rstlogic_reset : gc_reset_multi_aasd
generic map (
g_clocks => 1,
g_logdelay => 4,
g_syncdepth => 3)
g_CLOCKS => 1,
g_RST_LEN => 16)
port map (
free_clk_i => clk_125m_pllref,
locked_i => rstlogic_arst_n,
arst_i => rstlogic_arst,
clks_i(0) => clk_sys,
rstn_o(0) => rst_sys_n);
rst_n_o(0) => rst_sys_n);
U_Intercon : xwb_sdb_crossbar
generic map (
......@@ -251,72 +239,40 @@ begin -- architecture arch
irqs_i(3) => mt_notify_irq,
irq_master_o => vic_master_irq);
gen_with_pcie_core : if not g_SIM_BYPASS_PCIE generate
cmp_gn4124_core : gn4124_core
port map (
rst_n_a_i => gn_rst_n_i,
status_o => open,
p2l_clk_p_i => gn_p2l_clk_p_i,
p2l_clk_n_i => gn_p2l_clk_n_i,
p2l_data_i => gn_p2l_data_i,
p2l_dframe_i => gn_p2l_dframe_i,
p2l_valid_i => gn_p2l_valid_i,
p2l_rdy_o => gn_p2l_rdy_o,
p_wr_req_i => gn_p_wr_req_i,
p_wr_rdy_o => gn_p_wr_rdy_o,
rx_error_o => gn_rx_error_o,
vc_rdy_i => gn_vc_rdy_i,
l2p_clk_p_o => gn_l2p_clkp_o,
l2p_clk_n_o => gn_l2p_clkn_o,
l2p_data_o => gn_l2p_data_o,
l2p_dframe_o => gn_l2p_dframe_o,
l2p_valid_o => gn_l2p_valid_o,
l2p_edb_o => gn_l2p_edb_o,
l2p_rdy_i => gn_l2p_rdy_i,
l_wr_rdy_i => gn_l_wr_rdy_i,
p_rd_d_rdy_i => gn_p_rd_d_rdy_i,
tx_error_i => gn_tx_error_i,
dma_irq_o => open,
irq_p_i => vic_master_irq,
irq_p_o => gn_gpio_b(0),
dma_reg_clk_i => clk_sys,
dma_reg_adr_i => (others => '0'),
dma_reg_dat_i => (others => '0'),
dma_reg_sel_i => (others => '0'),
dma_reg_stb_i => '0',
dma_reg_we_i => '0',
dma_reg_cyc_i => '0',
csr_clk_i => clk_sys,
csr_adr_o => gn_wbadr,
csr_dat_o => cnx_master_out(c_MASTER_PCIE).dat,
csr_sel_o => cnx_master_out(c_MASTER_PCIE).sel,
csr_stb_o => cnx_master_out(c_MASTER_PCIE).stb,
csr_we_o => cnx_master_out(c_MASTER_PCIE).we,
csr_cyc_o => cnx_master_out(c_MASTER_PCIE).cyc,
csr_dat_i => cnx_master_in(c_MASTER_PCIE).dat,
csr_ack_i => cnx_master_in(c_MASTER_PCIE).ack,
csr_stall_i => cnx_master_in(c_MASTER_PCIE).stall,
csr_err_i => cnx_master_in(c_MASTER_PCIE).err,
csr_rty_i => cnx_master_in(c_MASTER_PCIE).rty,
dma_clk_i => clk_sys,
dma_dat_i => (others => '0'),
dma_ack_i => '1',
dma_stall_i => '0',
dma_err_i => '0',
dma_rty_i => '0');
-- "translating" word addressing of Gennum module into byte addressing
cnx_master_out(c_MASTER_PCIE).adr(1 downto 0) <= (others => '0');
cnx_master_out(c_MASTER_PCIE).adr(18 downto 2) <= gn_wbadr(16 downto 0);
cnx_master_out(c_MASTER_PCIE).adr(31 downto 19) <= (others => '0');
end generate gen_with_pcie_core;
gen_without_pcie_core : if g_SIM_BYPASS_PCIE generate
-- synthesis translate_off
cnx_master_out(c_MASTER_PCIE) <= sim_wb_i;
sim_wb_o <= cnx_master_in(c_MASTER_PCIE);
-- synthesis translate_on
end generate gen_without_pcie_core;
cmp_gn4124_core : xwb_gn4124_core
port map (
rst_n_a_i => gn_rst_n_i,
status_o => open,
p2l_clk_p_i => gn_p2l_clk_p_i,
p2l_clk_n_i => gn_p2l_clk_n_i,
p2l_data_i => gn_p2l_data_i,
p2l_dframe_i => gn_p2l_dframe_i,
p2l_valid_i => gn_p2l_valid_i,
p2l_rdy_o => gn_p2l_rdy_o,
p_wr_req_i => gn_p_wr_req_i,
p_wr_rdy_o => gn_p_wr_rdy_o,
rx_error_o => gn_rx_error_o,
vc_rdy_i => gn_vc_rdy_i,
l2p_clk_p_o => gn_l2p_clkp_o,
l2p_clk_n_o => gn_l2p_clkn_o,
l2p_data_o => gn_l2p_data_o,
l2p_dframe_o => gn_l2p_dframe_o,
l2p_valid_o => gn_l2p_valid_o,
l2p_edb_o => gn_l2p_edb_o,
l2p_rdy_i => gn_l2p_rdy_i,
l_wr_rdy_i => gn_l_wr_rdy_i,
p_rd_d_rdy_i => gn_p_rd_d_rdy_i,
tx_error_i => gn_tx_error_i,
dma_irq_o => open,
irq_p_i => vic_master_irq,
irq_p_o => gn_gpio_b(1),
wb_master_clk_i => clk_sys,
wb_master_rst_n_i => rst_sys_n,
wb_master_i => cnx_master_in(c_MASTER_PCIE),
wb_master_o => cnx_master_out(c_MASTER_PCIE));
-- drive unused GN GPIO output
gn_gpio_b(0) <= '0';
U_Mock_Turtle : mock_turtle_core
generic map (
......
software/firmware/Makefile
View file @ 24c843cd
......@@ -138,6 +138,9 @@ $(build_output).bin: $(build_output).elf
$(build_output).bram: $(build_output).bin
$(MEM_INIT_GEN) -i $(build_output).bin > $(build_output).bram
$(build_output).bram: $(build_output).bin
$(MEM_INIT_GEN) -i $(build_output).bin > $(build_output).bram
$(BUILDDIR)/urv/emulate.o: urv/emulate.c
${CC} $(DEPFLAGS) $(CFLAGS) -march=rv32i -c $< -o $@
$(POSTCOMPILE)
......
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