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MasterFIP - Gateware
Commit eaf3913c authored by Evangelia Gousiou's avatar Evangelia Gousiou
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-updated masterfip core: up to 263 frame bytes, corrected core reset, added… 

-updated masterfip core: up to 263 frame bytes, corrected core reset, added ext_sync and adc supply signals, ucf.
-updated testbench
parent df522070
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rtl/fmc_masterFIP_core.vhd
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rtl/fmc_masterFIP_mezz.vhd deleted 100644 → 0
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rtl/fmc_masterfip_csr.vhd
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rtl/masterFIP_pkg.vhd
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rtl/masterfip_rx.vhd
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rtl/masterfip_tx.vhd
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rtl/wbgen/fmc_masterfip_csr.wb
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sim/spec/data_vectors/masterFIP_test.vec
View file @ eaf3913c
......@@ -29,120 +29,122 @@ wait %d900
-------------------------------------------------------------------------------
--------------- RESETS ---------------
-- reset inactive
wr 0000000000050000 F CAFE0003
wr 0000000000030000 F CAFE0003
wait %d20
-- reset active
wr 0000000000050000 F CAFE0000
wr 0000000000030000 F CAFE0000
wait %d20
-- reset inactive
wr 0000000000050000 F CAFE0003
wr 0000000000030000 F CAFE0003
wait %d20
----- CHECK COUNTERS FUNCTINALITY -----
-- macrocycle cnt start
wr 0000000000030018 F 80007D00
wait %d20
-- turnar counter top
wr 0000000000050014 F 000007D0
wr 000000000003001C F 000007D0
wait %d20
-- silen counter top
wr 0000000000050018 F 00000FA0
wr 0000000000030020 F 00000FA0
wait %d20
-- macrocycle cnt start
wr 0000000000050010 F 80007D00
wait %d20
--------------- ID_DAT ---------------
tx_rst
wr 000000000005002C F 00000001
wr 0000000000030034 F 00000001
wait %d10
wr 000000000005002C F 00000000
wr 0000000000030034 F 00000000
wait %d20
-- control byte of id_dat
wr 00000000000500C4 F 00000003
wr 0000000000030154 F 00000003
wait %d20
-- data bytes varid = 0503 for agent to consume
wr 00000000000500C8 F 00000305
wr 0000000000030158 F 00000305
wait %d20
-- tx_start
wr 000000000005002C F 00000202
wr 0000000000030034 F 00000202
wait %d20000
--------------- RP_DAT ---------------
tx_rst
wr 000000000005002C F 00000001
wr 0000000000030034 F 00000001
wait %d10
wr 000000000005002C F 00000000
wr 0000000000030034 F 00000000
wait %d20
-- control byte of rp_dat
wr 00000000000500c4 F 00000002
wr 0000000000030154 F 00000002
wait %d20
-- data bytes
wr 00000000000500c8 F BBAA0340
wr 0000000000030158 F BBAA0340
wait %d20
wr 00000000000500cc F EEDDCC05
wr 000000000003015c F EEDDCC05
wait %d20
wr 00000000000500d0 F 0A090807
wr 0000000000030160 F 0A090807
wait %d20
wr 00000000000500D4 F 0E0D0C0B
wr 0000000000030164 F 0E0D0C0B
wait %d20
wr 00000000000500D8 F 06060605
wr 0000000000030168 F 06060605
wait %d20
-- tx_start
wr 000000000005002C F 00000502
wr 0000000000030034 F 00000502
wait %d40000
--------------- ID_DAT ---------------
tx_rst
wr 000000000005002C F 00000001
wr 0000000000030034 F 00000001
wait %d10
wr 000000000005002C F 00000000
wr 0000000000030034 F 00000000
wait %d20
-- control byte of id_dat
wr 00000000000500c4 F 00000003
wr 0000000000030154 F 00000003
wait %d20
-- data bytes varid = 1403 for agent to send identification
wr 00000000000500c8 F 00000314
wr 0000000000030158 F 00000314
wait %d20
-- tx_start
wr 000000000005002C F 00000202
wr 0000000000030034 F 00000202
wait %d20
-- deactivate tx_start
wr 000000000005002C F 00000000
wr 0000000000030034 F 00000000
-- release rx_rst
wr 0000000000050038 F 00000000
wr 0000000000030040 F 00000000
wait %d40000
-- read received data
rd 0000000000050040 F 00000002
rd 0000000000030048 F 00000002
wait %d20
rd 0000000000050044 F 00000050
rd 000000000003004c F 00000050
--------------- RP_FIN ---------------
-- control byte of rp_fin
wr 00000000000500C4 F 00000040
wr 0000000000030154 F 00000040
wait %d20
-- rx_rst
wr 0000000000050038 F 00000001
wr 0000000000030040 F 00000001
wait %d20
-- tx_start
wr 000000000005002C F 00000002
wr 0000000000030034 F 00000002
wait %d20000
\ No newline at end of file
sim/spec/testbench/tb_masterFIP.vhd
View file @ eaf3913c
......@@ -59,6 +59,10 @@ architecture behavioral of tb_masterFIP is
tx_error_i : in std_logic; -- Transmit Error
irq_p_o : out std_logic; -- Interrupt request pulse to GN4124 GPIO
ext_sync_i : in std_logic;
speed_b0_i : in std_logic;
speed_b1_i : in std_logic;
fd_rxcdn_i : in std_logic;
fd_rxd_i : in std_logic;
fd_txer_i : in std_logic;
......@@ -314,6 +318,8 @@ signal spec_led_red : std_logic;
signal consu_data : std_logic_vector (15 downto 0);
signal nanoFIP_rxcdn, nanoFIP_txena, nanoFIP_txck, nanoFIP_rstno ,nanoFIP_wdgn : std_logic;
signal nanoFIP_clk : std_logic:='0';
signal ext_sync : std_logic := '0';
-- GN4124 interface
signal rst_n : std_logic;
......@@ -388,7 +394,11 @@ begin
l_wr_rdy_i => l_wr_rdy,
p_rd_d_rdy_i => p_rd_d_rdy,
tx_error_i => tx_error,
irq_p_o => irq_p,
ext_sync_i => ext_sync,
speed_b0_i => '0',
speed_b1_i => '1',
fd_rxcdn_i => fd_rxcdn,
fd_rxd_i => fd_rxd,
......@@ -426,7 +436,7 @@ begin
fd_txena_o => nanoFIP_txena,
nostat_i => '1',
rstin_i => not (rst_n),
rstin_i => (rst_n),--was not
rstpon_i => '1',
slone_i => '1',
uclk_i => nanoFIP_clk,
......@@ -596,6 +606,9 @@ begin
nanoFIP_clk <= not (nanoFIP_clk) after 1 ns;
wait for nanoFIP_clk_period/2;
end process;
ext_sync <= '1' after 8500 ns, '0' after 8580 ns;
rst_n <= RSTOUT18n;
GPIO(0) <= irq_p;
......
syn/spec/spec_masterFIP.xise
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syn/spec_wrnode/spec_masterfip_wrnode.xise
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top/spec/spec_masterFIP.ucf
View file @ eaf3913c
......@@ -67,6 +67,32 @@ NET "led_rx_err_n_o" IOSTANDARD = "LVCMOS25";
NET "led_rx_act_n_o" LOC = A20;
NET "led_rx_act_n_o" IOSTANDARD = "LVCMOS25";
NET "bus_term_en_n_o" LOC = Y13;
NET "bus_term_en_n_o" IOSTANDARD = "LVCMOS25";
NET "ext_sync_term_en_o" LOC = AB13;
NET "ext_sync_term_en_o" IOSTANDARD = "LVCMOS25";
NET "ext_sync_i" LOC = T8;
NET "ext_sync_i" IOSTANDARD = "LVCMOS25";
NET "ext_sync_tst_n_o" LOC = U8;
NET "ext_sync_tst_n_o" IOSTANDARD = "LVCMOS25";
NET "ext_sync_oe_o" LOC = W6;
NET "ext_sync_oe_o" IOSTANDARD = "LVCMOS25";
NET "ext_sync_dir_o" LOC = Y6;
NET "ext_sync_dir_o" IOSTANDARD = "LVCMOS25";
NET "adc_1v8_shdn_n_o" LOC = V17;
NET "adc_1v8_shdn_n_o" IOSTANDARD = "LVCMOS25";
NET "adc_m5v_shdn_n_o" LOC = W18;
NET "adc_m5v_shdn_n_o" IOSTANDARD = "LVCMOS25";
NET "adc_5v_en_n_o" LOC = R9;
NET "adc_5v_en_n_o" IOSTANDARD = "LVCMOS25";
#NET "mezz_onewire_b" LOC = "A19";
#NET "mezz_onewire_b" IOSTANDARD = "LVCMOS25";
......
top/spec/spec_masterFIP.vhd
View file @ eaf3913c
......@@ -147,6 +147,21 @@ entity spec_masterFIP is
-- Bus Speed
speed_b0_i : in std_logic;
speed_b1_i : in std_logic;
-- Bus termination
bus_term_en_n_o : out std_logic;
-- External synchronisation pulse transceiver
ext_sync_term_en_o : out std_logic;
ext_sync_dir_o : out std_logic;
ext_sync_oe_o : out std_logic;
ext_sync_tst_n_o : out std_logic;
ext_sync_i : in std_logic;
-- Power supplies for the ADC
adc_1v8_shdn_n_o : out std_logic;
adc_m5v_shdn_n_o : out std_logic;
adc_5v_en_n_o : out std_logic;
-- FielDrive
fd_rxcdn_i : in std_logic;
......@@ -184,11 +199,10 @@ architecture rtl of spec_masterFIP is
-- Note: All address in sdb and crossbar are BYTE addresses!
-- Master ports on the wishbone crossbar
constant c_NUM_WB_MASTERS : integer := 4;
constant c_NUM_WB_MASTERS : integer := 3;
constant c_WB_SLAVE_SPEC_ONEWIRE: integer := 0; -- Carrier onewire interface
constant c_WB_SLAVE_SPEC_INFO : integer := 1; -- Info on SPEC control and status registers
constant c_WB_SLAVE_VIC : integer := 2; -- Interrupt controller
constant c_WB_SLAVE_MASTERFIP : integer := 3; -- TDC core configuration
constant c_WB_SLAVE_MASTERFIP : integer := 2; -- TDC core configuration
-- SDB header address
constant c_SDB_ADDRESS : t_wishbone_address := x"00000000";
......@@ -197,21 +211,13 @@ architecture rtl of spec_masterFIP is
constant c_NUM_WB_SLAVES : integer := 1;
constant c_MASTER_GENNUM : integer := 0;
constant c_FMC_MASTERFIP_SDB_BRIDGE : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"0001FFFF", x"00000000");
constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(5 downto 0) :=
constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(4 downto 0) :=
(0 => f_sdb_embed_device (c_ONEWIRE_SDB_DEVICE, x"00010000"),
1 => f_sdb_embed_device (c_SPEC_INFO_SDB_DEVICE, x"00020000"),
2 => f_sdb_embed_device (c_xwb_vic_sdb, x"00030000"), -- c_xwb_vic_sdb described in the wishbone_pkg
3 => f_sdb_embed_bridge (c_FMC_MASTERFIP_SDB_BRIDGE, x"00040000"),
4 => f_sdb_embed_repo_url (c_sdb_repo_url),
5 => f_sdb_embed_synthesis (c_sdb_synthesis_info));
---------------------------------------------------------------------------------------------------
-- VIC CONSTANT --
---------------------------------------------------------------------------------------------------
constant c_VIC_VECTOR_TABLE : t_wishbone_address_array(0 to 0) := (0 => x"00052000");
2 => f_sdb_embed_device (c_MASTERFIP_SDB_DEVICE, x"00030000"),
3 => f_sdb_embed_repo_url (c_SDB_REPO_URL),
4 => f_sdb_embed_synthesis (c_SDB_SYNTHESIS_INFO));
---------------------------------------------------------------------------------------------------
......@@ -392,6 +398,9 @@ begin
csr_dat_i => cnx_slave_out(c_MASTER_GENNUM).dat,
csr_ack_i => cnx_slave_out(c_MASTER_GENNUM).ack,
csr_stall_i => cnx_slave_out(c_MASTER_GENNUM).stall,
csr_err_i => cnx_slave_out(c_MASTER_GENNUM).err,
csr_rty_i => cnx_slave_out(c_MASTER_GENNUM).rty,
csr_int_i => '0',
-- DMA: not used
dma_clk_i => clk_40m_sys,
dma_adr_o => open,
......@@ -400,7 +409,10 @@ begin
dma_sel_o => open,
dma_stb_o => open,
dma_we_o => open,
dma_err_i => '0',
dma_ack_i => '1',
dma_rty_i => '0',
dma_int_i => '0',
dma_dat_i => (others => '0'),
dma_stall_i => '0',
dma_reg_clk_i => clk_40m_sys,
......@@ -422,38 +434,50 @@ begin
---------------------------------------------------------------------------------------------------
-- masterFIP BOARD --
---------------------------------------------------------------------------------------------------
cmp_masterFIP_mezz : fmc_masterFIP_mezz
cmp_masterFIP_mezz : fmc_masterFIP_core
generic map
(g_span => g_span,
g_width => g_width,
values_for_simul => FALSE)
(g_span => 32,
g_width => 32,
values_for_simul => FALSE)
port map
(clk_sys_i => clk_40m_sys,
rst_sys_n_i => rst_sys_n,
fd_rxcdn_i => fd_rxcdn_i,
fd_rxd_i => fd_rxd_i,
fd_txer_i => fd_txer_i,
fd_wdgn_i => fd_wdgn_i,
fd_rstn_o => fd_rstn_o,
fd_txck_o => fd_txck_o,
fd_txd_o => fd_txd_o,
fd_txena_o => fd_txena,
speed_b0_i => speed_b0_i,
speed_b1_i => speed_b1_i,
(clk_i => clk_40m_sys,
rst_i => rst_sys,
-- FielDrive
fd_rxcdn_i => fd_rxcdn_i,
fd_rxd_i => fd_rxd_i,
fd_txer_i => fd_txer_i,
fd_wdgn_i => fd_wdgn_i,
fd_rstn_o => fd_rstn_o,
fd_txck_o => fd_txck_o,
fd_txd_o => fd_txd_o,
fd_txena_o => fd_txena,
-- Bus bit rate
speed_b0_i => speed_b0_i,
speed_b1_i => speed_b1_i,
-- Bus termination
bus_term_en_n_o => bus_term_en_n_o,
-- External synchronisation pulse transceiver
ext_sync_term_en_o => ext_sync_term_en_o,
ext_sync_dir_o => ext_sync_dir_o,
ext_sync_oe_o => ext_sync_oe_o,
ext_sync_tst_n_o => ext_sync_tst_n_o,
ext_sync_i => ext_sync_i,
-- Power supplies for the ADC
adc_1v8_shdn_n_o => adc_1v8_shdn_n_o,
adc_m5v_shdn_n_o => adc_m5v_shdn_n_o,
adc_5v_en_n_o => adc_5v_en_n_o,
-- WISHBONE interface with the GN4124 core
wb_adr_i => cnx_master_out(c_WB_SLAVE_MASTERFIP).adr,
wb_dat_i => cnx_master_out(c_WB_SLAVE_MASTERFIP).dat,
wb_stb_i => cnx_master_out(c_WB_SLAVE_MASTERFIP).stb,
wb_we_i => cnx_master_out(c_WB_SLAVE_MASTERFIP).we,
wb_cyc_i => cnx_master_out(c_WB_SLAVE_MASTERFIP).cyc,
wb_sel_i => cnx_master_out(c_WB_SLAVE_MASTERFIP).sel,
wb_dat_o => cnx_master_in(c_WB_SLAVE_MASTERFIP).dat,
wb_ack_o => cnx_master_in(c_WB_SLAVE_MASTERFIP).ack,
wb_stall_o => cnx_master_in(c_WB_SLAVE_MASTERFIP).stall,
-- Interrupt line from EIC
wb_irq_o => fmc_eic_irq,
wb_adr_i => "00" & cnx_master_out(c_WB_SLAVE_MASTERFIP).adr(31 downto 2),
wb_dat_i => cnx_master_out(c_WB_SLAVE_MASTERFIP).dat,
wb_stb_i => cnx_master_out(c_WB_SLAVE_MASTERFIP).stb,
wb_we_i => cnx_master_out(c_WB_SLAVE_MASTERFIP).we,
wb_cyc_i => cnx_master_out(c_WB_SLAVE_MASTERFIP).cyc,
wb_sel_i => cnx_master_out(c_WB_SLAVE_MASTERFIP).sel,
wb_dat_o => cnx_master_in(c_WB_SLAVE_MASTERFIP).dat,
wb_ack_o => cnx_master_in(c_WB_SLAVE_MASTERFIP).ack,
wb_stall_o => cnx_master_in(c_WB_SLAVE_MASTERFIP).stall,
-- Aux
aux_o => aux);
aux_o => aux);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Unused wishbone signals
cnx_master_in(c_WB_SLAVE_MASTERFIP).err <= '0';
......@@ -474,7 +498,7 @@ begin
port map (
clk_i => clk_40m_sys,
rst_n_i => rst_sys_n,
pulse_i => aux(2),
pulse_i => aux(0),
extended_o => rx_err);
cmp_rx_act_extend_p : gc_extend_pulse
......@@ -486,23 +510,6 @@ begin
pulse_i => aux(1),
extended_o => rx_act);
---------------------------------------------------------------------------------------------------
-- VIC --
---------------------------------------------------------------------------------------------------
cmp_vic : xwb_vic
generic map
(g_interface_mode => PIPELINED,
g_address_granularity => BYTE,
g_num_interrupts => 1,
g_init_vectors => c_VIC_VECTOR_TABLE)
port map
(clk_sys_i => clk_40m_sys,
rst_n_i => rst_sys_n,
slave_i => cnx_master_out(c_WB_SLAVE_VIC),
slave_o => cnx_master_in(c_WB_SLAVE_VIC),
irqs_i(0) => fmc_eic_irq,
irq_master_o => irq_to_gn4124);
---------------------------------------------------------------------------------------------------
-- Carrier 1-wire MASTER DS18B20 (thermometer + unique ID) --
......@@ -525,7 +532,7 @@ begin
owr_i => carrier_owr_i);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
carrier_onewire_b <= '0' when carrier_owr_en(0) = '1' else 'Z';
carrier_onewire_b <= '0' when carrier_owr_en(0) = '1' else 'Z';
carrier_owr_i(0) <= carrier_onewire_b;
......
top/spec_wrnode/spec_top.ucf
View file @ eaf3913c
......@@ -201,6 +201,38 @@ NET "speed_b1_i" LOC = AB5;
NET "speed_b1_i" IOSTANDARD = "LVCMOS25";
NET "bus_term_en_n_o" LOC = Y13;
NET "bus_term_en_n_o" IOSTANDARD = "LVCMOS25";
NET "ext_sync_term_en_o" LOC = AB13;
NET "ext_sync_term_en_o" IOSTANDARD = "LVCMOS25";
NET "ext_sync_i" LOC = T8;
NET "ext_sync_i" IOSTANDARD = "LVCMOS25";
NET "ext_sync_tst_n_o" LOC = U8;
NET "ext_sync_tst_n_o" IOSTANDARD = "LVCMOS25";
NET "ext_sync_oe_o" LOC = W6;
NET "ext_sync_oe_o" IOSTANDARD = "LVCMOS25";
NET "ext_sync_dir_o" LOC = Y6;
NET "ext_sync_dir_o" IOSTANDARD = "LVCMOS25";
NET "adc_1v8_shdn_n_o" LOC = V17;
NET "adc_1v8_shdn_n_o" IOSTANDARD = "LVCMOS25";
NET "adc_m5v_shdn_n_o" LOC = W18;
NET "adc_m5v_shdn_n_o" IOSTANDARD = "LVCMOS25";
NET "adc_5v_en_n_o" LOC = R9;
NET "adc_5v_en_n_o" IOSTANDARD = "LVCMOS25";
NET "led_tx_err_n_o" LOC = C19;
NET "led_tx_err_n_o" IOSTANDARD = "LVCMOS25";
......
top/spec_wrnode/spec_top.vhd
View file @ eaf3913c
......@@ -6,7 +6,7 @@
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT
-- Created : 2014-04-01
-- Last update: 2015-10-06
-- Last update: 2015-08-14
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -45,6 +45,7 @@
library ieee;
use ieee.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.wishbone_pkg.all;
......@@ -106,7 +107,7 @@ entity spec_top is
tx_error : in std_logic; -- transmit error
vc_rdy : in std_logic_vector(1 downto 0); -- channel ready
-- font panel leds
-- front panel leds
led_red : out std_logic;
led_green : out std_logic;
......@@ -119,6 +120,20 @@ entity spec_top is
-- Bus Speed
speed_b0_i : in std_logic;
speed_b1_i : in std_logic;
-- Bus termination
bus_term_en_n_o : out std_logic; -- 150 Ohms termination of the bus -- check again
-- External synchronisation pulse transceiver
ext_sync_term_en_o : out std_logic; -- enable 50 Ohms termination of the pulse
ext_sync_dir_o : out std_logic; -- transceiver direction
ext_sync_oe_o : out std_logic; -- transceiver output enable
ext_sync_tst_n_o : out std_logic; -- emulation of the LEMO input
ext_sync_i : in std_logic; -- sync pulse
-- Power supplies for the ADC
adc_1v8_shdn_n_o : out std_logic;
adc_m5v_shdn_n_o : out std_logic;
adc_5v_en_n_o : out std_logic;
-- FielDrive
fd_rxcdn_i : in std_logic;
......@@ -153,16 +168,16 @@ architecture rtl of spec_top is
(
out_slot_count => 4,
out_slot_config => (
0 => (width => 128, entries => 4), -- control CPU 0 (to host)
1 => (width => 128, entries => 4), -- control CPU 1 (to host)
2 => (width => 128, entries => 4), -- log CPU 0
3 => (width => 128, entries => 4), -- log CPU 1
0 => (width => 128, entries => 8), -- control CPU 0 (to host)
1 => (width => 128, entries => 8), -- control CPU 1 (to host)
2 => (width => 16, entries => 128), -- log CPU 0
3 => (width => 16, entries => 128), -- log CPU 1
others => (0, 0)),
in_slot_count => 2,
in_slot_config => (
0 => (width => 128, entries => 4), -- control CPU 0 (from host)
1 => (width => 128, entries => 4), -- control CPU 1 (from host)
0 => (width => 32, entries => 8), -- control CPU 0 (from host)
1 => (width => 32, entries => 8), -- control CPU 1 (from host)
others => (0, 0)
)
);
......@@ -176,12 +191,12 @@ architecture rtl of spec_top is
(
out_slot_count => 1,
out_slot_config => (
0 => (width => 128, entries => 4), -- TDC remote out
0 => (width => 128, entries => 16), -- TDC remote out
others => (0, 0)),
in_slot_count => 1,
in_slot_config => (
0 => (width => 128, entries => 4), -- FD remote in
0 => (width => 128, entries => 16), -- FD remote in
others => (0, 0)
)
......@@ -191,7 +206,7 @@ architecture rtl of spec_top is
(
app_id => x"0f1dc03e",
cpu_count => 2,
cpu_memsizes => (65536, 65536, 0, 0, 0, 0, 0, 0),
cpu_memsizes => (32768, 32768, 0, 0, 0, 0, 0, 0),
hmq_config => c_hmq_config,
rmq_config => c_rmq_config,
shared_mem_size => 65536
......@@ -214,6 +229,10 @@ architecture rtl of spec_top is
signal rx_err, rx_act, fd_txena : std_logic;
signal aux : std_logic_vector(7 downto 0);
-- LEDs
signal led_clk_40m_divider : unsigned(22 downto 0);
signal led_clk_40m_aux : std_logic_vector(7 downto 0);
begin
U_Node_Template : spec_node_template
......@@ -274,38 +293,45 @@ begin
fmc0_host_irq_i => '0'
);
cmp_masterFIP_mezz : fmc_masterFIP_mezz
cmp_masterFIP_core : fmc_masterFIP_core
generic map
(g_span => 32,
g_width => 32,
values_for_simul => g_simulation)
(g_span => 32,
g_width => 32,
values_for_simul => g_simulation)
port map
(clk_sys_i => clk_sys,
rst_sys_n_i => rst_n_sys,
fd_rxcdn_i => fd_rxcdn_i,
fd_rxd_i => fd_rxd_i,
fd_txer_i => fd_txer_i,
fd_wdgn_i => fd_wdgn_i,
fd_rstn_o => fd_rstn_o,
fd_txck_o => fd_txck_o,
fd_txd_o => fd_txd_o,
fd_txena_o => fd_txena,
speed_b0_i => speed_b0_i,
speed_b1_i => speed_b1_i,
(clk_i => clk_sys,
rst_i => not(rst_n_sys),
fd_rxcdn_i => fd_rxcdn_i,
fd_rxd_i => fd_rxd_i,
fd_txer_i => fd_txer_i,
fd_wdgn_i => fd_wdgn_i,
fd_rstn_o => fd_rstn_o,
fd_txck_o => fd_txck_o,
fd_txd_o => fd_txd_o,
fd_txena_o => fd_txena,
speed_b0_i => speed_b0_i,
speed_b1_i => speed_b1_i,
bus_term_en_n_o => bus_term_en_n_o,
ext_sync_term_en_o => ext_sync_term_en_o,
ext_sync_dir_o => ext_sync_dir_o,
ext_sync_oe_o => ext_sync_oe_o,
ext_sync_tst_n_o => ext_sync_tst_n_o,
ext_sync_i => ext_sync_i,
adc_1v8_shdn_n_o => adc_1v8_shdn_n_o,
adc_m5v_shdn_n_o => adc_m5v_shdn_n_o,
adc_5v_en_n_o => adc_5v_en_n_o,
-- WISHBONE interface with the GN4124 core
wb_adr_i => fmc_dp_wb_out.adr,
wb_dat_i => fmc_dp_wb_out.dat,
wb_stb_i => fmc_dp_wb_out.stb,
wb_we_i => fmc_dp_wb_out.we,
wb_cyc_i => fmc_dp_wb_out.cyc,
wb_sel_i => fmc_dp_wb_out.sel,
wb_dat_o => fmc_dp_wb_in.dat,
wb_ack_o => fmc_dp_wb_in.ack,
wb_stall_o => fmc_dp_wb_in.stall,
-- Interrupt line from EIC
wb_irq_o => open,
wb_adr_i => fmc_dp_wb_out.adr,
wb_dat_i => fmc_dp_wb_out.dat,
wb_stb_i => fmc_dp_wb_out.stb,
wb_we_i => fmc_dp_wb_out.we,
wb_cyc_i => fmc_dp_wb_out.cyc,
wb_sel_i => fmc_dp_wb_out.sel,
wb_dat_o => fmc_dp_wb_in.dat,
wb_ack_o => fmc_dp_wb_in.ack,
wb_stall_o => fmc_dp_wb_in.stall,
-- Aux
aux_o => aux);
aux_o => aux);
fmc_dp_wb_in.err <= '0';
......@@ -314,8 +340,8 @@ begin
fd_txena_o <= fd_txena;
-- LEDs font panel
led_tx_err_n_o <= fd_txer_i;
-- LEDs front panel
--led_tx_err_n_o <= fd_txer_i;
led_tx_act_n_o <= fd_txena;
led_rx_err_n_o <= rx_err;
led_rx_act_n_o <= rx_act;
......@@ -336,7 +362,30 @@ begin
clk_i => clk_sys,
rst_n_i => rst_n_sys,
pulse_i => aux(1),
extended_o => rx_act);
extended_o => rx_act);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
clk_40m_sys_drive_led: process (clk_sys)
begin
if rising_edge(clk_sys) then
if(rst_n_sys = '0') then
led_clk_40m_aux <= "01111111";
led_clk_40m_divider <= (others => '0');
else
led_clk_40m_divider <= led_clk_40m_divider+ 1;
if(led_clk_40m_divider = 0) then
led_clk_40m_aux <= led_clk_40m_aux(6 downto 0) & led_clk_40m_aux(7);
end if;
end if;
end if;
end process;
-- -- -- -- --
led_tx_err_n_o <= led_clk_40m_aux(0);
end rtl;
......
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