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MasterFIP - Gateware
Commit eaf3913c authored by Evangelia Gousiou's avatar Evangelia Gousiou
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-updated masterfip core: up to 263 frame bytes, corrected core reset, added… 

-updated masterfip core: up to 263 frame bytes, corrected core reset, added ext_sync and adc supply signals, ucf.
-updated testbench
parent df522070
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rtl/fmc_masterFIP_core.vhd
View file @ eaf3913c
......@@ -56,47 +56,57 @@ use work.genram_pkg.all;
--=================================================================================================
entity fmc_masterFIP_core is
generic
(g_span : integer := 32; -- address span in bus interfaces
g_width : integer := 32; -- data width in bus interfaces
values_for_simul : boolean := FALSE); -- this generic is set to TRUE
-- when instantiated in a test-bench
(g_span : integer := 32; -- address span in bus interfaces
g_width : integer := 32; -- data width in bus interfaces
values_for_simul : boolean := FALSE); -- this generic is set to TRUE when instantiated in a test-bench
port
(-- Clock and reset
clk_i : in std_logic; --
rst_i : in std_logic; --
-- Bus Speed
speed_b0_i : in std_logic;
speed_b1_i : in std_logic;
clk_i : in std_logic; -- 40 MHz clock
rst_i : in std_logic; -- PoR or PCIe reset, synched with the clk_i
-- Bus Speed -- 31.25 Kbps: speed_b1 = 0, speed_b0 = 0
speed_b0_i : in std_logic; -- 1 Mbps : speed_b1 = 0, speed_b0 = 1
speed_b1_i : in std_logic; -- 2.5 Mbps : speed_b1 = 1, speed_b0 = 0
-- 5 Mbps : speed_b1 = 1, speed_b0 = 1
-- Bus termination
bus_term_en_n_o : out std_logic; -- 150 Ohms termination of the bus -- check again
-- External synchronisation pulse transceiver
ext_sync_term_en_o : out std_logic; -- enable 50 Ohms termination of the pulse
ext_sync_dir_o : out std_logic; -- transceiver direction
ext_sync_oe_o : out std_logic; -- transceiver output enable
ext_sync_tst_n_o : out std_logic; -- emulation of the LEMO input
ext_sync_i : in std_logic; -- sync pulse
-- Power supplies for the ADC
adc_1v8_shdn_n_o : out std_logic;
adc_m5v_shdn_n_o : out std_logic;
adc_5v_en_n_o : out std_logic;
-- FielDrive
fd_rxcdn_i : in std_logic;
fd_rxd_i : in std_logic;
fd_txer_i : in std_logic;
fd_wdgn_i : in std_logic;
fd_rstn_o : out std_logic;
fd_txck_o : out std_logic;
fd_txd_o : out std_logic;
fd_txena_o : out std_logic;
-- Interrupts
irq_p_o : out std_logic_vector(7 downto 0); -- vector that groups all sources if irqs
fd_rxcdn_i : in std_logic;
fd_rxd_i : in std_logic;
fd_txer_i : in std_logic;
fd_wdgn_i : in std_logic;
fd_rstn_o : out std_logic;
fd_txck_o : out std_logic;
fd_txd_o : out std_logic;
fd_txena_o : out std_logic;
-- WISHBONE classic bus interface
wb_adr_i : in std_logic_vector(g_span-1 downto 0);
wb_dat_i : in std_logic_vector(g_width-1 downto 0);
wb_stb_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_we_i : in std_logic;
wb_cyc_i : in std_logic;
wb_stall_o : out std_logic;
wb_ack_o : out std_logic;
wb_dat_o : out std_logic_vector(g_width-1 downto 0);
-- Aux
aux_o : out std_logic_vector(7 downto 0); -- group of 8 aux signals to pass to the higher levels
-- WISHBONE bus interface with the GN4124/VME core for the configuration of the core
wb_adr_i : in std_logic_vector(g_span-1 downto 0); -- WISHBONE classic address
wb_dat_i : in std_logic_vector(g_width-1 downto 0); -- WISHBONE classic data in
wb_stb_i : in std_logic; -- WISHBONE classic strobe
wb_sel_i : in std_logic_vector(3 downto 0); -- WISHBONE classic select
wb_we_i : in std_logic; -- WISHBONE classic write enable
wb_cyc_i : in std_logic; -- WISHBONE classic cycle
wb_stall_o : out std_logic; -- WISHBONE classic stall
wb_ack_o : out std_logic; -- WISHBONE classic acknowledge
wb_dat_o : out std_logic_vector(g_width-1 downto 0)); -- WISHBONE classic data out
end fmc_masterFIP_core;
aux_o : out std_logic_vector(7 downto 0)); -- group of 8 aux signals to pass to the higher levels
end fmc_masterFIP_core;
--=================================================================================================
......@@ -104,64 +114,55 @@ end fmc_masterFIP_core;
--=================================================================================================
architecture rtl of fmc_masterFIP_core is
constant c_RST_UNLOCK_VALUE : std_logic_vector(15 downto 0) := x"cafe";
signal rst_n, core_rst, rx_rst : std_logic;
-- control unit
signal tx_byte_index, rx_byte_index : std_logic_vector (7 downto 0);
-- masterfip_rx outputs
signal rx_fss_received_p, rx_fss_crc_fes_ok_p : std_logic;
signal rx_crc_wrong_p, rx_byte_ready_p : std_logic;
signal rx_byte : std_logic_vector (7 downto 0);
signal rx_data_bytes : std_logic_vector (8 downto 0);
-- wf_production outputs
signal byte_to_tx : std_logic_vector (7 downto 0);
-- masterfip_tx outputs
signal tx_completed_p : std_logic;
-- resets
signal core_sw_rstn_tmp, fd_sw_rstn_tmp : std_logic;--_vector (0 downto 0);
signal core_sw_rst, fd_sw_rst : std_logic;
signal core_sw_rst_p, core_sw_rst_n, fd_sw_rst_n : std_logic;
signal core_sw_rstn_lock : std_logic_vector (15 downto 0);
constant c_RST_UNLOCK_VALUE : std_logic_vector(15 downto 0) := x"cafe";
signal rst_n, core_rst, core_rst_n, rx_rst, rx_rst_p : std_logic;
signal core_rstn_tmp, fd_rstn_tmp, rstn_lock_wr : std_logic;--_vector (0 downto 0);
signal core_host_rst, fd_host_rst, core_host_rstn, fd_host_rstn : std_logic;
signal rstn_lock : std_logic_vector(15 downto 0);
-- speed
signal speed_host : std_logic_vector (1 downto 0);
signal speed_ok : std_logic;
signal speed_host : std_logic_vector(1 downto 0);
signal speed_ok : std_logic;
-- ext pulse
signal ext_sync_p : std_logic;
-- counters
signal macrocyc_lgth, turnar_lgth, silen_lgth : std_logic_vector (30 downto 0);
signal macrocyc_sw_load, turnar_sw_load, silen_sw_load : std_logic;
signal macrocyc_sw_load_p, turnar_sw_load_p, silen_sw_load_p : std_logic;
signal macrocyc_cnt, turnar_cnt, silen_cnt : std_logic_vector (30 downto 0);
signal macrocyc_cnt_zero_p, turnar_cnt_zero_p, silen_cnt_zero_p : std_logic;
signal macrocyc_lgth, turnar_lgth, silen_lgth : std_logic_vector(30 downto 0);
signal macrocyc_sw_load, turnar_sw_load, silen_sw_load : std_logic;
signal macrocyc_sw_load_p, turnar_sw_load_p, silen_sw_load_p : std_logic;
signal macrocyc_cnt, turnar_cnt, silen_cnt : std_logic_vector(30 downto 0);
signal macrocyc_cnt_zero_p : std_logic;
-- tx
signal tx_rst, tx_start, tx_start_p : std_logic;
signal tx_bytes_num : std_logic_vector (8 downto 0);
signal tx_frame : tx_frame_t;
signal tx_ctrl_byte : std_logic_vector (7 downto 0);
signal tx_completed_p, tx_rst, tx_start, tx_start_p : std_logic;
signal tx_frame : tx_frame_t;
signal tx_ctrl_byte : std_logic_vector(7 downto 0);
signal tx_bytes_num, tx_byte_index : std_logic_vector(8 downto 0); -- up to 263 bytes
-- rx
signal rx_pream_ok, rx_frame_ok_p, fd_txena : std_logic;
signal rx_frame : rx_frame_t;
signal rx_ctrl_byte : std_logic_vector (7 downto 0);
signal rx_fss_received_p, rx_fss_received, rx_fss_crc_fes_ok_p : std_logic;
signal rx_frame_ok_p, rx_crc_wrong_p, rx_byte_ready_p, fd_txena : std_logic;
signal rx_frame : rx_frame_t;
signal rx_ctrl_byte, rx_byte : std_logic_vector(7 downto 0);
signal rx_byte_index, rx_data_bytes : std_logic_vector(8 downto 0); -- up to 263 bytes
-- Chipscope
component chipscope_ila
port (
CONTROL : inout std_logic_vector(35 downto 0);
CLK : in std_logic;
TRIG0 : in std_logic_vector(31 downto 0);
TRIG1 : in std_logic_vector(31 downto 0);
TRIG2 : in std_logic_vector(31 downto 0);
TRIG3 : in std_logic_vector(31 downto 0));
end component;
component chipscope_icon
port (
CONTROL0 : inout std_logic_vector (35 downto 0));
end component;
signal CONTROL : std_logic_vector(35 downto 0);
signal CLK : std_logic;
signal TRIG0 : std_logic_vector(31 downto 0);
signal TRIG1 : std_logic_vector(31 downto 0);
signal TRIG2 : std_logic_vector(31 downto 0);
signal TRIG3 : std_logic_vector(31 downto 0);
-- component chipscope_ila
-- port (
-- CONTROL : inout std_logic_vector(35 downto 0);
-- CLK : in std_logic;
-- TRIG0 : in std_logic_vector(31 downto 0);
-- TRIG1 : in std_logic_vector(31 downto 0);
-- TRIG2 : in std_logic_vector(31 downto 0);
-- TRIG3 : in std_logic_vector(31 downto 0));
-- end component;
-- component chipscope_icon
-- port (
-- CONTROL0 : inout std_logic_vector (35 downto 0));
-- end component;
-- signal CONTROL : std_logic_vector(35 downto 0);
-- signal CLK : std_logic;
-- signal TRIG0 : std_logic_vector(31 downto 0);
-- signal TRIG1 : std_logic_vector(31 downto 0);
-- signal TRIG2 : std_logic_vector(31 downto 0);
-- signal TRIG3 : std_logic_vector(31 downto 0);
--=================================================================================================
......@@ -169,156 +170,251 @@ architecture rtl of fmc_masterFIP_core is
--=================================================================================================
begin
rst_n <= not rst_i;
---------------------------------------------------------------------------------------------------
-- REGISTERS --
---------------------------------------------------------------------------------------------------
cmp_masterfip_csr: fmc_masterfip_csr
port map(
-- wishbone
rst_n_i => rst_n,
clk_sys_i => clk_i,
wb_adr_i => wb_adr_i(6 downto 0),
wb_dat_i => wb_dat_i,
wb_dat_o => wb_dat_o,
wb_cyc_i => wb_cyc_i,
wb_sel_i => wb_sel_i,
wb_stb_i => wb_stb_i,
wb_we_i => wb_we_i,
wb_ack_o => wb_ack_o,
wb_stall_o => wb_stall_o,
rst_n_i => rst_n,
clk_sys_i => clk_i,
wb_adr_i => wb_adr_i(7 downto 0),
wb_dat_i => wb_dat_i,
wb_dat_o => wb_dat_o,
wb_cyc_i => wb_cyc_i,
wb_sel_i => wb_sel_i,
wb_stb_i => wb_stb_i,
wb_we_i => wb_we_i,
wb_ack_o => wb_ack_o,
wb_stall_o => wb_stall_o,
-- resets
mf_rst_core_o => core_sw_rstn_tmp,
mf_rst_fd_o => fd_sw_rstn_tmp,
mf_rst_lock_o => core_sw_rstn_lock,
mf_rst_lock_wr_o => core_sw_rst_p,
-- config
mf_config_host_speed_o => speed_host,
mf_config_host_ext_sync_term_en_n_o => open,
mf_config_host_subs_o => open,
mf_config_fmc_speed_i(1) => speed_b1_i,
mf_config_fmc_speed_i(0) => speed_b0_i,
mf_config_fmc_speed_ok_i => speed_ok,
mf_rstn_core_o => core_rstn_tmp, -- reset has to be confirmed with lock word
mf_rstn_fd_o => fd_rstn_tmp, -- reset has to be confirmed with lock word
mf_rstn_lock_o => rstn_lock,
mf_rstn_lock_wr_o => rstn_lock_wr,
-- adc supplies
mf_adc_1v8_shdn_n_o => adc_1v8_shdn_n_o,
mf_adc_m5v_shdn_n_o => adc_m5v_shdn_n_o,
mf_adc_5v_en_n_o => adc_5v_en_n_o,
-- external sync pulse
mf_ext_sync_term_en_o => ext_sync_term_en_o,
mf_ext_sync_dir_o => ext_sync_dir_o,
mf_ext_sync_oe_o => ext_sync_oe_o,
mf_ext_sync_tst_n_o => ext_sync_tst_n_o,
mf_ext_sync_tstamp_i => "00000000000000000000000000000000", -- external sync tstamp
-- bus termination
mf_bus_term_en_n_o => bus_term_en_n_o,
-- bus speed
mf_speed_i(1) => speed_b1_i,
mf_speed_i(0) => speed_b0_i,
-- counters outputs
mf_macrocyc_lgth_o => macrocyc_lgth,
mf_macrocyc_start_o => macrocyc_sw_load,
mf_turnar_lgth_o => turnar_lgth,
mf_turnar_start_o => turnar_sw_load,
mf_silen_lgth_o => silen_lgth,
mf_silen_start_o => silen_sw_load,
mf_macrocyc_lgth_o => macrocyc_lgth,
mf_macrocyc_start_o => macrocyc_sw_load,
mf_turnar_lgth_o => turnar_lgth,
mf_turnar_start_o => turnar_sw_load,
mf_silen_lgth_o => silen_lgth,
mf_silen_start_o => silen_sw_load,
-- counters inputs
mf_macrocyc_time_cnt_i => (macrocyc_cnt_zero_p or macrocyc_sw_load_p) & macrocyc_cnt,
mf_turnar_time_cnt_i => (tx_completed_p or turnar_sw_load_p) & turnar_cnt,
mf_silen_time_cnt_i => (tx_completed_p or silen_sw_load_p) & silen_cnt,
-- external sync pulse termination
mf_ext_sync_tstamp_i => "00000000000000000000000000000000",
-- tx control/status
mf_tx_rst_o => tx_rst, -- have to convert to pulse
mf_tx_start_o => tx_start, -- have to convert to pulse
mf_tx_bytes_num_o => tx_bytes_num,
mf_tx_stop_i => tx_completed_p, -- have to extend the pulse
mf_fd_wdgn_i => fd_wdgn_i,
mf_fd_txer_i => fd_txer_i,
mf_macrocyc_time_cnt_i => (macrocyc_cnt_zero_p or macrocyc_sw_load_p) & macrocyc_cnt,
mf_turnar_time_cnt_i => (tx_completed_p or turnar_sw_load_p) & turnar_cnt,
mf_silen_time_cnt_i => (tx_completed_p or silen_sw_load_p) & silen_cnt,
-- tx control
mf_tx_ctrl_rst_o => tx_rst, -- tx rst have to convert to pulse
mf_tx_ctrl_start_o => tx_start, -- tx start serializing a frame have to convert to pulse
mf_tx_ctrl_bytes_num_o => tx_bytes_num, -- number of bytes to serialize
-- tx status
mf_tx_stat_stop_i => tx_completed_p, -- pulse upon the end of delivery of a frame
mf_tx_stat_byte_index_i => tx_byte_index,
mf_fd_wdgn_i => fd_wdgn_i, -- FIELDRIVE watchdog
mf_fd_txer_i => fd_txer_i, -- FIELDRIVE txerr
-- rx control/status
mf_rx_rst_o => rx_rst, -- note: this is not a pulse
mf_rx_pream_ok_i => rx_pream_ok, -- have to extend the pulse
mf_rx_frame_ok_i => rx_frame_ok_p, -- have to extend the pulse
mf_rx_frame_err_i => '0',
mf_rx_frame_err_code_i => "000",
mf_rx_bytes_num_i => rx_data_bytes,
-- rx data
mf_rx_data_ctrl_i => rx_ctrl_byte,
mf_rx_data_reg1_i => rx_frame(0),
mf_rx_data_reg2_i => rx_frame(1),
mf_rx_data_reg3_i => rx_frame(2),
mf_rx_data_reg4_i => rx_frame(3),
mf_rx_data_reg5_i => rx_frame(4),
mf_rx_data_reg6_i => rx_frame(5),
mf_rx_data_reg7_i => rx_frame(6),
mf_rx_data_reg8_i => rx_frame(7),
mf_rx_data_reg9_i => rx_frame(8),
mf_rx_data_reg10_i => rx_frame(9),
mf_rx_data_reg11_i => rx_frame(10),
mf_rx_data_reg12_i => rx_frame(11),
mf_rx_data_reg13_i => rx_frame(12),
mf_rx_data_reg14_i => rx_frame(13),
mf_rx_data_reg15_i => rx_frame(14),
mf_rx_data_reg16_i => rx_frame(15),
mf_rx_data_reg17_i => rx_frame(16),
mf_rx_data_reg18_i => rx_frame(17),
mf_rx_data_reg19_i => rx_frame(18),
mf_rx_data_reg20_i => rx_frame(19),
mf_rx_data_reg21_i => rx_frame(20),
mf_rx_data_reg22_i => rx_frame(21),
mf_rx_data_reg23_i => rx_frame(22),
mf_rx_data_reg24_i => rx_frame(23),
mf_rx_data_reg25_i => rx_frame(24),
mf_rx_data_reg26_i => rx_frame(25),
mf_rx_data_reg27_i => rx_frame(26),
mf_rx_data_reg28_i => rx_frame(27),
mf_rx_data_reg29_i => rx_frame(28),
mf_rx_data_reg30_i => rx_frame(29),
mf_rx_data_reg31_i => rx_frame(30),
mf_rx_data_reg32_i => rx_frame(31),
mf_rx_ctrl_rst_o => rx_rst, -- note: this is not a pulse
-- rx status
mf_rx_stat_pream_ok_i => rx_fss_received,
mf_rx_stat_frame_ok_i => rx_frame_ok_p, -- have to extend the pulse
mf_rx_stat_frame_err_i => '0',
mf_rx_stat_frame_err_code_i => "000",
mf_rx_stat_bytes_num_i => rx_data_bytes,
-- rx data
mf_tx_data_ctrl_o => tx_ctrl_byte,
mf_tx_data_reg1_o => tx_frame(0),
mf_tx_data_reg2_o => tx_frame(1),
mf_tx_data_reg3_o => tx_frame(2),
mf_tx_data_reg4_o => tx_frame(3),
mf_tx_data_reg5_o => tx_frame(4),
mf_tx_data_reg6_o => tx_frame(5),
mf_tx_data_reg7_o => tx_frame(6),
mf_tx_data_reg8_o => tx_frame(7),
mf_tx_data_reg9_o => tx_frame(8),
mf_tx_data_reg10_o => tx_frame(9),
mf_tx_data_reg11_o => tx_frame(10),
mf_tx_data_reg12_o => tx_frame(11),
mf_tx_data_reg13_o => tx_frame(12),
mf_tx_data_reg14_o => tx_frame(13),
mf_tx_data_reg15_o => tx_frame(14),
mf_tx_data_reg16_o => tx_frame(15),
mf_tx_data_reg17_o => tx_frame(16),
mf_tx_data_reg18_o => tx_frame(17),
mf_tx_data_reg19_o => tx_frame(18),
mf_tx_data_reg20_o => tx_frame(19),
mf_tx_data_reg21_o => tx_frame(20),
mf_tx_data_reg22_o => tx_frame(21),
mf_tx_data_reg23_o => tx_frame(22),
mf_tx_data_reg24_o => tx_frame(23),
mf_tx_data_reg25_o => tx_frame(24),
mf_tx_data_reg26_o => tx_frame(25),
mf_tx_data_reg27_o => tx_frame(26),
mf_tx_data_reg28_o => tx_frame(27),
mf_tx_data_reg29_o => tx_frame(28),
mf_tx_data_reg30_o => tx_frame(29),
mf_tx_data_reg31_o => tx_frame(30),
mf_tx_data_reg32_o => tx_frame(31));
speed_ok <= '1' when speed_b1_i & speed_b0_i = speed_host else '0';
mf_rx_data_ctrl_i => rx_ctrl_byte,
mf_rx_data_reg1_i => rx_frame(0),
mf_rx_data_reg2_i => rx_frame(1),
mf_rx_data_reg3_i => rx_frame(2),
mf_rx_data_reg4_i => rx_frame(3),
mf_rx_data_reg5_i => rx_frame(4),
mf_rx_data_reg6_i => rx_frame(5),
mf_rx_data_reg7_i => rx_frame(6),
mf_rx_data_reg8_i => rx_frame(7),
mf_rx_data_reg9_i => rx_frame(8),
mf_rx_data_reg10_i => rx_frame(9),
mf_rx_data_reg11_i => rx_frame(10),
mf_rx_data_reg12_i => rx_frame(11),
mf_rx_data_reg13_i => rx_frame(12),
mf_rx_data_reg14_i => rx_frame(13),
mf_rx_data_reg15_i => rx_frame(14),
mf_rx_data_reg16_i => rx_frame(15),
mf_rx_data_reg17_i => rx_frame(16),
mf_rx_data_reg18_i => rx_frame(17),
mf_rx_data_reg19_i => rx_frame(18),
mf_rx_data_reg20_i => rx_frame(19),
mf_rx_data_reg21_i => rx_frame(20),
mf_rx_data_reg22_i => rx_frame(21),
mf_rx_data_reg23_i => rx_frame(22),
mf_rx_data_reg24_i => rx_frame(23),
mf_rx_data_reg25_i => rx_frame(24),
mf_rx_data_reg26_i => rx_frame(25),
mf_rx_data_reg27_i => rx_frame(26),
mf_rx_data_reg28_i => rx_frame(27),
mf_rx_data_reg29_i => rx_frame(28),
mf_rx_data_reg30_i => rx_frame(29),
mf_rx_data_reg31_i => rx_frame(30),
mf_rx_data_reg32_i => rx_frame(31),
mf_rx_data_reg33_i => rx_frame(32),
mf_rx_data_reg34_i => rx_frame(33),
mf_rx_data_reg35_i => rx_frame(34),
mf_rx_data_reg36_i => rx_frame(35),
mf_rx_data_reg37_i => rx_frame(36),
mf_rx_data_reg38_i => rx_frame(37),
mf_rx_data_reg39_i => rx_frame(38),
mf_rx_data_reg40_i => rx_frame(39),
mf_rx_data_reg41_i => rx_frame(40),
mf_rx_data_reg42_i => rx_frame(41),
mf_rx_data_reg43_i => rx_frame(42),
mf_rx_data_reg44_i => rx_frame(43),
mf_rx_data_reg45_i => rx_frame(44),
mf_rx_data_reg46_i => rx_frame(45),
mf_rx_data_reg47_i => rx_frame(46),
mf_rx_data_reg48_i => rx_frame(47),
mf_rx_data_reg49_i => rx_frame(48),
mf_rx_data_reg50_i => rx_frame(49),
mf_rx_data_reg51_i => rx_frame(50),
mf_rx_data_reg52_i => rx_frame(51),
mf_rx_data_reg53_i => rx_frame(52),
mf_rx_data_reg54_i => rx_frame(53),
mf_rx_data_reg55_i => rx_frame(54),
mf_rx_data_reg56_i => rx_frame(55),
mf_rx_data_reg57_i => rx_frame(56),
mf_rx_data_reg58_i => rx_frame(57),
mf_rx_data_reg59_i => rx_frame(58),
mf_rx_data_reg60_i => rx_frame(59),
mf_rx_data_reg61_i => rx_frame(60),
mf_rx_data_reg62_i => rx_frame(61),
mf_rx_data_reg63_i => rx_frame(62),
mf_rx_data_reg64_i => rx_frame(63),
mf_rx_data_reg65_i => rx_frame(64),
mf_rx_data_reg66_i => rx_frame(65),
-- tx data
mf_tx_data_ctrl_o => tx_ctrl_byte,
mf_tx_data_reg1_o => tx_frame(0),
mf_tx_data_reg2_o => tx_frame(1),
mf_tx_data_reg3_o => tx_frame(2),
mf_tx_data_reg4_o => tx_frame(3),
mf_tx_data_reg5_o => tx_frame(4),
mf_tx_data_reg6_o => tx_frame(5),
mf_tx_data_reg7_o => tx_frame(6),
mf_tx_data_reg8_o => tx_frame(7),
mf_tx_data_reg9_o => tx_frame(8),
mf_tx_data_reg10_o => tx_frame(9),
mf_tx_data_reg11_o => tx_frame(10),
mf_tx_data_reg12_o => tx_frame(11),
mf_tx_data_reg13_o => tx_frame(12),
mf_tx_data_reg14_o => tx_frame(13),
mf_tx_data_reg15_o => tx_frame(14),
mf_tx_data_reg16_o => tx_frame(15),
mf_tx_data_reg17_o => tx_frame(16),
mf_tx_data_reg18_o => tx_frame(17),
mf_tx_data_reg19_o => tx_frame(18),
mf_tx_data_reg20_o => tx_frame(19),
mf_tx_data_reg21_o => tx_frame(20),
mf_tx_data_reg22_o => tx_frame(21),
mf_tx_data_reg23_o => tx_frame(22),
mf_tx_data_reg24_o => tx_frame(23),
mf_tx_data_reg25_o => tx_frame(24),
mf_tx_data_reg26_o => tx_frame(25),
mf_tx_data_reg27_o => tx_frame(26),
mf_tx_data_reg28_o => tx_frame(27),
mf_tx_data_reg29_o => tx_frame(28),
mf_tx_data_reg30_o => tx_frame(29),
mf_tx_data_reg31_o => tx_frame(30),
mf_tx_data_reg32_o => tx_frame(31),
mf_tx_data_reg33_o => tx_frame(32),
mf_tx_data_reg34_o => tx_frame(33),
mf_tx_data_reg35_o => tx_frame(34),
mf_tx_data_reg36_o => tx_frame(35),
mf_tx_data_reg37_o => tx_frame(36),
mf_tx_data_reg38_o => tx_frame(37),
mf_tx_data_reg39_o => tx_frame(38),
mf_tx_data_reg40_o => tx_frame(39),
mf_tx_data_reg41_o => tx_frame(40),
mf_tx_data_reg42_o => tx_frame(41),
mf_tx_data_reg43_o => tx_frame(42),
mf_tx_data_reg44_o => tx_frame(43),
mf_tx_data_reg45_o => tx_frame(44),
mf_tx_data_reg46_o => tx_frame(45),
mf_tx_data_reg47_o => tx_frame(46),
mf_tx_data_reg48_o => tx_frame(47),
mf_tx_data_reg49_o => tx_frame(48),
mf_tx_data_reg50_o => tx_frame(49),
mf_tx_data_reg51_o => tx_frame(50),
mf_tx_data_reg52_o => tx_frame(51),
mf_tx_data_reg53_o => tx_frame(52),
mf_tx_data_reg54_o => tx_frame(53),
mf_tx_data_reg55_o => tx_frame(54),
mf_tx_data_reg56_o => tx_frame(55),
mf_tx_data_reg57_o => tx_frame(56),
mf_tx_data_reg58_o => tx_frame(57),
mf_tx_data_reg59_o => tx_frame(58),
mf_tx_data_reg60_o => tx_frame(59),
mf_tx_data_reg61_o => tx_frame(60),
mf_tx_data_reg62_o => tx_frame(61),
mf_tx_data_reg63_o => tx_frame(62),
mf_tx_data_reg64_o => tx_frame(63),
mf_tx_data_reg65_o => tx_frame(64),
mf_tx_data_reg66_o => tx_frame(65));
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
speed_ok <= '1' when speed_b1_i & speed_b0_i = speed_host else '0';
---------------------------------------------------------------------------------------------------
-- resets --
---------------------------------------------------------------------------------------------------
cmp_sw_reset : process(clk_i)
rst_n <= not rst_i;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- reset generation
p_sw_reset : process(clk_i)
begin
if rising_edge(clk_i) then
if(rst_n = '0') then
core_sw_rst_n <= '0';
fd_sw_rst_n <= '0';
core_host_rstn <= '0';
fd_host_rstn <= '0';
else
-- protection against accidental write
if(core_sw_rst_p = '1' and core_sw_rstn_lock = c_RST_UNLOCK_VALUE) then
core_sw_rst_n <= core_sw_rstn_tmp;--(0);
fd_sw_rst_n <= fd_sw_rstn_tmp;--(0);
if(rstn_lock_wr = '1' and rstn_lock = c_RST_UNLOCK_VALUE) then
core_host_rstn <= core_rstn_tmp;
fd_host_rstn <= fd_rstn_tmp;
end if;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- --
core_host_rst <= not core_host_rstn;
fd_rstn_o <= fd_host_rstn;
core_rst <= core_host_rst or rst_i; -- combination of PoR, PCIe reset, reset from WRNC
core_rst_n <= not core_rst;
core_sw_rst <= not core_sw_rst_n;
fd_rstn_o <= fd_sw_rst_n;
core_rst <= core_sw_rst or rst_i;
---------------------------------------------------------------------------------------------------
-- external sync --
---------------------------------------------------------------------------------------------------
cmp_ext_sync_p_detect: gc_sync_ffs
generic map(g_sync_edge => "positive")
port map(
clk_i => clk_i,
rst_n_i => core_rst_n,
data_i => ext_sync_i,
ppulse_o => ext_sync_p);
---------------------------------------------------------------------------------------------------
-- macrocycle counter --
---------------------------------------------------------------------------------------------------
......@@ -327,7 +423,7 @@ speed_ok <= '1' when speed_b1_i & speed_b0_i = speed_host else '0';
port map(
clk_i => clk_i,
rst_i => core_rst,
counter_load_i => macrocyc_cnt_zero_p or macrocyc_sw_load_p,
counter_load_i => macrocyc_cnt_zero_p or macrocyc_sw_load_p or ext_sync_p,
counter_top_i => macrocyc_lgth,
counter_o => macrocyc_cnt,
counter_is_zero_o => macrocyc_cnt_zero_p);
......@@ -336,9 +432,10 @@ speed_ok <= '1' when speed_b1_i & speed_b0_i = speed_host else '0';
generic map(g_sync_edge => "positive")
port map(
clk_i => clk_i,
rst_n_i => rst_n,
rst_n_i => core_rst_n,
data_i => macrocyc_sw_load,
ppulse_o => macrocyc_sw_load_p);
---------------------------------------------------------------------------------------------------
-- tournaround counter --
......@@ -348,16 +445,16 @@ speed_ok <= '1' when speed_b1_i & speed_b0_i = speed_host else '0';
port map(
clk_i => clk_i,
rst_i => core_rst,
counter_load_i => tx_completed_p or turnar_sw_load_p,
counter_load_i => tx_completed_p or rx_frame_ok_p or rx_crc_wrong_p or turnar_sw_load_p,
counter_top_i => turnar_lgth,
counter_o => turnar_cnt,
counter_is_zero_o => turnar_cnt_zero_p);
counter_is_zero_o => open);
turnar_sw_load_p_detect: gc_sync_ffs
generic map(g_sync_edge => "positive")
port map(
clk_i => clk_i,
rst_n_i => rst_n,
rst_n_i => core_rst_n,
data_i => turnar_sw_load,
ppulse_o => turnar_sw_load_p);
......@@ -372,52 +469,53 @@ speed_ok <= '1' when speed_b1_i & speed_b0_i = speed_host else '0';
port map(
clk_i => clk_i,
rst_i => core_rst,
counter_load_i => tx_completed_p or rx_frame_ok_p or silen_sw_load_p,
counter_load_i => tx_completed_p or rx_frame_ok_p or rx_crc_wrong_p or silen_sw_load_p,
counter_top_i => silen_lgth,
counter_o => silen_cnt,
counter_is_zero_o => silen_cnt_zero_p);
counter_is_zero_o => open);
cmp_silen_sw_load_p_detect: gc_sync_ffs
generic map(g_sync_edge => "positive")
port map(
clk_i => clk_i,
rst_n_i => rst_n,
rst_n_i => core_rst_n,
data_i => silen_sw_load,
ppulse_o => silen_sw_load_p);
--------------------------------------------------------------------------------------------------
-- signals for tx --
--------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------
-- edge detection on the tx_start signal
cmp_tx_start_p_detect: gc_sync_ffs
generic map(g_sync_edge => "positive")
port map(
clk_i => clk_i,
rst_n_i => rst_n,
rst_n_i => core_rst_n,
data_i => tx_start,
ppulse_o => tx_start_p);
--------------------------------------------------------------------------------------------------
-- signals for rx --
--------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------
-- extension of the rx_fss_received_p so as to ensure capturing by the wrnc
cmp_rx_extend_p : gc_extend_pulse
generic map (
g_width => 16)
port map (
clk_i => clk_i,
rst_n_i => rst_n,
rst_n_i => core_rst_n,
pulse_i => rx_fss_received_p,
extended_o => rx_pream_ok);
extended_o => rx_fss_received);
-- rx_rst_pulse_detect: gc_sync_ffs
-- generic map(g_sync_edge => "positive");
-- port map(
-- clk_i => clk_i,
-- rst_n_i => rst_n_i,
-- data_i => rx_rst,
-- ppulse_o => rx_rst_p);
rx_rst_pulse_detect: gc_sync_ffs
generic map(g_sync_edge => "positive")
port map(
clk_i => clk_i,
rst_n_i => rst_n,
data_i => rx_rst,
ppulse_o => rx_rst_p);
---------------------------------------------------------------------------------------------------
......@@ -425,13 +523,14 @@ speed_ok <= '1' when speed_b1_i & speed_b0_i = speed_host else '0';
---------------------------------------------------------------------------------------------------
cmp_masterfip_rx: masterfip_rx
port map(
uclk_i => clk_i,
core_rst_i => core_rst,
rate_i => "01",
clk_40m_i => clk_i,
rst_i => core_rst,
speed_i => "01",
fd_rxd_a_i => fd_rxd_i,
rx_rst_i => rx_rst or fd_txena,
rx_rst_i => rx_rst_p or fd_txena, -- reset from the WRNC or reset while transmitting
-------------------------------------------------------------
rx_byte_index_o => rx_byte_index, -- should have the amount of bytes
rx_byte_index_o => rx_byte_index, -- current amount of bytes (counting starts after the fss;
-- includes ctrl, data, crc, fes fields)
rx_ctrl_byte_o => rx_ctrl_byte,
rx_frame_o => rx_frame,
rx_byte_o => rx_byte,
......@@ -441,35 +540,34 @@ speed_ok <= '1' when speed_b1_i & speed_b0_i = speed_host else '0';
rx_crc_wrong_p_o => rx_crc_wrong_p);
-------------------------------------------------------------
rx_data_bytes <= '0' & (std_logic_vector(unsigned(rx_byte_index)-4));
-- actual size of data bytes (without preamble, postamble, ctrl, CRC); check with an RP_FIN if ok!
-- number of bytes to read from the rx_frame regs
-- size of data bytes (without fss, fes, ctrl, crc); check with an RP_FIN if ok!
rx_data_bytes <= (std_logic_vector(unsigned(rx_byte_index)-4));
---------------------------------------------------------------------------------------------------
-- tx --
---------------------------------------------------------------------------------------------------
cmp_masterfip_tx: masterfip_tx
port map(
uclk_i => clk_i,
core_rst_i => (core_rst or tx_rst),
rate_i => "01",
tx_bytes_num_i => tx_bytes_num(7 downto 0),
tx_start_p_i => tx_start_p,
tx_frame_i => tx_frame,
tx_ctrl_byte_i => tx_ctrl_byte,
clk_40m_i => clk_i,
rst_i => (core_rst or tx_rst),
speed_i => "01",
tx_bytes_num_i => tx_bytes_num,
tx_start_p_i => tx_start_p,
tx_frame_i => tx_frame,
tx_ctrl_byte_i => tx_ctrl_byte,
-------------------------------------------------------------
tx_byte_index_o => tx_byte_index,
tx_completed_p_o => tx_completed_p,
tx_data_o => fd_txd_o,
tx_enable_o => fd_txena,
tx_clk_o => fd_txck_o);
tx_byte_index_o => tx_byte_index,
tx_end_p_o => tx_completed_p,
tx_data_o => fd_txd_o,
tx_enable_o => fd_txena,
tx_clk_o => fd_txck_o);
-------------------------------------------------------------
fd_txena_o <= fd_txena;
---------------------------------------------------------------------------------------------------
-- irqs --
---------------------------------------------------------------------------------------------------
irq_p_o <= '0' & rx_crc_wrong_p & rx_frame_ok_p & rx_fss_received_p & tx_completed_p & turnar_cnt_zero_p & silen_cnt_zero_p & macrocyc_cnt_zero_p;
fd_txena_o <= fd_txena;
---------------------------------------------------------------------------------------------------
-- aux --
......
rtl/fmc_masterFIP_mezz.vhd deleted 100644 → 0
View file @ df522070
--_________________________________________________________________________________________________
-- |
-- |TDC core| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- |
-- fmc_masterFIP_mezz |
-- |
---------------------------------------------------------------------------------------------------
-- File fmc_masterFIP_mezz.vhd |
-- |
-- Description The unit combines |
-- o the masterFIP core |
-- o the I2C core for the communication with the TDC board EEPROM |
-- o the OneWire core for the communication with the TDC board UniqueID&Thermeter |
-- o the Embedded Interrupt Controller core that concentrates several interrupt |
-- sources into one WISHBONE interrupt request line. |
-- |
-- For the interconnection between the GN4124/VME core and the different cores (TDC, |
-- I2C, 1W, EIC, timestamps memory) the unit instantiates an SDB crossbar. |
-- |
-- Note that the TDC core uses word addressing, whereas the GN4124/VME cores use byte|
-- addressing |
-- _______________________________ |
-- | FMC TDC mezzanine | |
-- | | |
-- | | ________________ ___ | |
-- | |->| | | | | |
-- ACAM chip <--> | | masterFIP core | | | | <--> |
-- | |--|________________| | S | | |
-- | | ________________ | | | |
-- | | | | | | | |
-- EEPROM chip <--> | | | I2C core | | | | <--> |
-- | | |________________| | | | |
-- | | ________________ | D | | GN4124/VME core |
-- | | | | | | | |
-- 1W chip <--> | | | 1W core | | | | <--> |
-- | | |________________| | | | |
-- | | ________________ | | | |
-- | | | | | B | | |
-- | |->| EIC | | | | <--> |
-- | |________________| |___| | |
-- | | |
-- |________________________________| |
-- ^ ^ |
-- | 40 MHz rst | |
-- |
-- Figure 1: FMC masterFIP mezzanine architecture and |
-- connection with the clks_rsts_manager unit |
-- |
-- |
-- |
-- Authors Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 07/2014 |
-- Version v2 |
-- Depends on |
-- |
---------------- |
-- Last changes |
-- 07/2014 v1 EG First version |
-- |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
--=================================================================================================
-- Libraries & Packages
--=================================================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.masterFIP_pkg.all;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
--=================================================================================================
-- Entity declaration for fmc_masterFIP_mezz
--=================================================================================================
entity fmc_masterFIP_mezz is
generic
(g_with_wrabbit_core : boolean := FALSE;
g_span : integer := 32;
g_width : integer := 32;
values_for_simul : boolean := FALSE);
port
-- TDC core
(-- Clock & reset 40MHz
clk_sys_i : in std_logic; -- 40 MHz clock
rst_sys_n_i : in std_logic; -- reset for 40 MHz logic
-- Bus Speed
speed_b0_i : in std_logic;
speed_b1_i : in std_logic;
-- FielDrive
fd_rxcdn_i : in std_logic;
fd_rxd_i : in std_logic;
fd_txer_i : in std_logic;
fd_wdgn_i : in std_logic;
fd_rstn_o : out std_logic;
fd_txck_o : out std_logic;
fd_txd_o : out std_logic;
fd_txena_o : out std_logic;
-- WISHBONE interface with the GN4124/VME_core
-- for the core configuration | data retrieval | core interrupts | 1Wire | I2C
wb_adr_i : in std_logic_vector(31 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_dat_o : out std_logic_vector(31 downto 0);
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
wb_irq_o : out std_logic;
-- Aux
aux_o : out std_logic_vector(7 downto 0));
end fmc_masterFIP_mezz;
--=================================================================================================
-- architecture declaration
--=================================================================================================
architecture rtl of fmc_masterFIP_mezz is
---------------------------------------------------------------------------------------------------
-- SDB CONSTANTS --
---------------------------------------------------------------------------------------------------
-- Note: All address in sdb and crossbar are BYTE addresses!
-- Master ports on the wishbone crossbar
constant c_NUM_WB_MASTERS : integer := 2;
constant c_WB_SLAVE_CSR : integer := 0; -- core configuration and data registers
constant c_WB_SLAVE_EIC : integer := 1; -- interrupts
-- Slave port on the wishbone crossbar
constant c_NUM_WB_SLAVES : integer := 1;
-- Wishbone master(s)
constant c_WB_MASTER : integer := 0;
-- sdb header address
constant c_SDB_ADDRESS : t_wishbone_address := x"00000000";
-- WISHBONE crossbar layout
constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(1 downto 0) :=
(0 => f_sdb_embed_device(c_MASTERFIP_CSR_SDB_DEVICE, x"00010000"),
1 => f_sdb_embed_device(c_MASTERFIP_EIC_SDB_DEVICE, x"00011000"));
---------------------------------------------------------------------------------------------------
-- Signals --
---------------------------------------------------------------------------------------------------
-- resets
signal general_rst_n, rst_ref_0_n: std_logic;
-- Wishbone buse(s) from crossbar master port(s)
signal cnx_master_out : t_wishbone_master_out_array(c_NUM_WB_MASTERS-1 downto 0);
signal cnx_master_in : t_wishbone_master_in_array (c_NUM_WB_MASTERS-1 downto 0);
-- Wishbone buse(s) to crossbar slave port(s)
signal cnx_slave_out : t_wishbone_slave_out_array(c_NUM_WB_SLAVES-1 downto 0);
signal cnx_slave_in : t_wishbone_slave_in_array (c_NUM_WB_SLAVES-1 downto 0);
-- Wishbone bus from additional registers
signal xreg_slave_out : t_wishbone_slave_out;
signal xreg_slave_in : t_wishbone_slave_in;
-- WISHBONE addresses
signal wb_adr : std_logic_vector(31 downto 0);
signal tdc_mem_wb_adr : std_logic_vector(31 downto 0);
-- 1-wire
signal mezz_owr_en, mezz_owr_i : std_logic_vector(0 downto 0);
-- I2C
signal sys_scl_in, sys_scl_out : std_logic;
signal sys_scl_oe_n, sys_sda_in : std_logic;
signal sys_sda_out, sys_sda_oe_n : std_logic;
-- IRQ
signal irq_p : std_logic_vector(7 downto 0);
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
---------------------------------------------------------------------------------------------------
-- CSR WISHBONE CROSSBAR --
---------------------------------------------------------------------------------------------------
-- CSR wishbone address decoder
-- 0x10000 -> mezzanine board 1-Wire -not used
-- 0x11000 -> masterFIP core configuration and data
-- 0x12000 -> EIC
-- 0x13000 -> mezzanine board EEPROM I2C -not used
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
sdb_crossbar : xwb_sdb_crossbar
generic map
(g_num_masters => c_NUM_WB_SLAVES,
g_num_slaves => c_NUM_WB_MASTERS,
g_registered => true,
g_wraparound => true,
g_layout => c_INTERCONNECT_LAYOUT,
g_sdb_addr => c_SDB_ADDRESS)
port map
(clk_sys_i => clk_sys_i,
rst_n_i => rst_sys_n_i,
slave_i => cnx_slave_in,
slave_o => cnx_slave_out,
master_i => cnx_master_in,
master_o => cnx_master_out);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Unused wishbone signals
wb_dat_o <= cnx_slave_out(c_WB_MASTER).dat;
wb_ack_o <= cnx_slave_out(c_WB_MASTER).ack;
wb_stall_o <= cnx_slave_out(c_WB_MASTER).stall;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Connect crossbar slave port to entity port
cnx_slave_in(c_WB_MASTER).adr <= wb_adr_i;
cnx_slave_in(c_WB_MASTER).dat <= wb_dat_i;
cnx_slave_in(c_WB_MASTER).sel <= wb_sel_i;
cnx_slave_in(c_WB_MASTER).stb <= wb_stb_i;
cnx_slave_in(c_WB_MASTER).we <= wb_we_i;
cnx_slave_in(c_WB_MASTER).cyc <= wb_cyc_i;
---------------------------------------------------------------------------------------------------
-- masterFIP CORE --
---------------------------------------------------------------------------------------------------
masterfip_core: fmc_masterFIP_core
generic map
(g_span => g_span,
g_width => g_width,
values_for_simul => FALSE)
port map
(-- clks, rst
clk_i => clk_sys_i,
rst_i => not (rst_sys_n_i),
-- Bus Speed
speed_b0_i => speed_b0_i,
speed_b1_i => speed_b1_i,
-- FielDrive
fd_rxcdn_i => fd_rxcdn_i,
fd_rxd_i => fd_rxd_i,
fd_txer_i => fd_txer_i,
fd_wdgn_i => fd_wdgn_i,
fd_rstn_o => fd_rstn_o,
fd_txck_o => fd_txck_o,
fd_txd_o => fd_txd_o,
fd_txena_o => fd_txena_o,
-- Interrupts
irq_p_o => irq_p,
-- WISHBONE CSR for core configuration
wb_adr_i => wb_adr,
wb_dat_i => cnx_master_out(c_WB_SLAVE_CSR).dat,
wb_stb_i => cnx_master_out(c_WB_SLAVE_CSR).stb,
wb_sel_i => cnx_master_out(c_WB_SLAVE_CSR).sel,
wb_we_i => cnx_master_out(c_WB_SLAVE_CSR).we,
wb_cyc_i => cnx_master_out(c_WB_SLAVE_CSR).cyc,
wb_stall_o => cnx_master_in(c_WB_SLAVE_CSR).stall,
wb_dat_o => cnx_master_in(c_WB_SLAVE_CSR).dat,
wb_ack_o => cnx_master_in(c_WB_SLAVE_CSR).ack,
-- Aux
aux_o => aux_o);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Convert byte address into word address
wb_adr <= "00" & cnx_master_out(c_WB_SLAVE_CSR).adr(31 downto 2);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Unused wishbone signals
cnx_master_in(c_WB_SLAVE_CSR).err <= '0';
cnx_master_in(c_WB_SLAVE_CSR).rty <= '0';
cnx_master_in(c_WB_SLAVE_CSR).int <= '0';
---------------------------------------------------------------------------------------------------
-- WBGEN2 EMBEDDED INTERRUPTS CONTROLLER --
---------------------------------------------------------------------------------------------------
eic : fmc_masterfip_eic
port map
(clk_sys_i => clk_sys_i,
rst_n_i => rst_sys_n_i,
wb_adr_i => cnx_master_out(c_WB_SLAVE_EIC).adr(3 downto 2),
wb_dat_i => cnx_master_out(c_WB_SLAVE_EIC).dat,
wb_dat_o => cnx_master_in(c_WB_SLAVE_EIC).dat,
wb_cyc_i => cnx_master_out(c_WB_SLAVE_EIC).cyc,
wb_sel_i => cnx_master_out(c_WB_SLAVE_EIC).sel,
wb_stb_i => cnx_master_out(c_WB_SLAVE_EIC).stb,
wb_we_i => cnx_master_out(c_WB_SLAVE_EIC).we,
wb_ack_o => cnx_master_in(c_WB_SLAVE_EIC).ack,
wb_stall_o => cnx_master_in(c_WB_SLAVE_EIC).stall,
wb_int_o => wb_irq_o,
irq_macrocy_start_i => irq_p(0),
irq_silen_time_expire_i => irq_p(1),
irq_turnar_time_expire_i => irq_p(2),
irq_tx_completed_i => irq_p(3),
irq_rx_fss_ok_i => irq_p(4),
irq_rx_frame_ok_i => irq_p(5),
irq_rx_crc_wrong_i => irq_p(6));
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Unused wishbone signals
cnx_master_in(c_WB_SLAVE_EIC).err <= '0';
cnx_master_in(c_WB_SLAVE_EIC).rty <= '0';
cnx_master_in(c_WB_SLAVE_EIC).int <= '0';
end rtl;
----------------------------------------------------------------------------------------------------
-- architecture ends
----------------------------------------------------------------------------------------------------
\ No newline at end of file
rtl/fmc_masterfip_csr.vhd
View file @ eaf3913c
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : fmc_masterfip_csr.vhd
-- Author : auto-generated by wbgen2 from fmc_masterfip_csr.wb
-- Created : 07/23/15 17:04:12
-- Created : 10/07/15 16:39:58
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_masterfip_csr.wb
......@@ -18,7 +18,7 @@ entity fmc_masterfip_csr is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(6 downto 0);
wb_adr_i : in std_logic_vector(7 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
......@@ -27,23 +27,31 @@ entity fmc_masterfip_csr is
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- Port for BIT field: 'reset of the masterFIP core' in reg: 'rst'
mf_rst_core_o : out std_logic;
-- Port for BIT field: 'reset of the fieldrive chip (FD_RSTN)' in reg: 'rst'
mf_rst_fd_o : out std_logic;
-- Ports for PASS_THROUGH field: 'reset magic value' in reg: 'rst'
mf_rst_lock_o : out std_logic_vector(15 downto 0);
mf_rst_lock_wr_o : out std_logic;
-- Port for std_logic_vector field: 'speed' in reg: 'config from host'
mf_config_host_speed_o : out std_logic_vector(1 downto 0);
-- Port for BIT field: 'termination enable on the external synch input' in reg: 'config from host'
mf_config_host_ext_sync_term_en_n_o : out std_logic;
-- Port for std_logic_vector field: 'station address' in reg: 'config from host'
mf_config_host_subs_o : out std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'speed' in reg: 'config from fmc'
mf_config_fmc_speed_i : in std_logic_vector(1 downto 0);
-- Port for BIT field: 'speed match' in reg: 'config from fmc'
mf_config_fmc_speed_ok_i : in std_logic;
-- Port for BIT field: 'reset of the masterFIP core' in reg: 'rstn'
mf_rstn_core_o : out std_logic;
-- Port for BIT field: 'reset of the fieldrive chip (FD_RSTN)' in reg: 'rstn'
mf_rstn_fd_o : out std_logic;
-- Ports for PASS_THROUGH field: 'reset magic value' in reg: 'rstn'
mf_rstn_lock_o : out std_logic_vector(15 downto 0);
mf_rstn_lock_wr_o : out std_logic;
-- Port for BIT field: '1v8_shdn_n' in reg: 'adc power supplies'
mf_adc_1v8_shdn_n_o : out std_logic;
-- Port for BIT field: 'm5v_shdn_n' in reg: 'adc power supplies'
mf_adc_m5v_shdn_n_o : out std_logic;
-- Port for BIT field: '5v_en_n' in reg: 'adc power supplies'
mf_adc_5v_en_n_o : out std_logic;
-- Port for BIT field: 'termination enable' in reg: 'ext sync'
mf_ext_sync_term_en_o : out std_logic;
-- Port for BIT field: 'tranceiver direction' in reg: 'ext sync'
mf_ext_sync_dir_o : out std_logic;
-- Port for BIT field: 'tranceiver output enable' in reg: 'ext sync'
mf_ext_sync_oe_o : out std_logic;
-- Port for BIT field: 'test pulse' in reg: 'ext sync'
mf_ext_sync_tst_n_o : out std_logic;
-- Port for BIT field: '150ohms terination of the bus' in reg: '150ohms bus termination'
mf_bus_term_en_n_o : out std_logic;
-- Port for std_logic_vector field: 'speed' in reg: 'speed'
mf_speed_i : in std_logic_vector(1 downto 0);
-- Port for std_logic_vector field: 'macrocycle lgth' in reg: 'macrocycle lgth'
mf_macrocyc_lgth_o : out std_logic_vector(30 downto 0);
-- Port for BIT field: 'macrocycle cnt start' in reg: 'macrocycle lgth'
......@@ -65,30 +73,32 @@ entity fmc_masterfip_csr is
-- Port for std_logic_vector field: 'ext_sync_tstamp' in reg: 'ext sync tstamp'
mf_ext_sync_tstamp_i : in std_logic_vector(31 downto 0);
-- Port for BIT field: 'tx rst' in reg: 'tx ctrl'
mf_tx_rst_o : out std_logic;
mf_tx_ctrl_rst_o : out std_logic;
-- Port for BIT field: 'tx strt' in reg: 'tx ctrl'
mf_tx_start_o : out std_logic;
mf_tx_ctrl_start_o : out std_logic;
-- Port for std_logic_vector field: 'tx number of bytes' in reg: 'tx ctrl'
mf_tx_bytes_num_o : out std_logic_vector(8 downto 0);
-- Port for BIT field: 'tx stopped' in reg: 'tx status'
mf_tx_stop_i : in std_logic;
mf_tx_ctrl_bytes_num_o : out std_logic_vector(8 downto 0);
-- Port for BIT field: 'tx ended' in reg: 'tx status'
mf_tx_stat_stop_i : in std_logic;
-- Port for std_logic_vector field: 'tx current byte' in reg: 'tx status'
mf_tx_stat_byte_index_i : in std_logic_vector(8 downto 0);
-- Port for BIT field: 'fd watchdog' in reg: 'fieldrive status'
mf_fd_wdgn_i : in std_logic;
-- Port for BIT field: 'fd transmitter error' in reg: 'fieldrive status'
mf_fd_txer_i : in std_logic;
-- Port for BIT field: 'rx rst' in reg: 'rx ctrl'
mf_rx_rst_o : out std_logic;
mf_rx_ctrl_rst_o : out std_logic;
-- Port for BIT field: 'rx preamble detected' in reg: 'rx status'
mf_rx_pream_ok_i : in std_logic;
mf_rx_stat_pream_ok_i : in std_logic;
-- Port for BIT field: 'rx frame ok' in reg: 'rx status'
mf_rx_frame_ok_i : in std_logic;
mf_rx_stat_frame_ok_i : in std_logic;
-- Port for BIT field: 'rx frame error' in reg: 'rx status'
mf_rx_frame_err_i : in std_logic;
mf_rx_stat_frame_err_i : in std_logic;
-- Port for std_logic_vector field: 'rx frame error code' in reg: 'rx status'
mf_rx_frame_err_code_i : in std_logic_vector(2 downto 0);
mf_rx_stat_frame_err_code_i : in std_logic_vector(2 downto 0);
-- Port for std_logic_vector field: 'rx number of data bytes' in reg: 'rx status'
mf_rx_bytes_num_i : in std_logic_vector(8 downto 0);
-- Port for std_logic_vector field: 'rx ctrl byte' in reg: 'rx ctrl byte'
mf_rx_stat_bytes_num_i : in std_logic_vector(8 downto 0);
-- Port for std_logic_vector field: 'rx data ctrl byte' in reg: 'rx data ctrl byte'
mf_rx_data_ctrl_i : in std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'reg 1' in reg: 'rx data reg1'
mf_rx_data_reg1_i : in std_logic_vector(31 downto 0);
......@@ -154,6 +164,74 @@ entity fmc_masterfip_csr is
mf_rx_data_reg31_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg32' in reg: 'rx data reg32'
mf_rx_data_reg32_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg 33' in reg: 'rx data reg33'
mf_rx_data_reg33_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg34' in reg: 'rx data reg34'
mf_rx_data_reg34_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg35' in reg: 'rx data reg35'
mf_rx_data_reg35_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg36' in reg: 'rx data reg36'
mf_rx_data_reg36_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg37' in reg: 'rx data reg37'
mf_rx_data_reg37_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg38' in reg: 'rx data reg38'
mf_rx_data_reg38_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg39' in reg: 'rx data reg39'
mf_rx_data_reg39_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg40' in reg: 'rx data reg40'
mf_rx_data_reg40_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg41' in reg: 'rx data reg41'
mf_rx_data_reg41_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg42' in reg: 'rx data reg42'
mf_rx_data_reg42_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg43' in reg: 'rx data reg43'
mf_rx_data_reg43_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg44' in reg: 'rx data reg44'
mf_rx_data_reg44_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg45' in reg: 'rx data reg45'
mf_rx_data_reg45_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg46' in reg: 'rx data reg46'
mf_rx_data_reg46_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg47' in reg: 'rx data reg47'
mf_rx_data_reg47_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg48' in reg: 'rx data reg48'
mf_rx_data_reg48_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg49' in reg: 'rx data reg49'
mf_rx_data_reg49_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg50' in reg: 'rx data reg50'
mf_rx_data_reg50_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg51' in reg: 'rx data reg51'
mf_rx_data_reg51_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg52' in reg: 'rx data reg52'
mf_rx_data_reg52_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg53' in reg: 'rx data reg53'
mf_rx_data_reg53_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg54' in reg: 'rx data reg54'
mf_rx_data_reg54_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg55' in reg: 'rx data reg55'
mf_rx_data_reg55_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg56' in reg: 'rx data reg56'
mf_rx_data_reg56_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg57' in reg: 'rx data reg57'
mf_rx_data_reg57_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg58' in reg: 'rx data reg58'
mf_rx_data_reg58_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg59' in reg: 'rx data reg59'
mf_rx_data_reg59_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg60' in reg: 'rx data reg60'
mf_rx_data_reg60_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg61' in reg: 'rx data reg61'
mf_rx_data_reg61_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg62' in reg: 'rx data reg62'
mf_rx_data_reg62_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg63' in reg: 'rx data reg63'
mf_rx_data_reg63_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg64' in reg: 'rx data reg64'
mf_rx_data_reg64_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg65' in reg: 'rx data reg65'
mf_rx_data_reg65_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg66' in reg: 'rx data reg66'
mf_rx_data_reg66_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'tx ctrl byte' in reg: 'tx ctrl byte'
mf_tx_data_ctrl_o : out std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'reg1' in reg: 'tx data reg1'
......@@ -219,27 +297,100 @@ entity fmc_masterfip_csr is
-- Port for std_logic_vector field: 'reg31' in reg: 'tx data reg31'
mf_tx_data_reg31_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg32' in reg: 'tx data reg32'
mf_tx_data_reg32_o : out std_logic_vector(31 downto 0)
mf_tx_data_reg32_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg 33' in reg: 'tx data reg33'
mf_tx_data_reg33_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg34' in reg: 'tx data reg34'
mf_tx_data_reg34_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg35' in reg: 'tx data reg35'
mf_tx_data_reg35_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg36' in reg: 'tx data reg36'
mf_tx_data_reg36_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg37' in reg: 'tx data reg37'
mf_tx_data_reg37_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg38' in reg: 'tx data reg38'
mf_tx_data_reg38_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg39' in reg: 'tx data reg39'
mf_tx_data_reg39_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg40' in reg: 'tx data reg40'
mf_tx_data_reg40_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg41' in reg: 'tx data reg41'
mf_tx_data_reg41_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg42' in reg: 'tx data reg42'
mf_tx_data_reg42_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg43' in reg: 'tx data reg43'
mf_tx_data_reg43_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg44' in reg: 'tx data reg44'
mf_tx_data_reg44_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg45' in reg: 'tx data reg45'
mf_tx_data_reg45_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg46' in reg: 'tx data reg46'
mf_tx_data_reg46_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg47' in reg: 'tx data reg47'
mf_tx_data_reg47_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg48' in reg: 'tx data reg48'
mf_tx_data_reg48_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg49' in reg: 'tx data reg49'
mf_tx_data_reg49_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg50' in reg: 'tx data reg50'
mf_tx_data_reg50_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg51' in reg: 'tx data reg51'
mf_tx_data_reg51_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg52' in reg: 'tx data reg52'
mf_tx_data_reg52_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg53' in reg: 'tx data reg53'
mf_tx_data_reg53_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg54' in reg: 'tx data reg54'
mf_tx_data_reg54_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg55' in reg: 'tx data reg55'
mf_tx_data_reg55_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg56' in reg: 'tx data reg56'
mf_tx_data_reg56_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg57' in reg: 'tx data reg57'
mf_tx_data_reg57_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg58' in reg: 'tx data reg58'
mf_tx_data_reg58_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg59' in reg: 'tx data reg59'
mf_tx_data_reg59_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg60' in reg: 'tx data reg60'
mf_tx_data_reg60_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg61' in reg: 'tx data reg61'
mf_tx_data_reg61_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg62' in reg: 'tx data reg62'
mf_tx_data_reg62_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg63' in reg: 'tx data reg63'
mf_tx_data_reg63_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg64' in reg: 'tx data reg64'
mf_tx_data_reg64_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg65' in reg: 'tx data reg65'
mf_tx_data_reg65_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg66' in reg: 'tx data reg66'
mf_tx_data_reg66_o : out std_logic_vector(31 downto 0)
);
end fmc_masterfip_csr;
architecture syn of fmc_masterfip_csr is
signal mf_rst_core_int : std_logic ;
signal mf_rst_fd_int : std_logic ;
signal mf_config_host_speed_int : std_logic_vector(1 downto 0);
signal mf_config_host_ext_sync_term_en_n_int : std_logic ;
signal mf_config_host_subs_int : std_logic_vector(7 downto 0);
signal mf_rstn_core_int : std_logic ;
signal mf_rstn_fd_int : std_logic ;
signal mf_adc_1v8_shdn_n_int : std_logic ;
signal mf_adc_m5v_shdn_n_int : std_logic ;
signal mf_adc_5v_en_n_int : std_logic ;
signal mf_ext_sync_term_en_int : std_logic ;
signal mf_ext_sync_dir_int : std_logic ;
signal mf_ext_sync_oe_int : std_logic ;
signal mf_ext_sync_tst_n_int : std_logic ;
signal mf_bus_term_en_n_int : std_logic ;
signal mf_macrocyc_lgth_int : std_logic_vector(30 downto 0);
signal mf_macrocyc_start_int : std_logic ;
signal mf_turnar_lgth_int : std_logic_vector(30 downto 0);
signal mf_turnar_start_int : std_logic ;
signal mf_silen_lgth_int : std_logic_vector(30 downto 0);
signal mf_silen_start_int : std_logic ;
signal mf_tx_rst_int : std_logic ;
signal mf_tx_start_int : std_logic ;
signal mf_tx_bytes_num_int : std_logic_vector(8 downto 0);
signal mf_rx_rst_int : std_logic ;
signal mf_tx_ctrl_rst_int : std_logic ;
signal mf_tx_ctrl_start_int : std_logic ;
signal mf_tx_ctrl_bytes_num_int : std_logic_vector(8 downto 0);
signal mf_rx_ctrl_rst_int : std_logic ;
signal mf_tx_data_ctrl_int : std_logic_vector(7 downto 0);
signal mf_tx_data_reg1_int : std_logic_vector(31 downto 0);
signal mf_tx_data_reg2_int : std_logic_vector(31 downto 0);
......@@ -273,11 +424,45 @@ signal mf_tx_data_reg29_int : std_logic_vector(31 downto 0);
signal mf_tx_data_reg30_int : std_logic_vector(31 downto 0);
signal mf_tx_data_reg31_int : std_logic_vector(31 downto 0);
signal mf_tx_data_reg32_int : std_logic_vector(31 downto 0);
signal mf_tx_data_reg33_int : std_logic_vector(31 downto 0);
signal mf_tx_data_reg34_int : std_logic_vector(31 downto 0);
signal mf_tx_data_reg35_int : std_logic_vector(31 downto 0);
signal mf_tx_data_reg36_int : std_logic_vector(31 downto 0);
signal mf_tx_data_reg37_int : std_logic_vector(31 downto 0);
signal mf_tx_data_reg38_int : std_logic_vector(31 downto 0);
signal mf_tx_data_reg39_int : std_logic_vector(31 downto 0);
signal mf_tx_data_reg40_int : std_logic_vector(31 downto 0);
signal mf_tx_data_reg41_int : std_logic_vector(31 downto 0);
signal mf_tx_data_reg42_int : std_logic_vector(31 downto 0);
signal mf_tx_data_reg43_int : std_logic_vector(31 downto 0);
signal mf_tx_data_reg44_int : std_logic_vector(31 downto 0);
signal mf_tx_data_reg45_int : std_logic_vector(31 downto 0);
signal mf_tx_data_reg46_int : std_logic_vector(31 downto 0);
signal mf_tx_data_reg47_int : std_logic_vector(31 downto 0);
signal mf_tx_data_reg48_int : std_logic_vector(31 downto 0);
signal mf_tx_data_reg49_int : std_logic_vector(31 downto 0);
signal mf_tx_data_reg50_int : std_logic_vector(31 downto 0);
signal mf_tx_data_reg51_int : std_logic_vector(31 downto 0);
signal mf_tx_data_reg52_int : std_logic_vector(31 downto 0);
signal mf_tx_data_reg53_int : std_logic_vector(31 downto 0);
signal mf_tx_data_reg54_int : std_logic_vector(31 downto 0);
signal mf_tx_data_reg55_int : std_logic_vector(31 downto 0);
signal mf_tx_data_reg56_int : std_logic_vector(31 downto 0);
signal mf_tx_data_reg57_int : std_logic_vector(31 downto 0);
signal mf_tx_data_reg58_int : std_logic_vector(31 downto 0);
signal mf_tx_data_reg59_int : std_logic_vector(31 downto 0);
signal mf_tx_data_reg60_int : std_logic_vector(31 downto 0);
signal mf_tx_data_reg61_int : std_logic_vector(31 downto 0);
signal mf_tx_data_reg62_int : std_logic_vector(31 downto 0);
signal mf_tx_data_reg63_int : std_logic_vector(31 downto 0);
signal mf_tx_data_reg64_int : std_logic_vector(31 downto 0);
signal mf_tx_data_reg65_int : std_logic_vector(31 downto 0);
signal mf_tx_data_reg66_int : std_logic_vector(31 downto 0);
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(6 downto 0);
signal rwaddr_reg : std_logic_vector(7 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
......@@ -300,22 +485,27 @@ begin
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
mf_rst_core_int <= '0';
mf_rst_fd_int <= '0';
mf_rst_lock_wr_o <= '0';
mf_config_host_speed_int <= "00";
mf_config_host_ext_sync_term_en_n_int <= '0';
mf_config_host_subs_int <= "00000000";
mf_rstn_core_int <= '0';
mf_rstn_fd_int <= '0';
mf_rstn_lock_wr_o <= '0';
mf_adc_1v8_shdn_n_int <= '0';
mf_adc_m5v_shdn_n_int <= '0';
mf_adc_5v_en_n_int <= '0';
mf_ext_sync_term_en_int <= '0';
mf_ext_sync_dir_int <= '0';
mf_ext_sync_oe_int <= '0';
mf_ext_sync_tst_n_int <= '0';
mf_bus_term_en_n_int <= '0';
mf_macrocyc_lgth_int <= "0000000000000000000000000000000";
mf_macrocyc_start_int <= '0';
mf_turnar_lgth_int <= "0000000000000000000000000000000";
mf_turnar_start_int <= '0';
mf_silen_lgth_int <= "0000000000000000000000000000000";
mf_silen_start_int <= '0';
mf_tx_rst_int <= '0';
mf_tx_start_int <= '0';
mf_tx_bytes_num_int <= "000000000";
mf_rx_rst_int <= '0';
mf_tx_ctrl_rst_int <= '0';
mf_tx_ctrl_start_int <= '0';
mf_tx_ctrl_bytes_num_int <= "000000000";
mf_rx_ctrl_rst_int <= '0';
mf_tx_data_ctrl_int <= "00000000";
mf_tx_data_reg1_int <= "00000000000000000000000000000000";
mf_tx_data_reg2_int <= "00000000000000000000000000000000";
......@@ -349,28 +539,62 @@ begin
mf_tx_data_reg30_int <= "00000000000000000000000000000000";
mf_tx_data_reg31_int <= "00000000000000000000000000000000";
mf_tx_data_reg32_int <= "00000000000000000000000000000000";
mf_tx_data_reg33_int <= "00000000000000000000000000000000";
mf_tx_data_reg34_int <= "00000000000000000000000000000000";
mf_tx_data_reg35_int <= "00000000000000000000000000000000";
mf_tx_data_reg36_int <= "00000000000000000000000000000000";
mf_tx_data_reg37_int <= "00000000000000000000000000000000";
mf_tx_data_reg38_int <= "00000000000000000000000000000000";
mf_tx_data_reg39_int <= "00000000000000000000000000000000";
mf_tx_data_reg40_int <= "00000000000000000000000000000000";
mf_tx_data_reg41_int <= "00000000000000000000000000000000";
mf_tx_data_reg42_int <= "00000000000000000000000000000000";
mf_tx_data_reg43_int <= "00000000000000000000000000000000";
mf_tx_data_reg44_int <= "00000000000000000000000000000000";
mf_tx_data_reg45_int <= "00000000000000000000000000000000";
mf_tx_data_reg46_int <= "00000000000000000000000000000000";
mf_tx_data_reg47_int <= "00000000000000000000000000000000";
mf_tx_data_reg48_int <= "00000000000000000000000000000000";
mf_tx_data_reg49_int <= "00000000000000000000000000000000";
mf_tx_data_reg50_int <= "00000000000000000000000000000000";
mf_tx_data_reg51_int <= "00000000000000000000000000000000";
mf_tx_data_reg52_int <= "00000000000000000000000000000000";
mf_tx_data_reg53_int <= "00000000000000000000000000000000";
mf_tx_data_reg54_int <= "00000000000000000000000000000000";
mf_tx_data_reg55_int <= "00000000000000000000000000000000";
mf_tx_data_reg56_int <= "00000000000000000000000000000000";
mf_tx_data_reg57_int <= "00000000000000000000000000000000";
mf_tx_data_reg58_int <= "00000000000000000000000000000000";
mf_tx_data_reg59_int <= "00000000000000000000000000000000";
mf_tx_data_reg60_int <= "00000000000000000000000000000000";
mf_tx_data_reg61_int <= "00000000000000000000000000000000";
mf_tx_data_reg62_int <= "00000000000000000000000000000000";
mf_tx_data_reg63_int <= "00000000000000000000000000000000";
mf_tx_data_reg64_int <= "00000000000000000000000000000000";
mf_tx_data_reg65_int <= "00000000000000000000000000000000";
mf_tx_data_reg66_int <= "00000000000000000000000000000000";
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
mf_rst_lock_wr_o <= '0';
mf_rstn_lock_wr_o <= '0';
ack_in_progress <= '0';
else
mf_rst_lock_wr_o <= '0';
mf_rstn_lock_wr_o <= '0';
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(6 downto 0) is
when "0000000" =>
case rwaddr_reg(7 downto 0) is
when "00000000" =>
if (wb_we_i = '1') then
mf_rst_core_int <= wrdata_reg(0);
mf_rst_fd_int <= wrdata_reg(1);
mf_rst_lock_wr_o <= '1';
mf_rstn_core_int <= wrdata_reg(0);
mf_rstn_fd_int <= wrdata_reg(1);
mf_rstn_lock_wr_o <= '1';
end if;
rddata_reg(0) <= mf_rst_core_int;
rddata_reg(1) <= mf_rst_fd_int;
rddata_reg(0) <= mf_rstn_core_int;
rddata_reg(1) <= mf_rstn_fd_int;
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
......@@ -403,26 +627,113 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0000001" =>
when "00000001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= "11000000000000001111111111101110";
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0000010" =>
when "00000010" =>
if (wb_we_i = '1') then
mf_config_host_speed_int <= wrdata_reg(1 downto 0);
mf_config_host_ext_sync_term_en_n_int <= wrdata_reg(2);
mf_config_host_subs_int <= wrdata_reg(15 downto 8);
mf_adc_1v8_shdn_n_int <= wrdata_reg(0);
mf_adc_m5v_shdn_n_int <= wrdata_reg(1);
mf_adc_5v_en_n_int <= wrdata_reg(2);
end if;
rddata_reg(1 downto 0) <= mf_config_host_speed_int;
rddata_reg(2) <= mf_config_host_ext_sync_term_en_n_int;
rddata_reg(15 downto 8) <= mf_config_host_subs_int;
rddata_reg(0) <= mf_adc_1v8_shdn_n_int;
rddata_reg(1) <= mf_adc_m5v_shdn_n_int;
rddata_reg(2) <= mf_adc_5v_en_n_int;
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00000011" =>
if (wb_we_i = '1') then
mf_ext_sync_term_en_int <= wrdata_reg(0);
mf_ext_sync_dir_int <= wrdata_reg(1);
mf_ext_sync_oe_int <= wrdata_reg(2);
mf_ext_sync_tst_n_int <= wrdata_reg(3);
end if;
rddata_reg(0) <= mf_ext_sync_term_en_int;
rddata_reg(1) <= mf_ext_sync_dir_int;
rddata_reg(2) <= mf_ext_sync_oe_int;
rddata_reg(3) <= mf_ext_sync_tst_n_int;
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00000100" =>
if (wb_we_i = '1') then
mf_bus_term_en_n_int <= wrdata_reg(0);
end if;
rddata_reg(0) <= mf_bus_term_en_n_int;
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
......@@ -441,11 +752,10 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0000011" =>
when "00000101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(1 downto 0) <= mf_config_fmc_speed_i;
rddata_reg(31) <= mf_config_fmc_speed_ok_i;
rddata_reg(1 downto 0) <= mf_speed_i;
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
......@@ -475,9 +785,10 @@ begin
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0000100" =>
when "00000110" =>
if (wb_we_i = '1') then
mf_macrocyc_lgth_int <= wrdata_reg(30 downto 0);
mf_macrocyc_start_int <= wrdata_reg(31);
......@@ -486,7 +797,7 @@ begin
rddata_reg(31) <= mf_macrocyc_start_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0000101" =>
when "00000111" =>
if (wb_we_i = '1') then
mf_turnar_lgth_int <= wrdata_reg(30 downto 0);
mf_turnar_start_int <= wrdata_reg(31);
......@@ -495,7 +806,7 @@ begin
rddata_reg(31) <= mf_turnar_start_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0000110" =>
when "00001000" =>
if (wb_we_i = '1') then
mf_silen_lgth_int <= wrdata_reg(30 downto 0);
mf_silen_start_int <= wrdata_reg(31);
......@@ -504,39 +815,39 @@ begin
rddata_reg(31) <= mf_silen_start_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0000111" =>
when "00001001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_macrocyc_time_cnt_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0001000" =>
when "00001010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_turnar_time_cnt_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0001001" =>
when "00001011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_silen_time_cnt_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0001010" =>
when "00001100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_ext_sync_tstamp_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0001011" =>
when "00001101" =>
if (wb_we_i = '1') then
mf_tx_rst_int <= wrdata_reg(0);
mf_tx_start_int <= wrdata_reg(1);
mf_tx_bytes_num_int <= wrdata_reg(16 downto 8);
mf_tx_ctrl_rst_int <= wrdata_reg(0);
mf_tx_ctrl_start_int <= wrdata_reg(1);
mf_tx_ctrl_bytes_num_int <= wrdata_reg(16 downto 8);
end if;
rddata_reg(0) <= mf_tx_rst_int;
rddata_reg(1) <= mf_tx_start_int;
rddata_reg(16 downto 8) <= mf_tx_bytes_num_int;
rddata_reg(0) <= mf_tx_ctrl_rst_int;
rddata_reg(1) <= mf_tx_ctrl_start_int;
rddata_reg(16 downto 8) <= mf_tx_ctrl_bytes_num_int;
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
......@@ -560,10 +871,11 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0001100" =>
when "00001110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(0) <= mf_tx_stop_i;
rddata_reg(0) <= mf_tx_stat_stop_i;
rddata_reg(16 downto 8) <= mf_tx_stat_byte_index_i;
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
......@@ -571,15 +883,6 @@ begin
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
......@@ -597,7 +900,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0001101" =>
when "00001111" =>
if (wb_we_i = '1') then
end if;
rddata_reg(0) <= mf_fd_wdgn_i;
......@@ -634,11 +937,11 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0001110" =>
when "00010000" =>
if (wb_we_i = '1') then
mf_rx_rst_int <= wrdata_reg(0);
mf_rx_ctrl_rst_int <= wrdata_reg(0);
end if;
rddata_reg(0) <= mf_rx_rst_int;
rddata_reg(0) <= mf_rx_ctrl_rst_int;
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
......@@ -672,14 +975,14 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0001111" =>
when "00010001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(0) <= mf_rx_pream_ok_i;
rddata_reg(1) <= mf_rx_frame_ok_i;
rddata_reg(2) <= mf_rx_frame_err_i;
rddata_reg(5 downto 3) <= mf_rx_frame_err_code_i;
rddata_reg(16 downto 8) <= mf_rx_bytes_num_i;
rddata_reg(0) <= mf_rx_stat_pream_ok_i;
rddata_reg(1) <= mf_rx_stat_frame_ok_i;
rddata_reg(2) <= mf_rx_stat_frame_err_i;
rddata_reg(5 downto 3) <= mf_rx_stat_frame_err_code_i;
rddata_reg(16 downto 8) <= mf_rx_stat_bytes_num_i;
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(17) <= 'X';
......@@ -699,7 +1002,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0010000" =>
when "00010010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(7 downto 0) <= mf_rx_data_ctrl_i;
......@@ -729,199 +1032,403 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0010001" =>
when "00010011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg1_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0010010" =>
when "00010100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg2_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0010011" =>
when "00010101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg3_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0010100" =>
when "00010110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg4_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0010101" =>
when "00010111" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg5_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0010110" =>
when "00011000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg6_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0010111" =>
when "00011001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg7_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0011000" =>
when "00011010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg8_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0011001" =>
when "00011011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg9_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0011010" =>
when "00011100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg10_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0011011" =>
when "00011101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg11_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0011100" =>
when "00011110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg12_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0011101" =>
when "00011111" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg13_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0011110" =>
when "00100000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg14_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0011111" =>
when "00100001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg15_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0100000" =>
when "00100010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg16_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0100001" =>
when "00100011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg17_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0100010" =>
when "00100100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg18_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0100011" =>
when "00100101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg19_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0100100" =>
when "00100110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg20_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0100101" =>
when "00100111" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg21_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0100110" =>
when "00101000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg22_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0100111" =>
when "00101001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg23_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0101000" =>
when "00101010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg24_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0101001" =>
when "00101011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg25_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0101010" =>
when "00101100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg26_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0101011" =>
when "00101101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg27_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0101100" =>
when "00101110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg28_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0101101" =>
when "00101111" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg29_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0101110" =>
when "00110000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg30_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0101111" =>
when "00110001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg31_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0110000" =>
when "00110010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg32_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0110001" =>
when "00110011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg33_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00110100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg34_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00110101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg35_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00110110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg36_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00110111" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg37_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00111000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg38_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00111001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg39_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00111010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg40_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00111011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg41_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00111100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg42_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00111101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg43_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00111110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg44_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00111111" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg45_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01000000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg46_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01000001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg47_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01000010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg48_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01000011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg49_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01000100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg50_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01000101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg51_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01000110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg52_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01000111" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg53_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01001000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg54_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01001001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg55_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01001010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg56_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01001011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg57_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01001100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg58_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01001101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg59_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01001110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg60_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01001111" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg61_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01010000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg62_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01010001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg63_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01010010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg64_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01010011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg65_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01010100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg66_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01010101" =>
if (wb_we_i = '1') then
mf_tx_data_ctrl_int <= wrdata_reg(7 downto 0);
end if;
......@@ -952,230 +1459,468 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0110010" =>
when "01010110" =>
if (wb_we_i = '1') then
mf_tx_data_reg1_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg1_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0110011" =>
when "01010111" =>
if (wb_we_i = '1') then
mf_tx_data_reg2_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg2_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0110100" =>
when "01011000" =>
if (wb_we_i = '1') then
mf_tx_data_reg3_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg3_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0110101" =>
when "01011001" =>
if (wb_we_i = '1') then
mf_tx_data_reg4_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg4_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0110110" =>
when "01011010" =>
if (wb_we_i = '1') then
mf_tx_data_reg5_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg5_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0110111" =>
when "01011011" =>
if (wb_we_i = '1') then
mf_tx_data_reg6_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg6_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0111000" =>
when "01011100" =>
if (wb_we_i = '1') then
mf_tx_data_reg7_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg7_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0111001" =>
when "01011101" =>
if (wb_we_i = '1') then
mf_tx_data_reg8_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg8_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0111010" =>
when "01011110" =>
if (wb_we_i = '1') then
mf_tx_data_reg9_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg9_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0111011" =>
when "01011111" =>
if (wb_we_i = '1') then
mf_tx_data_reg10_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg10_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0111100" =>
when "01100000" =>
if (wb_we_i = '1') then
mf_tx_data_reg11_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg11_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0111101" =>
when "01100001" =>
if (wb_we_i = '1') then
mf_tx_data_reg12_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg12_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0111110" =>
when "01100010" =>
if (wb_we_i = '1') then
mf_tx_data_reg13_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg13_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0111111" =>
when "01100011" =>
if (wb_we_i = '1') then
mf_tx_data_reg14_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg14_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1000000" =>
when "01100100" =>
if (wb_we_i = '1') then
mf_tx_data_reg15_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg15_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1000001" =>
when "01100101" =>
if (wb_we_i = '1') then
mf_tx_data_reg16_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg16_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1000010" =>
when "01100110" =>
if (wb_we_i = '1') then
mf_tx_data_reg17_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg17_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1000011" =>
when "01100111" =>
if (wb_we_i = '1') then
mf_tx_data_reg18_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg18_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1000100" =>
when "01101000" =>
if (wb_we_i = '1') then
mf_tx_data_reg19_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg19_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1000101" =>
when "01101001" =>
if (wb_we_i = '1') then
mf_tx_data_reg20_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg20_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1000110" =>
when "01101010" =>
if (wb_we_i = '1') then
mf_tx_data_reg21_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg21_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1000111" =>
when "01101011" =>
if (wb_we_i = '1') then
mf_tx_data_reg22_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg22_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1001000" =>
when "01101100" =>
if (wb_we_i = '1') then
mf_tx_data_reg23_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg23_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1001001" =>
when "01101101" =>
if (wb_we_i = '1') then
mf_tx_data_reg24_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg24_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1001010" =>
when "01101110" =>
if (wb_we_i = '1') then
mf_tx_data_reg25_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg25_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1001011" =>
when "01101111" =>
if (wb_we_i = '1') then
mf_tx_data_reg26_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg26_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1001100" =>
when "01110000" =>
if (wb_we_i = '1') then
mf_tx_data_reg27_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg27_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1001101" =>
when "01110001" =>
if (wb_we_i = '1') then
mf_tx_data_reg28_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg28_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1001110" =>
when "01110010" =>
if (wb_we_i = '1') then
mf_tx_data_reg29_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg29_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1001111" =>
when "01110011" =>
if (wb_we_i = '1') then
mf_tx_data_reg30_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg30_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1010000" =>
when "01110100" =>
if (wb_we_i = '1') then
mf_tx_data_reg31_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg31_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1010001" =>
when "01110101" =>
if (wb_we_i = '1') then
mf_tx_data_reg32_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg32_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01110110" =>
if (wb_we_i = '1') then
mf_tx_data_reg33_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg33_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01110111" =>
if (wb_we_i = '1') then
mf_tx_data_reg34_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg34_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01111000" =>
if (wb_we_i = '1') then
mf_tx_data_reg35_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg35_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01111001" =>
if (wb_we_i = '1') then
mf_tx_data_reg36_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg36_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01111010" =>
if (wb_we_i = '1') then
mf_tx_data_reg37_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg37_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01111011" =>
if (wb_we_i = '1') then
mf_tx_data_reg38_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg38_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01111100" =>
if (wb_we_i = '1') then
mf_tx_data_reg39_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg39_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01111101" =>
if (wb_we_i = '1') then
mf_tx_data_reg40_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg40_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01111110" =>
if (wb_we_i = '1') then
mf_tx_data_reg41_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg41_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01111111" =>
if (wb_we_i = '1') then
mf_tx_data_reg42_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg42_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10000000" =>
if (wb_we_i = '1') then
mf_tx_data_reg43_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg43_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10000001" =>
if (wb_we_i = '1') then
mf_tx_data_reg44_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg44_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10000010" =>
if (wb_we_i = '1') then
mf_tx_data_reg45_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg45_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10000011" =>
if (wb_we_i = '1') then
mf_tx_data_reg46_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg46_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10000100" =>
if (wb_we_i = '1') then
mf_tx_data_reg47_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg47_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10000101" =>
if (wb_we_i = '1') then
mf_tx_data_reg48_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg48_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10000110" =>
if (wb_we_i = '1') then
mf_tx_data_reg49_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg49_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10000111" =>
if (wb_we_i = '1') then
mf_tx_data_reg50_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg50_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10001000" =>
if (wb_we_i = '1') then
mf_tx_data_reg51_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg51_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10001001" =>
if (wb_we_i = '1') then
mf_tx_data_reg52_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg52_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10001010" =>
if (wb_we_i = '1') then
mf_tx_data_reg53_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg53_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10001011" =>
if (wb_we_i = '1') then
mf_tx_data_reg54_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg54_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10001100" =>
if (wb_we_i = '1') then
mf_tx_data_reg55_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg55_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10001101" =>
if (wb_we_i = '1') then
mf_tx_data_reg56_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg56_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10001110" =>
if (wb_we_i = '1') then
mf_tx_data_reg57_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg57_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10001111" =>
if (wb_we_i = '1') then
mf_tx_data_reg58_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg58_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10010000" =>
if (wb_we_i = '1') then
mf_tx_data_reg59_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg59_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10010001" =>
if (wb_we_i = '1') then
mf_tx_data_reg60_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg60_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10010010" =>
if (wb_we_i = '1') then
mf_tx_data_reg61_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg61_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10010011" =>
if (wb_we_i = '1') then
mf_tx_data_reg62_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg62_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10010100" =>
if (wb_we_i = '1') then
mf_tx_data_reg63_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg63_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10010101" =>
if (wb_we_i = '1') then
mf_tx_data_reg64_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg64_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10010110" =>
if (wb_we_i = '1') then
mf_tx_data_reg65_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg65_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10010111" =>
if (wb_we_i = '1') then
mf_tx_data_reg66_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg66_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
......@@ -1190,20 +1935,29 @@ begin
-- Drive the data output bus
wb_dat_o <= rddata_reg;
-- reset of the masterFIP core
mf_rst_core_o <= mf_rst_core_int;
mf_rstn_core_o <= mf_rstn_core_int;
-- reset of the fieldrive chip (FD_RSTN)
mf_rst_fd_o <= mf_rst_fd_int;
mf_rstn_fd_o <= mf_rstn_fd_int;
-- reset magic value
-- pass-through field: reset magic value in register: rst
mf_rst_lock_o <= wrdata_reg(31 downto 16);
-- speed
mf_config_host_speed_o <= mf_config_host_speed_int;
-- termination enable on the external synch input
mf_config_host_ext_sync_term_en_n_o <= mf_config_host_ext_sync_term_en_n_int;
-- station address
mf_config_host_subs_o <= mf_config_host_subs_int;
-- pass-through field: reset magic value in register: rstn
mf_rstn_lock_o <= wrdata_reg(31 downto 16);
-- 1v8_shdn_n
mf_adc_1v8_shdn_n_o <= mf_adc_1v8_shdn_n_int;
-- m5v_shdn_n
mf_adc_m5v_shdn_n_o <= mf_adc_m5v_shdn_n_int;
-- 5v_en_n
mf_adc_5v_en_n_o <= mf_adc_5v_en_n_int;
-- termination enable
mf_ext_sync_term_en_o <= mf_ext_sync_term_en_int;
-- tranceiver direction
mf_ext_sync_dir_o <= mf_ext_sync_dir_int;
-- tranceiver output enable
mf_ext_sync_oe_o <= mf_ext_sync_oe_int;
-- test pulse
mf_ext_sync_tst_n_o <= mf_ext_sync_tst_n_int;
-- 150ohms terination of the bus
mf_bus_term_en_n_o <= mf_bus_term_en_n_int;
-- speed
-- speed match
-- macrocycle lgth
mf_macrocyc_lgth_o <= mf_macrocyc_lgth_int;
-- macrocycle cnt start
......@@ -1221,22 +1975,23 @@ begin
-- silence time counter
-- ext_sync_tstamp
-- tx rst
mf_tx_rst_o <= mf_tx_rst_int;
mf_tx_ctrl_rst_o <= mf_tx_ctrl_rst_int;
-- tx strt
mf_tx_start_o <= mf_tx_start_int;
mf_tx_ctrl_start_o <= mf_tx_ctrl_start_int;
-- tx number of bytes
mf_tx_bytes_num_o <= mf_tx_bytes_num_int;
-- tx stopped
mf_tx_ctrl_bytes_num_o <= mf_tx_ctrl_bytes_num_int;
-- tx ended
-- tx current byte
-- fd watchdog
-- fd transmitter error
-- rx rst
mf_rx_rst_o <= mf_rx_rst_int;
mf_rx_ctrl_rst_o <= mf_rx_ctrl_rst_int;
-- rx preamble detected
-- rx frame ok
-- rx frame error
-- rx frame error code
-- rx number of data bytes
-- rx ctrl byte
-- rx data ctrl byte
-- reg 1
-- reg2
-- reg3
......@@ -1269,6 +2024,40 @@ begin
-- reg30
-- reg31
-- reg32
-- reg 33
-- reg34
-- reg35
-- reg36
-- reg37
-- reg38
-- reg39
-- reg40
-- reg41
-- reg42
-- reg43
-- reg44
-- reg45
-- reg46
-- reg47
-- reg48
-- reg49
-- reg50
-- reg51
-- reg52
-- reg53
-- reg54
-- reg55
-- reg56
-- reg57
-- reg58
-- reg59
-- reg60
-- reg61
-- reg62
-- reg63
-- reg64
-- reg65
-- reg66
-- tx ctrl byte
mf_tx_data_ctrl_o <= mf_tx_data_ctrl_int;
-- reg1
......@@ -1335,6 +2124,74 @@ begin
mf_tx_data_reg31_o <= mf_tx_data_reg31_int;
-- reg32
mf_tx_data_reg32_o <= mf_tx_data_reg32_int;
-- reg 33
mf_tx_data_reg33_o <= mf_tx_data_reg33_int;
-- reg34
mf_tx_data_reg34_o <= mf_tx_data_reg34_int;
-- reg35
mf_tx_data_reg35_o <= mf_tx_data_reg35_int;
-- reg36
mf_tx_data_reg36_o <= mf_tx_data_reg36_int;
-- reg37
mf_tx_data_reg37_o <= mf_tx_data_reg37_int;
-- reg38
mf_tx_data_reg38_o <= mf_tx_data_reg38_int;
-- reg39
mf_tx_data_reg39_o <= mf_tx_data_reg39_int;
-- reg40
mf_tx_data_reg40_o <= mf_tx_data_reg40_int;
-- reg41
mf_tx_data_reg41_o <= mf_tx_data_reg41_int;
-- reg42
mf_tx_data_reg42_o <= mf_tx_data_reg42_int;
-- reg43
mf_tx_data_reg43_o <= mf_tx_data_reg43_int;
-- reg44
mf_tx_data_reg44_o <= mf_tx_data_reg44_int;
-- reg45
mf_tx_data_reg45_o <= mf_tx_data_reg45_int;
-- reg46
mf_tx_data_reg46_o <= mf_tx_data_reg46_int;
-- reg47
mf_tx_data_reg47_o <= mf_tx_data_reg47_int;
-- reg48
mf_tx_data_reg48_o <= mf_tx_data_reg48_int;
-- reg49
mf_tx_data_reg49_o <= mf_tx_data_reg49_int;
-- reg50
mf_tx_data_reg50_o <= mf_tx_data_reg50_int;
-- reg51
mf_tx_data_reg51_o <= mf_tx_data_reg51_int;
-- reg52
mf_tx_data_reg52_o <= mf_tx_data_reg52_int;
-- reg53
mf_tx_data_reg53_o <= mf_tx_data_reg53_int;
-- reg54
mf_tx_data_reg54_o <= mf_tx_data_reg54_int;
-- reg55
mf_tx_data_reg55_o <= mf_tx_data_reg55_int;
-- reg56
mf_tx_data_reg56_o <= mf_tx_data_reg56_int;
-- reg57
mf_tx_data_reg57_o <= mf_tx_data_reg57_int;
-- reg58
mf_tx_data_reg58_o <= mf_tx_data_reg58_int;
-- reg59
mf_tx_data_reg59_o <= mf_tx_data_reg59_int;
-- reg60
mf_tx_data_reg60_o <= mf_tx_data_reg60_int;
-- reg61
mf_tx_data_reg61_o <= mf_tx_data_reg61_int;
-- reg62
mf_tx_data_reg62_o <= mf_tx_data_reg62_int;
-- reg63
mf_tx_data_reg63_o <= mf_tx_data_reg63_int;
-- reg64
mf_tx_data_reg64_o <= mf_tx_data_reg64_int;
-- reg65
mf_tx_data_reg65_o <= mf_tx_data_reg65_int;
-- reg66
mf_tx_data_reg66_o <= mf_tx_data_reg66_int;
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
......
rtl/masterFIP_pkg.vhd
View file @ eaf3913c
......@@ -102,23 +102,6 @@ package masterFIP_pkg is
date => x"20121116",
name => "WB-SPEC.CSR ")));
constant c_MASTERFIP_EIC_SDB_DEVICE : t_sdb_device :=
(abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", -- 32-bit port granularity
sdb_component =>
(addr_first => x"0000000000000000",
addr_last => x"000000000000000F",
product =>
(vendor_id => x"000000000000CE42", -- CERN
device_id => x"00000605", -- "WB-FMC-ADC.EIC " | md5sum | cut -c1-8
version => x"00000001",
date => x"20121116",
name => "WB-MASTERFIP.EIC ")));
constant c_I2C_SDB_DEVICE : t_sdb_device :=
(abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
......@@ -135,7 +118,7 @@ package masterFIP_pkg is
date => x"20121116",
name => "WB-I2C.Control ")));
constant c_MASTERFIP_CSR_SDB_DEVICE : t_sdb_device :=
constant c_MASTERFIP_SDB_DEVICE : t_sdb_device :=
(abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
......@@ -143,12 +126,12 @@ package masterFIP_pkg is
wbd_width => x"4", -- 32-bit port granularity
sdb_component =>
(addr_first => x"0000000000000000",
addr_last => x"00000000000000FF",
addr_last => x"000000000000FFFF",
product =>
(vendor_id => x"000000000000CE42", -- CERN
device_id => x"00000604", -- "WB-TDC-Core-Config " | md5sum | cut -c1-8
device_id => x"00000AAA", -- ...
version => x"00000001",
date => x"20130429",
date => x"20151006",
name => "WB-MASTERFIP.CSR ")));
......@@ -162,8 +145,8 @@ package masterFIP_pkg is
-- Vector with the data Registers --
---------------------------------------------------------------------------------------------------
subtype data_word is std_logic_vector(31 downto 0);
type rx_frame_t is array (31 downto 0) of data_word;
type tx_frame_t is array (31 downto 0) of data_word;
type rx_frame_t is array (65 downto 0) of data_word;
type tx_frame_t is array (65 downto 0) of data_word;
......@@ -191,17 +174,207 @@ package masterFIP_pkg is
---------------------------------------------------------------------------------------------------
-- Components Declarations: --
---------------------------------------------------------------------------------------------------
component fmc_masterFIP_mezz is
component fmc_masterfip_csr is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(7 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
mf_rstn_core_o : out std_logic;
mf_rstn_fd_o : out std_logic;
mf_rstn_lock_o : out std_logic_vector(15 downto 0);
mf_rstn_lock_wr_o : out std_logic;
mf_adc_1v8_shdn_n_o : out std_logic;
mf_adc_m5v_shdn_n_o : out std_logic;
mf_adc_5v_en_n_o : out std_logic;
mf_ext_sync_term_en_o : out std_logic;
mf_ext_sync_dir_o : out std_logic;
mf_ext_sync_oe_o : out std_logic;
mf_ext_sync_tst_n_o : out std_logic;
mf_ext_sync_tstamp_i : in std_logic_vector(31 downto 0);
mf_bus_term_en_n_o : out std_logic;
mf_speed_i : in std_logic_vector(1 downto 0);
mf_macrocyc_lgth_o : out std_logic_vector(30 downto 0);
mf_macrocyc_start_o : out std_logic;
mf_turnar_lgth_o : out std_logic_vector(30 downto 0);
mf_turnar_start_o : out std_logic;
mf_silen_lgth_o : out std_logic_vector(30 downto 0);
mf_silen_start_o : out std_logic;
mf_macrocyc_time_cnt_i : in std_logic_vector(31 downto 0);
mf_turnar_time_cnt_i : in std_logic_vector(31 downto 0);
mf_silen_time_cnt_i : in std_logic_vector(31 downto 0);
mf_tx_ctrl_rst_o : out std_logic;
mf_tx_ctrl_start_o : out std_logic;
mf_tx_ctrl_bytes_num_o : out std_logic_vector(8 downto 0);
mf_tx_stat_stop_i : in std_logic;
mf_tx_stat_byte_index_i : in std_logic_vector(8 downto 0);
mf_fd_wdgn_i : in std_logic;
mf_fd_txer_i : in std_logic;
mf_rx_ctrl_rst_o : out std_logic;
mf_rx_stat_pream_ok_i : in std_logic;
mf_rx_stat_frame_ok_i : in std_logic;
mf_rx_stat_frame_err_i : in std_logic;
mf_rx_stat_frame_err_code_i : in std_logic_vector(2 downto 0);
mf_rx_stat_bytes_num_i : in std_logic_vector(8 downto 0);
mf_rx_data_ctrl_i : in std_logic_vector(7 downto 0);
mf_rx_data_reg1_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg2_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg3_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg4_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg5_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg6_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg7_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg8_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg9_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg10_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg11_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg12_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg13_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg14_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg15_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg16_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg17_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg18_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg19_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg20_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg21_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg22_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg23_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg24_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg25_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg26_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg27_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg28_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg29_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg30_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg31_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg32_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg33_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg34_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg35_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg36_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg37_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg38_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg39_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg40_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg41_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg42_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg43_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg44_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg45_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg46_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg47_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg48_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg49_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg50_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg51_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg52_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg53_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg54_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg55_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg56_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg57_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg58_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg59_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg60_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg61_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg62_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg63_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg64_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg65_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg66_i : in std_logic_vector(31 downto 0);
mf_tx_data_ctrl_o : out std_logic_vector(7 downto 0);
mf_tx_data_reg1_o : out std_logic_vector(31 downto 0);
mf_tx_data_reg2_o : out std_logic_vector(31 downto 0);
mf_tx_data_reg3_o : out std_logic_vector(31 downto 0);
mf_tx_data_reg4_o : out std_logic_vector(31 downto 0);
mf_tx_data_reg5_o : out std_logic_vector(31 downto 0);
mf_tx_data_reg6_o : out std_logic_vector(31 downto 0);
mf_tx_data_reg7_o : out std_logic_vector(31 downto 0);
mf_tx_data_reg8_o : out std_logic_vector(31 downto 0);
mf_tx_data_reg9_o : out std_logic_vector(31 downto 0);
mf_tx_data_reg10_o : out std_logic_vector(31 downto 0);
mf_tx_data_reg11_o : out std_logic_vector(31 downto 0);
mf_tx_data_reg12_o : out std_logic_vector(31 downto 0);
mf_tx_data_reg13_o : out std_logic_vector(31 downto 0);
mf_tx_data_reg14_o : out std_logic_vector(31 downto 0);
mf_tx_data_reg15_o : out std_logic_vector(31 downto 0);
mf_tx_data_reg16_o : out std_logic_vector(31 downto 0);
mf_tx_data_reg17_o : out std_logic_vector(31 downto 0);
mf_tx_data_reg18_o : out std_logic_vector(31 downto 0);
mf_tx_data_reg19_o : out std_logic_vector(31 downto 0);
mf_tx_data_reg20_o : out std_logic_vector(31 downto 0);
mf_tx_data_reg21_o : out std_logic_vector(31 downto 0);
mf_tx_data_reg22_o : out std_logic_vector(31 downto 0);
mf_tx_data_reg23_o : out std_logic_vector(31 downto 0);
mf_tx_data_reg24_o : out std_logic_vector(31 downto 0);
mf_tx_data_reg25_o : out std_logic_vector(31 downto 0);
mf_tx_data_reg26_o : out std_logic_vector(31 downto 0);
mf_tx_data_reg27_o : out std_logic_vector(31 downto 0);
mf_tx_data_reg28_o : out std_logic_vector(31 downto 0);
mf_tx_data_reg29_o : out std_logic_vector(31 downto 0);
mf_tx_data_reg30_o : out std_logic_vector(31 downto 0);
mf_tx_data_reg31_o : out std_logic_vector(31 downto 0);
mf_tx_data_reg32_o : out std_logic_vector(31 downto 0);
mf_tx_data_reg33_o : out std_logic_vector(31 downto 0);
mf_tx_data_reg34_o : out std_logic_vector(31 downto 0);
mf_tx_data_reg35_o : out std_logic_vector(31 downto 0);
mf_tx_data_reg36_o : out std_logic_vector(31 downto 0);
mf_tx_data_reg37_o : out std_logic_vector(31 downto 0);
mf_tx_data_reg38_o : out std_logic_vector(31 downto 0);
mf_tx_data_reg39_o : out std_logic_vector(31 downto 0);
mf_tx_data_reg40_o : out std_logic_vector(31 downto 0);
mf_tx_data_reg41_o : out std_logic_vector(31 downto 0);
mf_tx_data_reg42_o : out std_logic_vector(31 downto 0);
mf_tx_data_reg43_o : out std_logic_vector(31 downto 0);
mf_tx_data_reg44_o : out std_logic_vector(31 downto 0);
mf_tx_data_reg45_o : out std_logic_vector(31 downto 0);
mf_tx_data_reg46_o : out std_logic_vector(31 downto 0);
mf_tx_data_reg47_o : out std_logic_vector(31 downto 0);
mf_tx_data_reg48_o : out std_logic_vector(31 downto 0);
mf_tx_data_reg49_o : out std_logic_vector(31 downto 0);
mf_tx_data_reg50_o : out std_logic_vector(31 downto 0);
mf_tx_data_reg51_o : out std_logic_vector(31 downto 0);
mf_tx_data_reg52_o : out std_logic_vector(31 downto 0);
mf_tx_data_reg53_o : out std_logic_vector(31 downto 0);
mf_tx_data_reg54_o : out std_logic_vector(31 downto 0);
mf_tx_data_reg55_o : out std_logic_vector(31 downto 0);
mf_tx_data_reg56_o : out std_logic_vector(31 downto 0);
mf_tx_data_reg57_o : out std_logic_vector(31 downto 0);
mf_tx_data_reg58_o : out std_logic_vector(31 downto 0);
mf_tx_data_reg59_o : out std_logic_vector(31 downto 0);
mf_tx_data_reg60_o : out std_logic_vector(31 downto 0);
mf_tx_data_reg61_o : out std_logic_vector(31 downto 0);
mf_tx_data_reg62_o : out std_logic_vector(31 downto 0);
mf_tx_data_reg63_o : out std_logic_vector(31 downto 0);
mf_tx_data_reg64_o : out std_logic_vector(31 downto 0);
mf_tx_data_reg65_o : out std_logic_vector(31 downto 0);
mf_tx_data_reg66_o : out std_logic_vector(31 downto 0));
end component;
---------------------------------------------------------------------------------------------------
component fmc_masterFIP_core is
generic
(g_with_wrabbit_core: boolean := FALSE;
g_span : integer := 32;
(g_span : integer := 32;
g_width : integer := 32;
values_for_simul : boolean := FALSE);
port
(clk_sys_i : in std_logic;
rst_sys_n_i : in std_logic;
(clk_i : in std_logic;
rst_i : in std_logic;
speed_b0_i : in std_logic;
speed_b1_i : in std_logic;
fd_rxcdn_i : in std_logic;
......@@ -212,164 +385,25 @@ package masterFIP_pkg is
fd_txck_o : out std_logic;
fd_txd_o : out std_logic;
fd_txena_o : out std_logic;
wb_adr_i : in std_logic_vector(31 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
bus_term_en_n_o : out std_logic;
ext_sync_term_en_o : out std_logic;
ext_sync_dir_o : out std_logic;
ext_sync_oe_o : out std_logic;
ext_sync_tst_n_o : out std_logic;
ext_sync_i : in std_logic;
adc_1v8_shdn_n_o : out std_logic;
adc_m5v_shdn_n_o : out std_logic;
adc_5v_en_n_o : out std_logic;
aux_o : out std_logic_vector(7 downto 0);
wb_adr_i : in std_logic_vector(g_span-1 downto 0);
wb_dat_i : in std_logic_vector(g_width-1 downto 0);
wb_stb_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_we_i : in std_logic;
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
wb_irq_o : out std_logic;
aux_o : out std_logic_vector(7 downto 0));
end component;
component fmc_masterfip_csr is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(6 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
mf_rst_core_o : out std_logic;
mf_rst_fd_o : out std_logic;
mf_rst_lock_o : out std_logic_vector(15 downto 0);
mf_rst_lock_wr_o : out std_logic;
mf_config_host_speed_o : out std_logic_vector(1 downto 0);
mf_config_host_ext_sync_term_en_n_o : out std_logic;
mf_config_host_subs_o : out std_logic_vector(7 downto 0);
mf_config_fmc_speed_i : in std_logic_vector(1 downto 0);
mf_config_fmc_speed_ok_i : in std_logic;
mf_macrocyc_lgth_o : out std_logic_vector(30 downto 0);
mf_macrocyc_start_o : out std_logic;
mf_turnar_lgth_o : out std_logic_vector(30 downto 0);
mf_turnar_start_o : out std_logic;
mf_silen_lgth_o : out std_logic_vector(30 downto 0);
mf_silen_start_o : out std_logic;
mf_macrocyc_time_cnt_i : in std_logic_vector(31 downto 0);
mf_turnar_time_cnt_i : in std_logic_vector(31 downto 0);
mf_silen_time_cnt_i : in std_logic_vector(31 downto 0);
mf_ext_sync_tstamp_i : in std_logic_vector(31 downto 0);
mf_tx_rst_o : out std_logic;
mf_tx_start_o : out std_logic;
mf_tx_bytes_num_o : out std_logic_vector(8 downto 0);
mf_tx_stop_i : in std_logic;
mf_fd_wdgn_i : in std_logic;
mf_fd_txer_i : in std_logic;
mf_rx_rst_o : out std_logic;
mf_rx_pream_ok_i : in std_logic;
mf_rx_frame_ok_i : in std_logic;
mf_rx_frame_err_i : in std_logic;
mf_rx_frame_err_code_i : in std_logic_vector(2 downto 0);
mf_rx_bytes_num_i : in std_logic_vector(8 downto 0);
mf_rx_data_ctrl_i : in std_logic_vector(7 downto 0);
mf_rx_data_reg1_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg2_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg3_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg4_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg5_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg6_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg7_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg8_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg9_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg10_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg11_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg12_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg13_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg14_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg15_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg16_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg17_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg18_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg19_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg20_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg21_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg22_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg23_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg24_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg25_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg26_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg27_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg28_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg29_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg30_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg31_i : in std_logic_vector(31 downto 0);
mf_rx_data_reg32_i : in std_logic_vector(31 downto 0);
mf_tx_data_ctrl_o : out std_logic_vector(7 downto 0);
mf_tx_data_reg1_o : out std_logic_vector(31 downto 0);
mf_tx_data_reg2_o : out std_logic_vector(31 downto 0);
mf_tx_data_reg3_o : out std_logic_vector(31 downto 0);
mf_tx_data_reg4_o : out std_logic_vector(31 downto 0);
mf_tx_data_reg5_o : out std_logic_vector(31 downto 0);
mf_tx_data_reg6_o : out std_logic_vector(31 downto 0);
mf_tx_data_reg7_o : out std_logic_vector(31 downto 0);
mf_tx_data_reg8_o : out std_logic_vector(31 downto 0);
mf_tx_data_reg9_o : out std_logic_vector(31 downto 0);
mf_tx_data_reg10_o : out std_logic_vector(31 downto 0);
mf_tx_data_reg11_o : out std_logic_vector(31 downto 0);
mf_tx_data_reg12_o : out std_logic_vector(31 downto 0);
mf_tx_data_reg13_o : out std_logic_vector(31 downto 0);
mf_tx_data_reg14_o : out std_logic_vector(31 downto 0);
mf_tx_data_reg15_o : out std_logic_vector(31 downto 0);
mf_tx_data_reg16_o : out std_logic_vector(31 downto 0);
mf_tx_data_reg17_o : out std_logic_vector(31 downto 0);
mf_tx_data_reg18_o : out std_logic_vector(31 downto 0);
mf_tx_data_reg19_o : out std_logic_vector(31 downto 0);
mf_tx_data_reg20_o : out std_logic_vector(31 downto 0);
mf_tx_data_reg21_o : out std_logic_vector(31 downto 0);
mf_tx_data_reg22_o : out std_logic_vector(31 downto 0);
mf_tx_data_reg23_o : out std_logic_vector(31 downto 0);
mf_tx_data_reg24_o : out std_logic_vector(31 downto 0);
mf_tx_data_reg25_o : out std_logic_vector(31 downto 0);
mf_tx_data_reg26_o : out std_logic_vector(31 downto 0);
mf_tx_data_reg27_o : out std_logic_vector(31 downto 0);
mf_tx_data_reg28_o : out std_logic_vector(31 downto 0);
mf_tx_data_reg29_o : out std_logic_vector(31 downto 0);
mf_tx_data_reg30_o : out std_logic_vector(31 downto 0);
mf_tx_data_reg31_o : out std_logic_vector(31 downto 0);
mf_tx_data_reg32_o : out std_logic_vector(31 downto 0));
end component;
---------------------------------------------------------------------------------------------------
component fmc_masterFIP_core is
generic
(g_span : integer := 32;
g_width : integer := 32;
values_for_simul : boolean := FALSE);
port
(clk_i : in std_logic;
rst_i : in std_logic;
speed_b0_i : in std_logic;
speed_b1_i : in std_logic;
fd_rxcdn_i : in std_logic;
fd_rxd_i : in std_logic;
fd_txer_i : in std_logic;
fd_wdgn_i : in std_logic;
fd_rstn_o : out std_logic;
fd_txck_o : out std_logic;
fd_txd_o : out std_logic;
fd_txena_o : out std_logic;
irq_p_o : out std_logic_vector(7 downto 0);
aux_o : out std_logic_vector(7 downto 0);
wb_adr_i : in std_logic_vector(g_span-1 downto 0);
wb_dat_i : in std_logic_vector(g_width-1 downto 0);
wb_stb_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_we_i : in std_logic;
wb_cyc_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
wb_dat_o : out std_logic_vector(g_width-1 downto 0));
wb_dat_o : out std_logic_vector(g_width-1 downto 0));
end component;
......@@ -383,50 +417,6 @@ package masterFIP_pkg is
end component;
---------------------------------------------------------------------------------------------------
component fmc_masterfip_eic
port
(rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(1 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
wb_int_o : out std_logic;
irq_macrocy_start_i : in std_logic;
irq_silen_time_expire_i : in std_logic;
irq_turnar_time_expire_i : in std_logic;
irq_tx_completed_i : in std_logic;
irq_rx_fss_ok_i : in std_logic;
irq_rx_frame_ok_i : in std_logic;
irq_rx_crc_wrong_i : in std_logic);
end component fmc_masterfip_eic;
---------------------------------------------------------------------------------------------------
component irq_controller
port
(clk_i : in std_logic;
rst_n_i : in std_logic;
irq_src_p_i : in std_logic_vector(31 downto 0);
wb_adr_i : in std_logic_vector(1 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
----------------------------------------------------------------------
wb_dat_o : out std_logic_vector(31 downto 0);
wb_ack_o : out std_logic;
irq_p_o : out std_logic);
end component irq_controller;
---------------------------------------------------------------------------------------------------
component carrier_info
port
......@@ -463,16 +453,16 @@ package masterFIP_pkg is
---------------------------------------------------------------------------------------------------
component masterfip_rx is
port (
uclk_i : in std_logic;
rate_i : in std_logic_vector (1 downto 0);
clk_40m_i : in std_logic;
speed_i : in std_logic_vector (1 downto 0);
fd_rxd_a_i : in std_logic;
core_rst_i : in std_logic;
rst_i : in std_logic;
rx_rst_i : in std_logic;
-----------------------------------------------------------------
rx_byte_index_o : out std_logic_vector (7 downto 0);
rx_ctrl_byte_o : out std_logic_vector (7 downto 0);
rx_frame_o : out rx_frame_t;
rx_byte_o : out std_logic_vector (7 downto 0);
rx_byte_index_o : out std_logic_vector (8 downto 0);
rx_ctrl_byte_o : out std_logic_vector (7 downto 0);
rx_frame_o : out rx_frame_t;
rx_byte_o : out std_logic_vector (7 downto 0);
rx_byte_ready_p_o : out std_logic;
rx_fss_crc_fes_ok_p_o : out std_logic;
rx_fss_received_p_o : out std_logic;
......@@ -484,19 +474,19 @@ package masterFIP_pkg is
---------------------------------------------------------------------------------------------------
component masterfip_tx is
port (
uclk_i : in std_logic;
rate_i : in std_logic_vector (1 downto 0);
core_rst_i : in std_logic;
tx_start_p_i : in std_logic;
tx_bytes_num_i : in std_logic_vector (7 downto 0);
tx_frame_i : in tx_frame_t;
tx_ctrl_byte_i : in std_logic_vector (7 downto 0);
clk_40m_i : in std_logic;
speed_i : in std_logic_vector (1 downto 0);
rst_i : in std_logic;
tx_start_p_i : in std_logic;
tx_bytes_num_i : in std_logic_vector (8 downto 0);
tx_frame_i : in tx_frame_t;
tx_ctrl_byte_i : in std_logic_vector (7 downto 0);
-----------------------------------------------------------------
tx_byte_index_o : out std_logic_vector (7 downto 0);
tx_completed_p_o : out std_logic;
tx_data_o : out std_logic;
tx_enable_o : out std_logic;
tx_clk_o : out std_logic);
tx_byte_index_o : out std_logic_vector (8 downto 0);
tx_end_p_o : out std_logic;
tx_data_o : out std_logic;
tx_enable_o : out std_logic;
tx_clk_o : out std_logic);
-----------------------------------------------------------------
end component masterfip_tx;
......
rtl/masterfip_rx.vhd
View file @ eaf3913c
......@@ -7,32 +7,32 @@
---------------------------------------------------------------------------------------------------
-- |
-- masterfip_rx |
-- masterfip_rx |
-- |
---------------------------------------------------------------------------------------------------
-- File masterfip_rx.vhd |
-- File masterfip_rx.vhd |
-- |
-- Description The unit groups the main actions that regard FIELDRIVE data reception. |
-- It instantiates the units: |
-- |
-- o wf_rx_deserializer: for the formation of bytes of data to be provided to the: |
-- o wf_engine_control unit, for the contents of ID_DAT frames |
-- o wf_cons_bytes_processor unit, for the contents of consumed|
-- RP_DAT frames |
-- It instantiates the units/processes: |
-- |
-- o wf_rx_osc : for the clock recovery |
-- |
-- o wf_rx_deglitcher : for the filtering of the input FD_RXD |
-- |
-- o wf_rx_deserializer: for the bytes retrieval; also detects FSS/FES & checks CRC |
-- |
-- o bytes_c : for the counting of the retrieved bytes |
-- |
-- _________________________ _________________________ |
-- | | | | |
-- | wf_Consumption | | wf_engine_control | |
-- |_________________________| |_________________________| |
-- /\ /\ |
-- o create_32bit_words: for the formation of 32-bit words to be provided to the WRNC|
-- |
-- WRNC |
-- ___________________________________________________________ |
-- | wf_fd_revceiver | |
-- | _________ | |
-- | | |
-- | _________ _______________________ | |
-- | | | | | | |
-- | | bytes_c | | create_32bit_words | | |
-- | |_________| |_______________________| | |
-- | /\ /\ _________ | |
-- | _______________________________________ | | | |
-- | | | | | | |
-- | | wf_rx_deserializer | | wf_rx | | |
......@@ -47,18 +47,17 @@
-- |___________________________________________________________| |
-- /\ |
-- ___________________________________________________________________ |
-- 0_____________________________FIELDBUS______________________________O |
-- 0_____________________________FIELDBUS______________________________0 |
-- |
-- |
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 15/02/2011 |
-- Authors Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 30/09/2015 |
-- Version v0.01 |
-- Depends on wf_reset_unit |
-- wf_engine_control |
-- Depends on |
-- |
---------------- |
-- Last changes |
-- 02/2011 v0.01 EG First version |
-- 09/2015 v0.01 EG First version |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
......@@ -86,7 +85,7 @@ use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific library
library work;
use work.masterFIP_pkg.all; -- definitions of types, constants, entities
use work.masterFIP_pkg.all; -- definitions of types, constants, entities
use work.wf_package.all;
......@@ -95,39 +94,44 @@ use work.wf_package.all;
--=================================================================================================
entity masterfip_rx is port(
-- INPUTS
-- nanoFIP User Interface, General signals
uclk_i : in std_logic; -- 40 MHZ clock
clk_40m_i : in std_logic; -- 40 MHZ clock
-- nanoFIP WorldFIP Settings
rate_i : in std_logic_vector (1 downto 0); -- WorldFIP bit rate
rst_i : in std_logic; -- core rst, synched with clk_40m_i
rx_rst_i : in std_logic; -- rx reset during production or
-- reset pulse from the WRNC when during
-- reception a frame is rejected
-- (ex: RP_DAT > 133 bytes, wrong CTRL byte)
speed_i : in std_logic_vector(1 downto 0); -- WorldFIP bit rate
-- nanoFIP FIELDRIVE
fd_rxd_a_i : in std_logic; -- receiver data
fd_rxd_a_i : in std_logic; -- FielDrive receiver data
-- Signal from the wf_reset_unit
core_rst_i : in std_logic; -- nanoFIP internal reset
-- Signal from the wf_engine_control unit
rx_rst_i : in std_logic; -- reset during production or
-- reset pulse when during reception a frame is rejected
-- by the engine_control (example: ID_DAT > 8 bytes,
-- RP_DAT > 133 bytes, wrong ID_DAT CTRL/ VAR/ SUBS bytes)
-- OUTPUTS
rx_byte_ready_p_o : out std_logic; -- pulse indicating a new retrieved byte
rx_byte_o : out std_logic_vector(7 downto 0); -- currently retrieved byte
-- OUTPUTS
rx_byte_index_o : out std_logic_vector (7 downto 0);
rx_ctrl_byte_o : out std_logic_vector (7 downto 0);
rx_frame_o : out rx_frame_t;
-- Signals to the wf_engine_control and wf_consumption
rx_byte_o : out std_logic_vector (7 downto 0); -- retrieved data byte
rx_byte_ready_p_o : out std_logic; -- pulse indicating a new retrieved data byte
rx_fss_crc_fes_ok_p_o : out std_logic; -- indication of a frame (ID_DAT or RP_DAT) with
-- correct FSS, FES & CRC; pulse upon FES detection
rx_crc_wrong_p_o : out std_logic; -- indication of a frame (ID_DAT or RP_DAT) with
-- wrong CRC; pulse upon FES detection
-- Signals to the wf_engine_control
rx_fss_received_p_o : out std_logic);-- pulse upon FSS detection (ID/ RP_DAT)
rx_byte_index_o : out std_logic_vector(8 downto 0); -- index of currently retrieved byte
-- counting starts after FSS; it includes the
-- CTRL, DATA, CRC and FES fields
rx_ctrl_byte_o : out std_logic_vector(7 downto 0); -- frame CTRL byte
rx_frame_o : out rx_frame_t; -- frame DATA bytes
-- structure with 66 words of 32-bit each
-- this represents the max length of a frame
-- upon the rx_fss_crc_fes_ok_p_o only
-- rx_byte_index_o bytes have to be read by the WRNC
rx_fss_crc_fes_ok_p_o : out std_logic; -- indication of a frame with
-- correct FSS, FES & CRC; pulse upon FES detection
rx_crc_wrong_p_o : out std_logic; -- indication of a frame with
-- wrong CRC; pulse upon FES detection
rx_fss_received_p_o : out std_logic); -- pulse upon FSS detection (ID/ RP_DAT)
end entity masterfip_rx;
......@@ -137,72 +141,50 @@ end entity masterfip_rx;
--=================================================================================================
architecture struc of masterfip_rx is
-- wf_rx_osc
signal s_rx_osc_rst, s_adjac_bits_window, s_signif_edge_window : std_logic;
signal s_sample_bit_p, s_sample_manch_bit_p : std_logic;
-- wf_rx_deglitcher
signal s_fd_rxd_filt, s_rxd_filt_edge_p : std_logic;
signal s_fd_rxd_filt_f_edge_p, s_fd_rxd_filt_r_edge_p : std_logic;
-- wf_rx_deserializer
signal rx_byte_ready_p : std_logic;
signal rx_byte : std_logic_vector (7 downto 0);
-- retreived bytes into 32-bit regs
signal byte0, byte1, byte2, byte3 : std_logic_vector(7 downto 0);
signal word32 : std_logic_vector(31 downto 0);
signal word32_num : integer range 0 to 31;
signal rx_byte_index, rx_byte_index_d1 : unsigned(7 downto 0);
-- bytes counter
signal rx_byte_index, rx_byte_index_d1 : unsigned(8 downto 0);
signal bytes_c_rst : std_logic;
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
---------------------------------------------------------------------------------------------------
-- Deglitcher --
-- Deserializer as in the nanoFIP project --
---------------------------------------------------------------------------------------------------
cmp_rx_deglitcher: wf_rx_deglitcher
port map(
uclk_i => uclk_i,
nfip_rst_i => core_rst_i,
uclk_i => clk_40m_i,
nfip_rst_i => rst_i,
fd_rxd_a_i => fd_rxd_a_i,
-----------------------------------------------------------------
fd_rxd_filt_o => s_fd_rxd_filt,
fd_rxd_filt_edge_p_o => s_rxd_filt_edge_p,
fd_rxd_filt_f_edge_p_o => s_fd_rxd_filt_f_edge_p);
-----------------------------------------------------------------
s_fd_rxd_filt_r_edge_p <= s_rxd_filt_edge_p and (not s_fd_rxd_filt_f_edge_p);
---------------------------------------------------------------------------------------------------
-- Oscillator --
---------------------------------------------------------------------------------------------------
cmp_rx_osc: wf_rx_osc
port map(
uclk_i => uclk_i,
rate_i => rate_i,
nfip_rst_i => core_rst_i,
fd_rxd_edge_p_i => s_rxd_filt_edge_p,
rx_osc_rst_i => s_rx_osc_rst,
-----------------------------------------------------------------
rx_manch_clk_p_o => s_sample_manch_bit_p,
rx_bit_clk_p_o => s_sample_bit_p,
rx_signif_edge_window_o => s_signif_edge_window,
rx_adjac_bits_window_o => s_adjac_bits_window);
-----------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- Deserializer --
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
cmp_rx_deserializer: wf_rx_deserializer
port map(
uclk_i => uclk_i,
nfip_rst_i => core_rst_i,
uclk_i => clk_40m_i,
nfip_rst_i => rst_i,
rx_rst_i => rx_rst_i,
fd_rxd_f_edge_p_i => s_fd_rxd_filt_f_edge_p,
fd_rxd_r_edge_p_i => s_fd_rxd_filt_r_edge_p,
......@@ -219,35 +201,49 @@ begin
fss_received_p_o => rx_fss_received_p_o,
crc_wrong_p_o => rx_crc_wrong_p_o);
-----------------------------------------------------------------
rx_byte_ready_p_o <= rx_byte_ready_p;
rx_byte_o <= rx_byte;
rx_byte_ready_p_o <= rx_byte_ready_p;
rx_byte_o <= rx_byte;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
cmp_rx_osc: wf_rx_osc
port map(
uclk_i => clk_40m_i,
rate_i => speed_i,
nfip_rst_i => rst_i,
fd_rxd_edge_p_i => s_rxd_filt_edge_p,
rx_osc_rst_i => s_rx_osc_rst,
-----------------------------------------------------------------
rx_manch_clk_p_o => s_sample_manch_bit_p,
rx_bit_clk_p_o => s_sample_bit_p,
rx_signif_edge_window_o => s_signif_edge_window,
rx_adjac_bits_window_o => s_adjac_bits_window);
-----------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- bytes counter --
---------------------------------------------------------------------------------------------------
cmp_rx_bytes_cnt: wf_incr_counter
generic map(g_counter_lgth => 8)
generic map(g_counter_lgth => 9)
port map(
uclk_i => uclk_i,
uclk_i => clk_40m_i,
counter_reinit_i => bytes_c_rst,
counter_incr_i => rx_byte_ready_p,
counter_is_full_o => open,
-------------------------------------------------------
counter_o => rx_byte_index);
-------------------------------------------------------
bytes_c_rst <= '1' when (core_rst_i = '1' or rx_rst_i = '1') else '0';
rx_byte_index_o <= std_logic_vector(rx_byte_index);
bytes_c_rst <= '1' when (rst_i = '1' or rx_rst_i = '1') else '0';
rx_byte_index_o <= std_logic_vector(rx_byte_index);
---------------------------------------------------------------------------------------------------
-- combination of four received bytes to a 32-bit word --
-- combination of four retrieved bytes to a 32-bit word --
---------------------------------------------------------------------------------------------------
create_32bit_words: process (uclk_i)
create_32bit_words: process (clk_40m_i)
begin
if rising_edge (uclk_i) then
if core_rst_i = '1' or rx_rst_i = '1' then
if rising_edge (clk_40m_i) then
if rst_i = '1' or rx_rst_i = '1' then
byte0 <= (others => '0');
byte1 <= (others => '0');
byte2 <= (others => '0');
......@@ -255,7 +251,7 @@ begin
rx_ctrl_byte_o <= (others => '0');
else
if rx_byte_ready_p = '1' then
if std_logic_vector(rx_byte_index) = c_CTRL_BYTE_INDEX then
if rx_byte_index = resize(unsigned(c_CTRL_BYTE_INDEX),9) then
rx_ctrl_byte_o <= rx_byte;
else
byte0 <= rx_byte;
......@@ -274,29 +270,28 @@ begin
---------------------------------------------------------------------------------------------------
-- Storage of consumed bytes to the cons_frame regs --
---------------------------------------------------------------------------------------------------
-- Synchronous process Data_Transfer_To_Regs: transfer 32bit words to the cons_frame registers
-- transfer 32bit words to the cons_frame registers
delay: process (uclk_i)
delay: process (clk_40m_i)
begin
if rising_edge (uclk_i) then
if core_rst_i = '1' or rx_rst_i = '1' then
if rising_edge (clk_40m_i) then
if rst_i = '1' or rx_rst_i = '1' then
rx_byte_index_d1 <= (others =>'0'); -- needed for synching
else
if rx_byte_ready_p = '1' then
rx_byte_index_d1 <= rx_byte_index;
rx_byte_index_d1 <= rx_byte_index;
end if;
end if;
end if;
end process;
data_transfer_to_regs: process (uclk_i)
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
data_transfer_to_regs: process (clk_40m_i)
begin
if rising_edge (uclk_i) then
if core_rst_i = '1' or rx_rst_i = '1' then
word32_num <= 0;
rx_frame_o <= (others =>(others =>'0'));
if rising_edge (clk_40m_i) then
if rst_i = '1' or rx_rst_i = '1' then
word32_num <= 0;
rx_frame_o <= (others =>(others =>'0'));
else
if rx_byte_ready_p = '1' and (rx_byte_index_d1) > 0 and (rx_byte_index_d1) mod 4 = 0 then
word32_num <= word32_num + 1;
......
rtl/masterfip_tx.vhd
View file @ eaf3913c
......@@ -7,32 +7,39 @@
---------------------------------------------------------------------------------------------------
-- |
-- masterfip_tx |
-- masterfip_tx |
-- |
---------------------------------------------------------------------------------------------------
-- File masterfip_tx.vhd |
-- File masterfip_tx.vhd |
-- |
-- Description The unit groups the main actions that regard FIELDRIVE data transmission. |
-- It instantiates the units: |
-- It instantiates the units/processes: |
-- |
-- o wf_tx_serializer: that receives bytes from the wf_production, encodes them |
-- (Manchester 2), adds the FSS, FCS & FES fields and puts one |
-- by one bits to the FIELDRIVE output FD_TXD, following the |
-- synchronization signals from the wf_tx_osc unit. |
-- Also generates the nanoFIP output FD_TXENA. |
-- o wf_tx_serializer: that receives bytes from the WRNC trough the tx_frame , |
-- structure, encodes them (Manchester 2), adds the FSS, FCS, FES|
-- fields and puts one by one bits to the FIELDRIVE output FD_TXD|
-- following the synchronization signals from the wf_tx_osc unit.|
-- Also generates the output FD_TXENA. |
-- |
-- o wf_tx_osc : that generates the nanoFIP FIELDRIVE output FD_TXCK |
-- and the array of pulses tx_sched_p_buff, used for the |
-- synchronization of the wf_tx_serializer's actions. |
-- o wf_tx_osc : that generates the output FD_TXCK and the array of pulses |
-- tx_sched_p_buff, used for the synchronization of the |
-- wf_tx_serializer's actions. |
-- |
-- _____________________________________ |
-- | | |
-- | wf_Production | |
-- |_____________________________________| |
-- \/ |
-- o data_retrieval : that copies the bytes provided by the WRNC upon the activation|
-- of the signal tx_start |
-- |
-- WRNC |
-- ___________________________________________________________ |
-- | masterfip_tx | |
-- | | |
-- | _______________________________ | |
-- | | | | |
-- | | data_retrieval | | |
-- | |_______________________________| | |
-- | \/ \/ | |
-- | _________ _______________ | |
-- | | | | | | |
-- | | bytes_c | | select_byte | | |
-- | |_________| |_______________| | |
-- | \/ | |
-- | _____________ __________________________________ | |
-- | | | | | | |
-- | | wf_tx_osc | > | wf_tx_serializer | | |
......@@ -44,16 +51,14 @@
-- 0_____________________________FIELDBUS______________________________O |
-- |
-- |
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 11/01/2011 |
-- Authors Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 30/09/2015 |
-- Version v0.01 |
-- Depends on wf_reset_unit |
-- wf_production |
-- wf_engine_control |
-- Depends on |
-- |
---------------- |
-- Last changes |
-- 01/2011 EG v0.01 first version |
-- 09/2015 v0.01 EG First version |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
......@@ -81,7 +86,7 @@ use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific library
library work;
use work.masterFIP_pkg.all; -- definitions of types, constants, entities
use work.masterFIP_pkg.all; -- definitions of types, constants, entities
use work.wf_package.all;
......@@ -91,36 +96,34 @@ use work.wf_package.all;
entity masterfip_tx is port(
-- INPUTS
-- nanoFIP User Interface, General signal
uclk_i : in std_logic; -- 40 MHz clock
clk_40m_i : in std_logic; -- 40 MHz clock
rst_i : in std_logic; -- core rst, synched with clk_40m_i
-- nanoFIP WorldFIP Settings
rate_i : in std_logic_vector (1 downto 0); -- WorldFIP bit rate
speed_i : in std_logic_vector(1 downto 0); -- WorldFIP bit rate
tx_frame_i : in tx_frame_t; -- frame DATA bytes
-- structure with 66 words of 32-bit each
-- this represents the max length of a frame
-- upon tx_start_p_i only tx_bytes_num_i are read and transmitted
-- Signal from the wf_reset_unit
core_rst_i : in std_logic; -- nanoFIP internal reset
tx_bytes_num_i : in std_logic_vector (7 downto 0);
tx_bytes_num_i : in std_logic_vector(8 downto 0); -- number of bytes to be serialized
-- Signals from the wf_engine_control
tx_start_p_i : in std_logic; -- indication for the start of the production
tx_ctrl_byte_i : in std_logic_vector(7 downto 0); -- frame CTRL byte
-- structure with 32 words of 32-bit each
tx_frame_i : in tx_frame_t;
-- control byte
tx_ctrl_byte_i : in std_logic_vector (7 downto 0);
tx_start_p_i : in std_logic; -- indication for the start of the serialization
-- OUTPUTS
tx_byte_index_o : out std_logic_vector (7 downto 0);
-- Signal to the wf_engine_control
tx_completed_p_o : out std_logic; -- pulse upon termination of a transmission
-- (CRC & FES included)
tx_byte_index_o : out std_logic_vector(8 downto 0); -- index of the byte currently being serialized (0-262)
tx_end_p_o : out std_logic; -- pulse upon termination of a transmission (CRC & FES included)
-- nanoFIP FIELDRIVE outputs
tx_data_o : out std_logic; -- transmitter data
tx_enable_o : out std_logic; -- transmitter enable
tx_clk_o : out std_logic);-- line driver half bit clock
tx_data_o : out std_logic; -- FIELDRIVE transmitter data
tx_enable_o : out std_logic; -- FIELDRIVE transmitter enable
tx_clk_o : out std_logic); -- FIELDRIVE transmitter line driver half bit clock
end entity masterfip_tx;
......@@ -130,63 +133,65 @@ end entity masterfip_tx;
--=================================================================================================
architecture struc of masterfip_tx is
signal s_tx_clk_p_buff : std_logic_vector (c_TX_SCHED_BUFF_LGTH-1 downto 0);
-- frame bytes
signal prod_bytes_c : unsigned(8 downto 0);
signal ctrl_byte, tx_byte : std_logic_vector(7 downto 0);
signal prod_frame : tx_frame_t;
signal word32_num : integer range 0 to 31;
signal word32 : std_logic_vector(31 downto 0);
-- bytes counter
signal bytes_num : std_logic_vector(8 downto 0);
signal prod_data_lgth_match : std_logic;
signal last_data_byte_p, last_data_byte_p_d : std_logic;
-- wf_tx_osc
signal s_tx_clk_p_buff : std_logic_vector(c_TX_SCHED_BUFF_LGTH-1 downto 0);
signal s_tx_osc_rst_p : std_logic;
-- other signals
signal byte_request_accept_p : std_logic;
signal byte_request_accept_p_d1 : std_logic;
signal byte_request_accept_p_d2 : std_logic;
signal last_data_byte_p, last_data_byte_p_d : std_logic;
signal bytes_num : std_logic_vector (7 downto 0);
signal prod_bytes_c : unsigned (7 downto 0);
signal data_lgth : std_logic_vector (7 downto 0);
signal tx_byte_request_p : std_logic;
signal last_data_byte_p_tmp : std_logic;
signal byte_request_accept_p_tmp : std_logic;
signal data_lgth_match, tx_byte_request_p : std_logic;
signal prod_data_lgth_match : std_logic;
signal ctrl_byte, tx_byte : std_logic_vector (7 downto 0);
signal prod_frame : tx_frame_t;
signal word32_num : integer range 0 to 31;
signal word32 : std_logic_vector (31 downto 0);
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
---------------------------------------------------------------------------------------------------
-- Copy of the frame data --
---------------------------------------------------------------------------------------------------
-- Copying of the data so that they are kept static locally upon the tx_start_p_i.
copy_data: process (uclk_i)
-- Retrieval of the data bytes upon the tx_start_p_i.
-- All the frame bytes are copied to local registers; like this the frame data remain stable
-- until the next tx_start_p_i arrives.
data_retrieval: process (clk_40m_i)
begin
if rising_edge (uclk_i) then
if core_rst_i = '1' then
if rising_edge (clk_40m_i) then
if rst_i = '1' then
prod_frame <= ((others => (others=>'0')));
ctrl_byte <= (others=>'0');
bytes_num <= (others=>'0');
else
if tx_start_p_i = '1' then
prod_frame <= tx_frame_i;
ctrl_byte <= tx_ctrl_byte_i;
bytes_num <= tx_bytes_num_i;
prod_frame <= tx_frame_i; -- copying of the data bytes
ctrl_byte <= tx_ctrl_byte_i; -- copying of the ctrl byte
bytes_num <= tx_bytes_num_i; -- num of bytes to serialize from the prod_frame
end if;
end if;
end if;
end process;
---------------------------------------------------------------------------------------------------
-- Select the right byte --
-- Mux to select the right byte --
---------------------------------------------------------------------------------------------------
select_byte: process (uclk_i)
-- The process retrieves sequentially one by one the byte to be sent to the serializer.
select_byte: process (clk_40m_i)
begin
if rising_edge (uclk_i) then
if core_rst_i = '1' then
if rising_edge (clk_40m_i) then
if rst_i = '1' then
word32_num <= 0;
else
if prod_bytes_c mod 4 = 0 and tx_byte_request_p = '1' and prod_bytes_c > 0 then
......@@ -196,40 +201,76 @@ begin
end if;
end process;
word32 <= prod_frame(word32_num);
tx_byte <= ctrl_byte when prod_bytes_c = "00000000" else
word32(7 downto 0) when prod_bytes_c mod 4 = 1 else
word32(15 downto 8) when prod_bytes_c mod 4 = 2 else
word32(23 downto 16) when prod_bytes_c mod 4 = 3 else
word32(31 downto 24);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Instantiation of a wf_incr_counter for the counting of the number of the bytes that are
-- being produced. The same counter is used for the question (ID) and response (RP) frames that
-- are being produced.
-- being serialized.
cmp_tx_bytes_cnt: wf_incr_counter
generic map(g_counter_lgth => 8)
generic map(g_counter_lgth => 9)
port map(
uclk_i => uclk_i,
uclk_i => clk_40m_i,
counter_reinit_i => tx_start_p_i,
counter_incr_i => tx_byte_request_p,
counter_is_full_o => open,
-------------------------------------------------------
counter_o => prod_bytes_c);
-------------------------------------------------------
tx_byte_index_o <= std_logic_vector(prod_bytes_c);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
word32 <= prod_frame(word32_num);
tx_byte <= ctrl_byte when prod_bytes_c = "00000000" else
word32(7 downto 0) when prod_bytes_c mod 4 = 1 else
word32(15 downto 8) when prod_bytes_c mod 4 = 2 else
word32(23 downto 16) when prod_bytes_c mod 4 = 3 else
word32(31 downto 24);
---------------------------------------------------------------------------------------------------
-- Serializer as in the nanoFIP project --
---------------------------------------------------------------------------------------------------
cmp_tx_serializer: wf_tx_serializer
port map(
uclk_i => clk_40m_i,
nfip_rst_i => rst_i,
byte_i => tx_byte,
tx_start_p_i => tx_start_p_i,
byte_request_accept_p_i => byte_request_accept_p,
last_byte_p_i => last_data_byte_p,
tx_sched_p_buff_i => s_tx_clk_p_buff,
-----------------------------------------------
tx_byte_request_p_o => tx_byte_request_p,
tx_completed_p_o => tx_end_p_o,
tx_data_o => tx_data_o,
tx_osc_rst_p_o => s_tx_osc_rst_p,
tx_enable_o => tx_enable_o);
-----------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
cmp_tx_osc: wf_tx_osc
port map(
uclk_i => clk_40m_i,
rate_i => speed_i,
nfip_rst_i => rst_i,
tx_osc_rst_p_i => s_tx_osc_rst_p,
-----------------------------------------------
tx_clk_o => tx_clk_o,
tx_sched_p_buff_o => s_tx_clk_p_buff);
-----------------------------------------------
---------------------------------------------------------------------------------------------------
-- Other signals --
---------------------------------------------------------------------------------------------------
-- when s_prod_data_lgth bytes have been counted,the signal prod_data_lgth_match is activated
prod_data_lgth_match <= '1' when prod_bytes_c = unsigned(bytes_num) else '0';
tx_byte_index_o <= std_logic_vector(prod_bytes_c);
synch_signals: process (uclk_i)
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
synch_signals: process (clk_40m_i)
begin
if rising_edge (uclk_i) then
if core_rst_i = '1' then
if rising_edge (clk_40m_i) then
if rst_i = '1' then
last_data_byte_p <= '0'; -- indication of the last data byte (CRC, FES not included)
last_data_byte_p_d <= '0';
byte_request_accept_p_d1 <= '0';
......@@ -243,51 +284,11 @@ begin
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- --
byte_request_accept_p_tmp <= tx_byte_request_p or tx_start_p_i;
last_data_byte_p_tmp <= prod_data_lgth_match and tx_byte_request_p;
-- response to wf_tx_serializer request for a byte
byte_request_accept_p <= byte_request_accept_p_d2;
byte_request_accept_p <= byte_request_accept_p_d2; -- response to wf_tx_serializer request for a byte
---------------------------------------------------------------------------------------------------
-- Oscillator --
---------------------------------------------------------------------------------------------------
cmp_tx_osc: wf_tx_osc
port map(
uclk_i => uclk_i,
rate_i => rate_i,
nfip_rst_i => core_rst_i,
tx_osc_rst_p_i => s_tx_osc_rst_p,
-----------------------------------------------
tx_clk_o => tx_clk_o,
tx_sched_p_buff_o => s_tx_clk_p_buff);
-----------------------------------------------
---------------------------------------------------------------------------------------------------
-- Serializer --
---------------------------------------------------------------------------------------------------
cmp_tx_serializer: wf_tx_serializer
port map(
uclk_i => uclk_i,
nfip_rst_i => core_rst_i,
byte_i => tx_byte,
tx_start_p_i => tx_start_p_i,
byte_request_accept_p_i => byte_request_accept_p,
last_byte_p_i => last_data_byte_p,
tx_sched_p_buff_i => s_tx_clk_p_buff,
-----------------------------------------------
tx_byte_request_p_o => tx_byte_request_p,
tx_completed_p_o => tx_completed_p_o,
tx_data_o => tx_data_o,
tx_osc_rst_p_o => s_tx_osc_rst_p,
tx_enable_o => tx_enable_o);
-----------------------------------------------
end architecture struc;
--=================================================================================================
......
rtl/wbgen/fmc_masterfip_csr.wb
View file @ eaf3913c
......@@ -9,8 +9,8 @@ peripheral {
-- reset --
-------------------------------------------------------------------------------
reg {
name = "Reset Register";
prefix = "RST";
name = "rstn";
prefix = "rstn";
description = "software reset of the masterFIP core; active low; there is also an unlock word provided to prevent resetting the core by accidentally accessing this register.";
field {
......@@ -49,9 +49,9 @@ peripheral {
-- identification --
-------------------------------------------------------------------------------
reg {
name = "Identification Register";
name = "id";
description = "an identification value";
prefix = "ID";
prefix = "id";
field {
name = "an id value";
......@@ -64,40 +64,103 @@ peripheral {
-------------------------------------------------------------------------------
-- config from the host --
-- ADC power supplies --
-------------------------------------------------------------------------------
reg {
name = "config from host";
prefix = "CONFIG_HOST";
name = "adc power supplies";
prefix = "adc";
field {
name = "1v8_shdn_n";
prefix = "1v8_shdn_n";
description = "write 0: enable the adc_1v8_shdn_n_o\
write 1: disable the adc_1v8_shdn_n_o";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "m5v_shdn_n";
prefix = "m5v_shdn_n";
description = "write 0: enable the adc_m5v_shdn_n_o\
write 1: disable the adc_m5v_shdn_n_o";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "5v_en_n";
prefix = "5v_en_n";
description = "write 0: enable the adc_5v_en_n_o\
write 1: disable the adc_5v_en_n_o";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
-------------------------------------------------------------------------------
-- external synch --
-------------------------------------------------------------------------------
reg {
name = "ext sync";
prefix = "ext_sync";
field {
name = "speed";
description = "WorldFIP speed: 00: 31.25Kbps | 01: 1Mbps | 10: 2.5 Mbps | 11: not used";
prefix = "speed";
type = SLV;
size = 2;
name = "termination enable";
prefix = "term_en";
description = "write 0: disable 50ohms termination of the external sync pulse\
write 1: enable 50ohms termination of the external sync pulse";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "tranceiver direction";
prefix = "dir";
description = "write 0: normal operation\
write 1: test mode where a pulse from the FPGA can be output to the front panel LEMO connector";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "tranceiver output enable";
prefix = "oe";
description = "write 0: the external sync pulse arrives to the FPGA\
write 1: the external sync pulse does not arrive to the FPGA";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "termination enable on the external synch input";
description = "write 0: enable 50ohms termination on the external synch input\
write 1: disable 50ohms termination on the external synch input";
prefix = "ext_sync_term_en_n";
name = "test pulse";
prefix = "tst_n";
description = "emulate a pulse";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
};
-------------------------------------------------------------------------------
-- bus termination --
-------------------------------------------------------------------------------
reg {
name = "150ohms bus termination";
prefix = "bus_term_en_n";
field {
name = "station address";
description = "station address; normally set to 0x00";
prefix = "subs";
type = SLV;
size = 8;
align = 8;
name = "150ohms terination of the bus";
description = "write 0: enable 150ohms termination on the bus\
write 1: disable 150ohms termination on the bus";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
......@@ -105,42 +168,29 @@ peripheral {
-------------------------------------------------------------------------------
-- config from the fmc board --
-- speed configuration from the board --
-------------------------------------------------------------------------------
reg {
name = "config from fmc";
prefix = "CONFIG_FMC";
name = "speed";
prefix = "speed";
field {
name = "speed";
description = "WorldFIP speed: 00: 31.25Kbps | 01: 1Mbps | 10: 2.5 Mbps | 11: not used";
prefix = "speed";
description = "WorldFIP speed: 00: 31.25Kbps | 01: 1Mbps | 10: 2.5 Mbps | 11: 5 Mbps";
type = SLV;
size = 2;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "speed match";
description = "read 0: configuration from host and from fmc board mismatch\
read 1: configuration from host and from fmc board match";
prefix = "speed_ok";
type = BIT;
align = 31;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
-------------------------------------------------------------------------------
-- timing --
-- counters --
-------------------------------------------------------------------------------
reg {
name = "Macrocycle Length Register";
prefix = "MACROCYC";
name = "macrocycle lgth";
prefix = "macrocyc";
field {
name = "macrocycle lgth";
......@@ -162,7 +212,7 @@ peripheral {
};
reg {
name = "Turnaround Length Register";
name = "turnaround lgth";
prefix = "turnar";
field {
......@@ -185,7 +235,7 @@ peripheral {
};
reg {
name = "Silence Length Register";
name = "silence lgth";
prefix = "silen";
field {
......@@ -209,7 +259,7 @@ peripheral {
reg {
name = "Macrocycle Time Counter";
name = "macrocycle time cnt";
prefix = "macrocyc_time_cnt";
field {
......@@ -224,7 +274,7 @@ peripheral {
reg {
name = "Turnaround Time Counter";
name = "turnaround time cnt";
prefix = "turnar_time_cnt";
field {
......@@ -238,7 +288,7 @@ peripheral {
};
reg {
name = "Silence Time Counter";
name = "silence time cnt";
prefix = "silen_time_cnt";
field {
......@@ -252,7 +302,7 @@ peripheral {
};
reg {
name = "External Sync Timestamp";
name = "ext sync tstamp";
prefix = "ext_sync_tstamp";
field {
......@@ -265,12 +315,13 @@ peripheral {
};
};
-------------------------------------------------------------------------------
-- serializer ctrl --
-------------------------------------------------------------------------------
reg {
name = "TC Control Register";
prefix = "TX_CTRL";
name = "tx ctrl";
prefix = "tx_ctrl";
field {
name = "tx rst";
......@@ -308,17 +359,28 @@ peripheral {
-- serializer stat --
-------------------------------------------------------------------------------
reg {
name = "TX Status Register";
prefix = "TX_STATUS";
name = "tx status";
prefix = "tx_stat";
field {
name = "tx stopped";
name = "tx ended";
description = "indication that the serializer finished the delivery of a frame";
prefix = "stop";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "tx current byte";
description = "index of the byte currently being serialized";
prefix = "byte_index";
type = SLV;
size = 9; -- max WorldFIP frame size = 263 bytes (without preamble, crc, postamble)
align = 8;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
......@@ -326,8 +388,8 @@ peripheral {
-- fieldrive status signals --
-------------------------------------------------------------------------------
reg {
name = "FielDrive Status Register";
prefix = "FD_STATUS";
name = "fieldrive status";
prefix = "fd";
field {
name = "fd watchdog";
......@@ -351,8 +413,8 @@ peripheral {
-- deserializer ctrl --
-------------------------------------------------------------------------------
reg {
name = "RX Control";
prefix = "RX_CTRL";
name = "rx ctrl";
prefix = "rx_ctrl";
description = "active high reset of the deserializer";
field {
......@@ -371,8 +433,8 @@ peripheral {
-- deserializer stat --
-------------------------------------------------------------------------------
reg {
name = "RX Status";
prefix = "RX_STATUS";
name = "rx status";
prefix = "rx_stat";
field {
name = "rx preamble detected";
......@@ -424,16 +486,16 @@ peripheral {
};
-------------------------------------------------------------------------------
-- wannabe rx data --
-- rx data bytes --
-------------------------------------------------------------------------------
reg {
name = "RX Control Byte";
prefix = "RX_DATA_CTRL";
name = "rx data ctrl byte";
prefix = "rx_data_ctrl";
description = "contains the 8-bits of the control field of a received frame";
field {
name = "rx ctrl byte";
name = "rx data ctrl byte";
description = "contains the 8-bits of the control field of a received frame";
type = SLV;
size = 8;
......@@ -621,6 +683,7 @@ peripheral {
access_dev = WRITE_ONLY;
};
};
reg {
name = "rx data reg13";
prefix = "rx_data_reg13";
......@@ -635,6 +698,7 @@ peripheral {
access_dev = WRITE_ONLY;
};
};
reg {
name = "rx data reg14";
prefix = "rx_data_reg14";
......@@ -679,6 +743,7 @@ peripheral {
access_dev = WRITE_ONLY;
};
};
reg {
name = "rx data reg17";
prefix = "rx_data_reg17";
......@@ -693,6 +758,7 @@ peripheral {
access_dev = WRITE_ONLY;
};
};
reg {
name = "rx data reg18";
prefix = "rx_data_reg18";
......@@ -707,6 +773,7 @@ peripheral {
access_dev = WRITE_ONLY;
};
};
reg {
name = "rx data reg19";
prefix = "rx_data_reg19";
......@@ -721,6 +788,7 @@ peripheral {
access_dev = WRITE_ONLY;
};
};
reg {
name = "rx data reg20";
prefix = "rx_data_reg20";
......@@ -825,6 +893,7 @@ peripheral {
access_dev = WRITE_ONLY;
};
};
reg {
name = "rx data reg27";
prefix = "rx_data_reg27";
......@@ -899,6 +968,7 @@ peripheral {
access_dev = WRITE_ONLY;
};
};
reg {
name = "rx data reg32";
prefix = "rx_data_reg32";
......@@ -914,313 +984,1065 @@ peripheral {
};
};
-------------------------------------------------------------------------------
-- wannabe tx data --
-------------------------------------------------------------------------------
reg {
name = "TX Control Byte";
prefix = "tx_data_ctrl";
description = "contains the 8-bits of the control field of a frame to transmit";
field {
name = "tx ctrl byte";
description = "contains the 8-bits of the control field of a frame to transmit";
type = SLV;
size = 8;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx data reg1";
prefix = "tx_data_reg1";
name = "rx data reg33";
prefix = "rx_data_reg33";
description = "32 bits of the received frame";
field {
name = "reg1";
description = "1st 32-bit word";
name = "reg 33";
description = "33rd 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "tx data reg2";
prefix = "tx_data_reg2";
name = "rx data reg34";
prefix = "rx_data_reg34";
description = "32 bits of the received frame";
field {
name = "reg2";
description = "2nd 32-bit word";
name = "reg34";
description = "34th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "tx data reg3";
prefix = "tx_data_reg3";
name = "rx data reg35";
prefix = "rx_data_reg35";
description = "32 bits of the received frame";
field {
name = "reg3";
description = "3rd 32-bit word";
name = "reg35";
description = "35th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "tx data reg4";
prefix = "tx_data_reg4";
name = "rx data reg36";
prefix = "rx_data_reg36";
description = "32 bits of the received frame";
field {
name = "reg4";
description = "4th 32-bit word";
name = "reg36";
description = "36th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "tx data reg5";
prefix = "tx_data_reg5";
name = "rx data reg37";
prefix = "rx_data_reg37";
description = "32 bits of the received frame";
field {
name = "reg5";
description = "5th 32-bit word";
name = "reg37";
description = "37th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "tx data reg6";
prefix = "tx_data_reg6";
name = "rx data reg38";
prefix = "rx_data_reg38";
description = "32 bits of the received frame";
field {
name = "reg6";
description = "6th 32-bit word";
name = "reg38";
description = "38th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "tx data reg7";
prefix = "tx_data_reg7";
name = "rx data reg39";
prefix = "rx_data_reg39";
description = "32 bits of the received frame";
field {
name = "reg7";
description = "7th 32-bit word";
name = "reg39";
description = "39th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "tx data reg8";
prefix = "tx_data_reg8";
name = "rx data reg40";
prefix = "rx_data_reg40";
description = "32 bits of the received frame";
field {
name = "reg8";
description = "8th 32-bit word";
name = "reg40";
description = "40th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "tx data reg9";
prefix = "tx_data_reg9";
name = "rx data reg41";
prefix = "rx_data_reg41";
description = "32 bits of the received frame";
field {
name = "reg9";
description = "9th 32-bit word";
name = "reg41";
description = "41th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "tx data reg10";
prefix = "tx_data_reg10";
name = "rx data reg42";
prefix = "rx_data_reg42";
description = "32 bits of the received frame";
field {
name = "reg10";
description = "10th 32-bit word";
name = "reg42";
description = "42nd 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "tx data reg11";
prefix = "tx_data_reg11";
name = "rx data reg43";
prefix = "rx_data_reg43";
description = "32 bits of the received frame";
field {
name = "reg11";
description = "11th 32-bit word";
name = "reg43";
description = "43rd 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "tx data reg12";
prefix = "tx_data_reg12";
name = "rx data reg44";
prefix = "rx_data_reg44";
description = "32 bits of the received frame";
field {
name = "reg12";
description = "12th 32-bit word";
name = "reg44";
description = "44th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
};
reg {
name = "tx data reg13";
prefix = "tx_data_reg13";
name = "rx data reg45";
prefix = "rx_data_reg45";
description = "32 bits of the received frame";
field {
name = "reg13";
description = "13th 32-bit word";
name = "reg45";
description = "45th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
};
reg {
name = "tx data reg14";
prefix = "tx_data_reg14";
name = "rx data reg46";
prefix = "rx_data_reg46";
description = "32 bits of the received frame";
field {
name = "reg14";
description = "14th 32-bit word";
name = "reg46";
description = "46th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "tx data reg15";
prefix = "tx_data_reg15";
name = "rx data reg47";
prefix = "rx_data_reg47";
description = "32 bits of the received frame";
field {
name = "reg15";
description = "15th 32-bit word";
name = "reg47";
description = "47th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "tx data reg16";
prefix = "tx_data_reg16";
name = "rx data reg48";
prefix = "rx_data_reg48";
description = "32 bits of the received frame";
field {
name = "reg16";
description = "16th 32-bit word";
name = "reg48";
description = "48th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
};
reg {
name = "tx data reg17";
prefix = "tx_data_reg17";
name = "rx data reg49";
prefix = "rx_data_reg49";
description = "32 bits of the received frame";
field {
name = "reg17";
description = "17th 32-bit word";
name = "reg49";
description = "49th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
};
reg {
name = "tx data reg18";
prefix = "tx_data_reg18";
name = "rx data reg50";
prefix = "rx_data_reg50";
description = "32 bits of the received frame";
field {
name = "reg18";
description = "18th 32-bit word";
name = "reg50";
description = "50th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
};
reg {
name = "tx data reg19";
prefix = "tx_data_reg19";
name = "rx data reg51";
prefix = "rx_data_reg51";
description = "32 bits of the received frame";
field {
name = "reg19";
description = "19th 32-bit word";
name = "reg51";
description = "51st 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "rx data reg52";
prefix = "rx_data_reg52";
description = "32 bits of the received frame";
field {
name = "reg52";
description = "52nd 32-bit word";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "rx data reg53";
prefix = "rx_data_reg53";
description = "32 bits of the received frame";
field {
name = "reg53";
description = "53rd 32-bit word";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "rx data reg54";
prefix = "rx_data_reg54";
description = "32 bits of the received frame";
field {
name = "reg54";
description = "54th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "rx data reg55";
prefix = "rx_data_reg55";
description = "32 bits of the received frame";
field {
name = "reg55";
description = "55th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "rx data reg56";
prefix = "rx_data_reg56";
description = "32 bits of the received frame";
field {
name = "reg56";
description = "56th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "rx data reg57";
prefix = "rx_data_reg57";
description = "32 bits of the received frame";
field {
name = "reg57";
description = "57th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "rx data reg58";
prefix = "rx_data_reg58";
description = "32 bits of the received frame";
field {
name = "reg58";
description = "58th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "rx data reg59";
prefix = "rx_data_reg59";
description = "32 bits of the received frame";
field {
name = "reg59";
description = "59th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "rx data reg60";
prefix = "rx_data_reg60";
description = "32 bits of the received frame";
field {
name = "reg60";
description = "60th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "rx data reg61";
prefix = "rx_data_reg61";
description = "32 bits of the received frame";
field {
name = "reg61";
description = "61st 32-bit word";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "rx data reg62";
prefix = "rx_data_reg62";
description = "32 bits of the received frame";
field {
name = "reg62";
description = "62nd 32-bit word";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "rx data reg63";
prefix = "rx_data_reg63";
description = "32 bits of the received frame";
field {
name = "reg63";
description = "63rd 32-bit word";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "rx data reg64";
prefix = "rx_data_reg64";
description = "32 bits of the received frame";
field {
name = "reg64";
description = "64th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "rx data reg65";
prefix = "rx_data_reg65";
description = "32 bits of the received frame";
field {
name = "reg65";
description = "65th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "rx data reg66";
prefix = "rx_data_reg66";
description = "32 bits of the received frame";
field {
name = "reg66";
description = "66th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
-------------------------------------------------------------------------------
-- tx data --
-------------------------------------------------------------------------------
reg {
name = "tx ctrl byte";
prefix = "tx_data_ctrl";
description = "contains the 8-bits of the control field of a frame to transmit";
field {
name = "tx ctrl byte";
description = "contains the 8-bits of the control field of a frame to transmit";
type = SLV;
size = 8;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx data reg1";
prefix = "tx_data_reg1";
description = "32 bits of the received frame";
field {
name = "reg1";
description = "1st 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx data reg2";
prefix = "tx_data_reg2";
description = "32 bits of the received frame";
field {
name = "reg2";
description = "2nd 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx data reg3";
prefix = "tx_data_reg3";
description = "32 bits of the received frame";
field {
name = "reg3";
description = "3rd 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx data reg4";
prefix = "tx_data_reg4";
description = "32 bits of the received frame";
field {
name = "reg4";
description = "4th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx data reg5";
prefix = "tx_data_reg5";
description = "32 bits of the received frame";
field {
name = "reg5";
description = "5th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx data reg6";
prefix = "tx_data_reg6";
description = "32 bits of the received frame";
field {
name = "reg6";
description = "6th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx data reg7";
prefix = "tx_data_reg7";
description = "32 bits of the received frame";
field {
name = "reg7";
description = "7th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx data reg8";
prefix = "tx_data_reg8";
description = "32 bits of the received frame";
field {
name = "reg8";
description = "8th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx data reg9";
prefix = "tx_data_reg9";
description = "32 bits of the received frame";
field {
name = "reg9";
description = "9th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx data reg10";
prefix = "tx_data_reg10";
description = "32 bits of the received frame";
field {
name = "reg10";
description = "10th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx data reg11";
prefix = "tx_data_reg11";
description = "32 bits of the received frame";
field {
name = "reg11";
description = "11th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx data reg12";
prefix = "tx_data_reg12";
description = "32 bits of the received frame";
field {
name = "reg12";
description = "12th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx data reg13";
prefix = "tx_data_reg13";
description = "32 bits of the received frame";
field {
name = "reg13";
description = "13th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx data reg14";
prefix = "tx_data_reg14";
description = "32 bits of the received frame";
field {
name = "reg14";
description = "14th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx data reg15";
prefix = "tx_data_reg15";
description = "32 bits of the received frame";
field {
name = "reg15";
description = "15th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx data reg16";
prefix = "tx_data_reg16";
description = "32 bits of the received frame";
field {
name = "reg16";
description = "16th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx data reg17";
prefix = "tx_data_reg17";
description = "32 bits of the received frame";
field {
name = "reg17";
description = "17th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx data reg18";
prefix = "tx_data_reg18";
description = "32 bits of the received frame";
field {
name = "reg18";
description = "18th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx data reg19";
prefix = "tx_data_reg19";
description = "32 bits of the received frame";
field {
name = "reg19";
description = "19th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx data reg20";
prefix = "tx_data_reg20";
description = "32 bits of the received frame";
field {
name = "reg20";
description = "20th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx data reg21";
prefix = "tx_data_reg21";
description = "32 bits of the received frame";
field {
name = "reg21";
description = "21th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx data reg22";
prefix = "tx_data_reg22";
description = "32 bits of the received frame";
field {
name = "reg22";
description = "22th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx data reg23";
prefix = "tx_data_reg23";
description = "32 bits of the received frame";
field {
name = "reg23";
description = "23th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx data reg24";
prefix = "tx_data_reg24";
description = "32 bits of the received frame";
field {
name = "reg24";
description = "24th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx data reg25";
prefix = "tx_data_reg25";
description = "32 bits of the received frame";
field {
name = "reg25";
description = "25th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx data reg26";
prefix = "tx_data_reg26";
description = "32 bits of the received frame";
field {
name = "reg26";
description = "26th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx data reg27";
prefix = "tx_data_reg27";
description = "32 bits of the received frame";
field {
name = "reg27";
description = "27th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx data reg28";
prefix = "tx_data_reg28";
description = "32 bits of the received frame";
field {
name = "reg28";
description = "28th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx data reg29";
prefix = "tx_data_reg29";
description = "32 bits of the received frame";
field {
name = "reg29";
description = "29th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx data reg30";
prefix = "tx_data_reg30";
description = "32 bits of the received frame";
field {
name = "reg30";
description = "30th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx data reg31";
prefix = "tx_data_reg31";
description = "32 bits of the received frame";
field {
name = "reg31";
description = "31th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx data reg32";
prefix = "tx_data_reg32";
description = "32 bits of the received frame";
field {
name = "reg32";
description = "32th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx data reg33";
prefix = "tx_data_reg33";
description = "32 bits of the received frame";
field {
name = "reg 33";
description = "33rd 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx data reg34";
prefix = "tx_data_reg34";
description = "32 bits of the received frame";
field {
name = "reg34";
description = "34th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx data reg35";
prefix = "tx_data_reg35";
description = "32 bits of the received frame";
field {
name = "reg35";
description = "35th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx data reg20";
prefix = "tx_data_reg20";
name = "tx data reg36";
prefix = "tx_data_reg36";
description = "32 bits of the received frame";
field {
name = "reg20";
description = "20th 32-bit word";
name = "reg36";
description = "36th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
......@@ -1229,13 +2051,13 @@ peripheral {
};
reg {
name = "tx data reg21";
prefix = "tx_data_reg21";
name = "tx data reg37";
prefix = "tx_data_reg37";
description = "32 bits of the received frame";
field {
name = "reg21";
description = "21th 32-bit word";
name = "reg37";
description = "37th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
......@@ -1244,43 +2066,283 @@ peripheral {
};
reg {
name = "tx data reg22";
prefix = "tx_data_reg22";
name = "tx data reg38";
prefix = "tx_data_reg38";
description = "32 bits of the received frame";
field {
name = "reg22";
description = "22th 32-bit word";
name = "reg38";
description = "38th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx data reg39";
prefix = "tx_data_reg39";
description = "32 bits of the received frame";
field {
name = "reg39";
description = "39th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx data reg23";
prefix = "tx_data_reg23";
name = "tx data reg40";
prefix = "tx_data_reg40";
description = "32 bits of the received frame";
field {
name = "reg23";
description = "23th 32-bit word";
name = "reg40";
description = "40th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx data reg41";
prefix = "tx_data_reg41";
description = "32 bits of the received frame";
field {
name = "reg41";
description = "41th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx data reg42";
prefix = "tx_data_reg42";
description = "32 bits of the received frame";
field {
name = "reg42";
description = "42nd 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx data reg43";
prefix = "tx_data_reg43";
description = "32 bits of the received frame";
field {
name = "reg43";
description = "43rd 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx data reg44";
prefix = "tx_data_reg44";
description = "32 bits of the received frame";
field {
name = "reg44";
description = "44th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx data reg24";
prefix = "tx_data_reg24";
name = "tx data reg45";
prefix = "tx_data_reg45";
description = "32 bits of the received frame";
field {
name = "reg24";
description = "24th 32-bit word";
name = "reg45";
description = "45th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx data reg46";
prefix = "tx_data_reg46";
description = "32 bits of the received frame";
field {
name = "reg46";
description = "46th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx data reg47";
prefix = "tx_data_reg47";
description = "32 bits of the received frame";
field {
name = "reg47";
description = "47th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx data reg48";
prefix = "tx_data_reg48";
description = "32 bits of the received frame";
field {
name = "reg48";
description = "48th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx data reg49";
prefix = "tx_data_reg49";
description = "32 bits of the received frame";
field {
name = "reg49";
description = "49th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx data reg50";
prefix = "tx_data_reg50";
description = "32 bits of the received frame";
field {
name = "reg50";
description = "50th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx data reg51";
prefix = "tx_data_reg51";
description = "32 bits of the received frame";
field {
name = "reg51";
description = "51st 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx data reg52";
prefix = "tx_data_reg52";
description = "32 bits of the received frame";
field {
name = "reg52";
description = "52nd 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx data reg53";
prefix = "tx_data_reg53";
description = "32 bits of the received frame";
field {
name = "reg53";
description = "53rd 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx data reg54";
prefix = "tx_data_reg54";
description = "32 bits of the received frame";
field {
name = "reg54";
description = "54th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx data reg55";
prefix = "tx_data_reg55";
description = "32 bits of the received frame";
field {
name = "reg55";
description = "55th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx data reg56";
prefix = "tx_data_reg56";
description = "32 bits of the received frame";
field {
name = "reg56";
description = "56th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
......@@ -1289,13 +2351,13 @@ peripheral {
};
reg {
name = "tx data reg25";
prefix = "tx_data_reg25";
name = "tx data reg57";
prefix = "tx_data_reg57";
description = "32 bits of the received frame";
field {
name = "reg25";
description = "25th 32-bit word";
name = "reg57";
description = "57th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
......@@ -1304,27 +2366,28 @@ peripheral {
};
reg {
name = "tx data reg26";
prefix = "tx_data_reg26";
name = "tx data reg58";
prefix = "tx_data_reg58";
description = "32 bits of the received frame";
field {
name = "reg26";
description = "26th 32-bit word";
name = "reg58";
description = "58th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx data reg27";
prefix = "tx_data_reg27";
name = "tx data reg59";
prefix = "tx_data_reg59";
description = "32 bits of the received frame";
field {
name = "reg27";
description = "27th 32-bit word";
name = "reg59";
description = "59th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
......@@ -1333,13 +2396,13 @@ peripheral {
};
reg {
name = "tx data reg28";
prefix = "tx_data_reg28";
name = "tx data reg60";
prefix = "tx_data_reg60";
description = "32 bits of the received frame";
field {
name = "reg28";
description = "28th 32-bit word";
name = "reg60";
description = "60th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
......@@ -1348,13 +2411,13 @@ peripheral {
};
reg {
name = "tx data reg29";
prefix = "tx_data_reg29";
name = "tx data reg61";
prefix = "tx_data_reg61";
description = "32 bits of the received frame";
field {
name = "reg29";
description = "29th 32-bit word";
name = "reg61";
description = "61st 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
......@@ -1363,13 +2426,13 @@ peripheral {
};
reg {
name = "tx data reg30";
prefix = "tx_data_reg30";
name = "tx data reg62";
prefix = "tx_data_reg62";
description = "32 bits of the received frame";
field {
name = "reg30";
description = "30th 32-bit word";
name = "reg62";
description = "62nd 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
......@@ -1378,33 +2441,63 @@ peripheral {
};
reg {
name = "tx data reg31";
prefix = "tx_data_reg31";
name = "tx data reg63";
prefix = "tx_data_reg63";
description = "32 bits of the received frame";
field {
name = "reg31";
description = "31th 32-bit word";
name = "reg63";
description = "63rd 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx data reg32";
prefix = "tx_data_reg32";
name = "tx data reg64";
prefix = "tx_data_reg64";
description = "32 bits of the received frame";
field {
name = "reg32";
description = "32th 32-bit word";
name = "reg64";
description = "64th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx data reg65";
prefix = "tx_data_reg65";
description = "32 bits of the received frame";
field {
name = "reg65";
description = "65th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx data reg66";
prefix = "tx_data_reg66";
description = "32 bits of the received frame";
field {
name = "reg66";
description = "66th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
};
\ No newline at end of file
sim/spec/data_vectors/masterFIP_test.vec
View file @ eaf3913c
......@@ -29,120 +29,122 @@ wait %d900
-------------------------------------------------------------------------------
--------------- RESETS ---------------
-- reset inactive
wr 0000000000050000 F CAFE0003
wr 0000000000030000 F CAFE0003
wait %d20
-- reset active
wr 0000000000050000 F CAFE0000
wr 0000000000030000 F CAFE0000
wait %d20
-- reset inactive
wr 0000000000050000 F CAFE0003
wr 0000000000030000 F CAFE0003
wait %d20
----- CHECK COUNTERS FUNCTINALITY -----
-- macrocycle cnt start
wr 0000000000030018 F 80007D00
wait %d20
-- turnar counter top
wr 0000000000050014 F 000007D0
wr 000000000003001C F 000007D0
wait %d20
-- silen counter top
wr 0000000000050018 F 00000FA0
wr 0000000000030020 F 00000FA0
wait %d20
-- macrocycle cnt start
wr 0000000000050010 F 80007D00
wait %d20
--------------- ID_DAT ---------------
tx_rst
wr 000000000005002C F 00000001
wr 0000000000030034 F 00000001
wait %d10
wr 000000000005002C F 00000000
wr 0000000000030034 F 00000000
wait %d20
-- control byte of id_dat
wr 00000000000500C4 F 00000003
wr 0000000000030154 F 00000003
wait %d20
-- data bytes varid = 0503 for agent to consume
wr 00000000000500C8 F 00000305
wr 0000000000030158 F 00000305
wait %d20
-- tx_start
wr 000000000005002C F 00000202
wr 0000000000030034 F 00000202
wait %d20000
--------------- RP_DAT ---------------
tx_rst
wr 000000000005002C F 00000001
wr 0000000000030034 F 00000001
wait %d10
wr 000000000005002C F 00000000
wr 0000000000030034 F 00000000
wait %d20
-- control byte of rp_dat
wr 00000000000500c4 F 00000002
wr 0000000000030154 F 00000002
wait %d20
-- data bytes
wr 00000000000500c8 F BBAA0340
wr 0000000000030158 F BBAA0340
wait %d20
wr 00000000000500cc F EEDDCC05
wr 000000000003015c F EEDDCC05
wait %d20
wr 00000000000500d0 F 0A090807
wr 0000000000030160 F 0A090807
wait %d20
wr 00000000000500D4 F 0E0D0C0B
wr 0000000000030164 F 0E0D0C0B
wait %d20
wr 00000000000500D8 F 06060605
wr 0000000000030168 F 06060605
wait %d20
-- tx_start
wr 000000000005002C F 00000502
wr 0000000000030034 F 00000502
wait %d40000
--------------- ID_DAT ---------------
tx_rst
wr 000000000005002C F 00000001
wr 0000000000030034 F 00000001
wait %d10
wr 000000000005002C F 00000000
wr 0000000000030034 F 00000000
wait %d20
-- control byte of id_dat
wr 00000000000500c4 F 00000003
wr 0000000000030154 F 00000003
wait %d20
-- data bytes varid = 1403 for agent to send identification
wr 00000000000500c8 F 00000314
wr 0000000000030158 F 00000314
wait %d20
-- tx_start
wr 000000000005002C F 00000202
wr 0000000000030034 F 00000202
wait %d20
-- deactivate tx_start
wr 000000000005002C F 00000000
wr 0000000000030034 F 00000000
-- release rx_rst
wr 0000000000050038 F 00000000
wr 0000000000030040 F 00000000
wait %d40000
-- read received data
rd 0000000000050040 F 00000002
rd 0000000000030048 F 00000002
wait %d20
rd 0000000000050044 F 00000050
rd 000000000003004c F 00000050
--------------- RP_FIN ---------------
-- control byte of rp_fin
wr 00000000000500C4 F 00000040
wr 0000000000030154 F 00000040
wait %d20
-- rx_rst
wr 0000000000050038 F 00000001
wr 0000000000030040 F 00000001
wait %d20
-- tx_start
wr 000000000005002C F 00000002
wr 0000000000030034 F 00000002
wait %d20000
\ No newline at end of file
sim/spec/testbench/tb_masterFIP.vhd
View file @ eaf3913c
......@@ -59,6 +59,10 @@ architecture behavioral of tb_masterFIP is
tx_error_i : in std_logic; -- Transmit Error
irq_p_o : out std_logic; -- Interrupt request pulse to GN4124 GPIO
ext_sync_i : in std_logic;
speed_b0_i : in std_logic;
speed_b1_i : in std_logic;
fd_rxcdn_i : in std_logic;
fd_rxd_i : in std_logic;
fd_txer_i : in std_logic;
......@@ -314,6 +318,8 @@ signal spec_led_red : std_logic;
signal consu_data : std_logic_vector (15 downto 0);
signal nanoFIP_rxcdn, nanoFIP_txena, nanoFIP_txck, nanoFIP_rstno ,nanoFIP_wdgn : std_logic;
signal nanoFIP_clk : std_logic:='0';
signal ext_sync : std_logic := '0';
-- GN4124 interface
signal rst_n : std_logic;
......@@ -388,7 +394,11 @@ begin
l_wr_rdy_i => l_wr_rdy,
p_rd_d_rdy_i => p_rd_d_rdy,
tx_error_i => tx_error,
irq_p_o => irq_p,
ext_sync_i => ext_sync,
speed_b0_i => '0',
speed_b1_i => '1',
fd_rxcdn_i => fd_rxcdn,
fd_rxd_i => fd_rxd,
......@@ -426,7 +436,7 @@ begin
fd_txena_o => nanoFIP_txena,
nostat_i => '1',
rstin_i => not (rst_n),
rstin_i => (rst_n),--was not
rstpon_i => '1',
slone_i => '1',
uclk_i => nanoFIP_clk,
......@@ -596,6 +606,9 @@ begin
nanoFIP_clk <= not (nanoFIP_clk) after 1 ns;
wait for nanoFIP_clk_period/2;
end process;
ext_sync <= '1' after 8500 ns, '0' after 8580 ns;
rst_n <= RSTOUT18n;
GPIO(0) <= irq_p;
......
syn/spec/spec_masterFIP.xise
View file @ eaf3913c
This source diff could not be displayed because it is too large. You can view the blob instead.
syn/spec_wrnode/spec_masterfip_wrnode.xise
View file @ eaf3913c
......@@ -49,7 +49,7 @@
<property xil_pn:name="Change Device Speed To" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
......@@ -81,6 +81,7 @@
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
......@@ -346,9 +347,6 @@
<file xil_pn:name="../../top/spec_wrnode/spec_top.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/spec/ip_cores/l2p_fifo.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="Implementation" xil_pn:seqID="147"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_endpoint/endpoint_private_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
</file>
......@@ -359,7 +357,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wrc_core/wrc_periph.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="145"/>
<association xil_pn:name="Implementation" xil_pn:seqID="139"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
......@@ -368,7 +366,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/rtl/wrnc/mqueue/wrn_mqueue_wishbone_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="107"/>
<association xil_pn:name="Implementation" xil_pn:seqID="104"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
......@@ -380,7 +378,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/etherbone-core/hdl/eb_master_core/eb_master_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="184"/>
<association xil_pn:name="Implementation" xil_pn:seqID="180"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_eca/eca_flags.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
......@@ -389,7 +387,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../rtl/from_nanofip/wf_rx_osc.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="132"/>
<association xil_pn:name="Implementation" xil_pn:seqID="158"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/rtl/wrnc/cpu/wrn_cpu_iram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
......@@ -401,16 +399,16 @@
<association xil_pn:name="Implementation" xil_pn:seqID="33"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="151"/>
<association xil_pn:name="Implementation" xil_pn:seqID="144"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_fsm.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="99"/>
<association xil_pn:name="Implementation" xil_pn:seqID="98"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/p2l_des.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="175"/>
<association xil_pn:name="Implementation" xil_pn:seqID="171"/>
</file>
<file xil_pn:name="../../rtl/free_counter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
......@@ -419,13 +417,13 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_se.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="148"/>
<association xil_pn:name="Implementation" xil_pn:seqID="141"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_rx_crc_size_check.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="47"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_dma_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="179"/>
<association xil_pn:name="Implementation" xil_pn:seqID="175"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_rx_wb_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="40"/>
......@@ -437,13 +435,13 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_leds_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="88"/>
<association xil_pn:name="Implementation" xil_pn:seqID="87"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_arbiter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="180"/>
<association xil_pn:name="Implementation" xil_pn:seqID="176"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_mini_nic/minic_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="36"/>
......@@ -452,13 +450,13 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="121"/>
<association xil_pn:name="Implementation" xil_pn:seqID="118"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_decode32.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="178"/>
<association xil_pn:name="Implementation" xil_pn:seqID="174"/>
</file>
<file xil_pn:name="../../rtl/from_nanofip/wf_tx_serializer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="130"/>
<association xil_pn:name="Implementation" xil_pn:seqID="156"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="50"/>
......@@ -467,16 +465,16 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_wishbone_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="84"/>
<association xil_pn:name="Implementation" xil_pn:seqID="83"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_endpoint/endpoint_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="90"/>
<association xil_pn:name="Implementation" xil_pn:seqID="89"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_rx_buffer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="48"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_softpll_ng/spll_bangbang_pd.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="80"/>
<association xil_pn:name="Implementation" xil_pn:seqID="79"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_rx_oob_insert.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="45"/>
......@@ -488,7 +486,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../rtl/from_nanofip/wf_tx_osc.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="131"/>
<association xil_pn:name="Implementation" xil_pn:seqID="157"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/rtl/wrnc/mqueue/wrn_mqueue_irq_unit.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
......@@ -497,7 +495,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_dma_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="177"/>
<association xil_pn:name="Implementation" xil_pn:seqID="173"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_timer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
......@@ -506,10 +504,10 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/rtl/wrnc/mqueue/wrn_eb_cycle_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="76"/>
<association xil_pn:name="Implementation" xil_pn:seqID="75"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_mini_nic/minic_wb_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="83"/>
<association xil_pn:name="Implementation" xil_pn:seqID="82"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/timing/pulse_stamper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
......@@ -518,19 +516,19 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/rtl/wrnc/mqueue/wrn_mqueue_etherbone_output.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="109"/>
<association xil_pn:name="Implementation" xil_pn:seqID="106"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_clock_alignment_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="52"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="153"/>
<association xil_pn:name="Implementation" xil_pn:seqID="146"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/timing/pulse_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_endpoint/wr_endpoint.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="115"/>
<association xil_pn:name="Implementation" xil_pn:seqID="112"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_tx_pcs_16bit.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="38"/>
......@@ -545,22 +543,22 @@
<association xil_pn:name="Implementation" xil_pn:seqID="42"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_rx_path.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="87"/>
<association xil_pn:name="Implementation" xil_pn:seqID="86"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/rtl/wrnc/cpu/wrn_cpu_csr_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="78"/>
<association xil_pn:name="Implementation" xil_pn:seqID="77"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_pass_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="100"/>
<association xil_pn:name="Implementation" xil_pn:seqID="99"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/wr_gtp_phy_spartan6.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="191"/>
<association xil_pn:name="Implementation" xil_pn:seqID="189"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="60"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_diff.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="149"/>
<association xil_pn:name="Implementation" xil_pn:seqID="142"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/whiterabbitgtx_wrapper_gtx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
......@@ -569,7 +567,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="54"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="119"/>
<association xil_pn:name="Implementation" xil_pn:seqID="116"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtp_phase_align_virtex6.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
......@@ -584,22 +582,22 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_dacs/spec_serial_dac.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="171"/>
<association xil_pn:name="Implementation" xil_pn:seqID="166"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_narrow.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="123"/>
<association xil_pn:name="Implementation" xil_pn:seqID="120"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="94"/>
<association xil_pn:name="Implementation" xil_pn:seqID="93"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" xil_pn:type="FILE_VHDL">
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......@@ -617,7 +615,7 @@
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......@@ -629,7 +627,7 @@
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......@@ -638,7 +636,7 @@
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......@@ -647,40 +645,37 @@
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......@@ -698,7 +693,7 @@
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......@@ -710,10 +705,10 @@
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......@@ -722,37 +717,37 @@
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......@@ -761,16 +756,16 @@
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......@@ -779,7 +774,7 @@
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......@@ -788,16 +783,16 @@
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......@@ -812,7 +807,7 @@
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......@@ -824,34 +819,34 @@
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......@@ -860,10 +855,10 @@
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......@@ -872,7 +867,7 @@
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......@@ -887,10 +882,10 @@
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<association xil_pn:name="Implementation" xil_pn:seqID="135"/>
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<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
......@@ -899,16 +894,16 @@
<association xil_pn:name="Implementation" xil_pn:seqID="72"/>
</file>
<file xil_pn:name="../../rtl/fmc_masterfip_eic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="185"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/rtl/wrnc/mqueue/wrn_mqueue_host.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="138"/>
<association xil_pn:name="Implementation" xil_pn:seqID="132"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/common/gc_big_adder.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/timing/dmtd_phase_meas.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="92"/>
<association xil_pn:name="Implementation" xil_pn:seqID="91"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_tlu/tlu_fsm.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
......@@ -920,7 +915,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_timestamping_unit.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="86"/>
<association xil_pn:name="Implementation" xil_pn:seqID="85"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/rtl/wrnc/cpu/wrn_private_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
......@@ -950,7 +945,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/top/spec/node_template/spec_node_template.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="197"/>
<association xil_pn:name="Implementation" xil_pn:seqID="195"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/common/gc_dyn_glitch_filt.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
......@@ -965,7 +960,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="118"/>
<association xil_pn:name="Implementation" xil_pn:seqID="115"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_bridge/wb_i2c_bridge.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
......@@ -980,16 +975,16 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_clk_pll_s2_diff.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="174"/>
<association xil_pn:name="Implementation" xil_pn:seqID="169"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="95"/>
<association xil_pn:name="Implementation" xil_pn:seqID="94"/>
</file>
<file xil_pn:name="../../rtl/masterFIP_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="129"/>
<association xil_pn:name="Implementation" xil_pn:seqID="155"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_eca/eca_offset.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
......@@ -1007,7 +1002,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/wbmaster32.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="173"/>
<association xil_pn:name="Implementation" xil_pn:seqID="168"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_fsm.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
......@@ -1025,13 +1020,13 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/etherbone-core/hdl/eb_master_core/eb_master_wb_if.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="159"/>
<association xil_pn:name="Implementation" xil_pn:seqID="152"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_softpll_ng/spll_wb_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="79"/>
<association xil_pn:name="Implementation" xil_pn:seqID="78"/>
</file>
<file xil_pn:name="../../rtl/masterfip_rx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="163"/>
<association xil_pn:name="Implementation" xil_pn:seqID="182"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="24"/>
......@@ -1040,16 +1035,16 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtp_phase_align.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="168"/>
<association xil_pn:name="Implementation" xil_pn:seqID="163"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="157"/>
<association xil_pn:name="Implementation" xil_pn:seqID="150"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_pps_gen/pps_gen_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="82"/>
<association xil_pn:name="Implementation" xil_pn:seqID="81"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/etherbone-core/hdl/eb_master_core/eb_commit_len_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="128"/>
<association xil_pn:name="Implementation" xil_pn:seqID="125"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_si57x_interface/si570_if_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
......@@ -1058,7 +1053,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="64"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_pps_gen/xwr_pps_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="142"/>
<association xil_pn:name="Implementation" xil_pn:seqID="136"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="63"/>
......@@ -1070,13 +1065,13 @@
<association xil_pn:name="Implementation" xil_pn:seqID="51"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_1000basex_pcs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="89"/>
<association xil_pn:name="Implementation" xil_pn:seqID="88"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="195"/>
<association xil_pn:name="Implementation" xil_pn:seqID="193"/>
</file>
<file xil_pn:name="../../rtl/fmc_masterFIP_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="186"/>
<association xil_pn:name="Implementation" xil_pn:seqID="194"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_irq/irqm_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
......@@ -1088,10 +1083,10 @@
<association xil_pn:name="Implementation" xil_pn:seqID="44"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_widen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="122"/>
<association xil_pn:name="Implementation" xil_pn:seqID="119"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/whiterabbitgtp_wrapper_tile.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="167"/>
<association xil_pn:name="Implementation" xil_pn:seqID="162"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="69"/>
......@@ -1103,13 +1098,13 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_wbm_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="96"/>
<association xil_pn:name="Implementation" xil_pn:seqID="95"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/pulse_sync_rtl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="170"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/rtl/wrnc/cpu/wrn_cpu_lr_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="111"/>
<association xil_pn:name="Implementation" xil_pn:seqID="108"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_tbi_phy/wr_tbi_phy.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
......@@ -1118,7 +1113,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="58"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/rtl/wrnc/wr_node_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="166"/>
<association xil_pn:name="Implementation" xil_pn:seqID="161"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
......@@ -1133,7 +1128,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="34"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/etherbone-core/hdl/eb_master_core/eb_master_eth_tx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="160"/>
<association xil_pn:name="Implementation" xil_pn:seqID="153"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/timing/dmtd_with_deglitcher.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="55"/>
......@@ -1142,10 +1137,10 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="182"/>
<association xil_pn:name="Implementation" xil_pn:seqID="178"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/top/spec/node_template/spec_node_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="188"/>
<association xil_pn:name="Implementation" xil_pn:seqID="186"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_autonegotiation.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="53"/>
......@@ -1157,13 +1152,13 @@
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_rx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="126"/>
<association xil_pn:name="Implementation" xil_pn:seqID="123"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/fabric/xwb_fabric_source.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/rtl/wrnc/cpu/wrn_lm32_wrapper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="110"/>
<association xil_pn:name="Implementation" xil_pn:seqID="107"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/common/gc_reset.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
......@@ -1184,13 +1179,13 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wrc_core/wr_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="172"/>
<association xil_pn:name="Implementation" xil_pn:seqID="167"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_endpoint/xwr_endpoint.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="144"/>
<association xil_pn:name="Implementation" xil_pn:seqID="138"/>
</file>
<file xil_pn:name="../../rtl/from_nanofip/wf_decr_counter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="105"/>
<association xil_pn:name="Implementation" xil_pn:seqID="127"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/common/gc_extend_pulse.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="31"/>
......@@ -1202,7 +1197,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="62"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wrc_core/wrcore_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="117"/>
<association xil_pn:name="Implementation" xil_pn:seqID="114"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_softpll_ng/spll_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="35"/>
......@@ -1220,28 +1215,28 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../rtl/from_nanofip/wf_crc.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="106"/>
<association xil_pn:name="Implementation" xil_pn:seqID="128"/>
</file>
<file xil_pn:name="../../rtl/masterfip_tx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="162"/>
<association xil_pn:name="Implementation" xil_pn:seqID="181"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_mini_nic/xwr_mini_nic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="143"/>
<association xil_pn:name="Implementation" xil_pn:seqID="137"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/fabric/xwrf_mux.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="146"/>
<association xil_pn:name="Implementation" xil_pn:seqID="140"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="124"/>
<association xil_pn:name="Implementation" xil_pn:seqID="121"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/etherbone-core/hdl/eb_master_core/eb_framer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="161"/>
<association xil_pn:name="Implementation" xil_pn:seqID="154"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/common/gc_delay_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_softpll_ng/softpll_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="81"/>
<association xil_pn:name="Implementation" xil_pn:seqID="80"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
......@@ -1274,7 +1269,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../rtl/from_nanofip/wf_package.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="75"/>
<association xil_pn:name="Implementation" xil_pn:seqID="103"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="56"/>
......
top/spec/spec_masterFIP.ucf
View file @ eaf3913c
......@@ -67,6 +67,32 @@ NET "led_rx_err_n_o" IOSTANDARD = "LVCMOS25";
NET "led_rx_act_n_o" LOC = A20;
NET "led_rx_act_n_o" IOSTANDARD = "LVCMOS25";
NET "bus_term_en_n_o" LOC = Y13;
NET "bus_term_en_n_o" IOSTANDARD = "LVCMOS25";
NET "ext_sync_term_en_o" LOC = AB13;
NET "ext_sync_term_en_o" IOSTANDARD = "LVCMOS25";
NET "ext_sync_i" LOC = T8;
NET "ext_sync_i" IOSTANDARD = "LVCMOS25";
NET "ext_sync_tst_n_o" LOC = U8;
NET "ext_sync_tst_n_o" IOSTANDARD = "LVCMOS25";
NET "ext_sync_oe_o" LOC = W6;
NET "ext_sync_oe_o" IOSTANDARD = "LVCMOS25";
NET "ext_sync_dir_o" LOC = Y6;
NET "ext_sync_dir_o" IOSTANDARD = "LVCMOS25";
NET "adc_1v8_shdn_n_o" LOC = V17;
NET "adc_1v8_shdn_n_o" IOSTANDARD = "LVCMOS25";
NET "adc_m5v_shdn_n_o" LOC = W18;
NET "adc_m5v_shdn_n_o" IOSTANDARD = "LVCMOS25";
NET "adc_5v_en_n_o" LOC = R9;
NET "adc_5v_en_n_o" IOSTANDARD = "LVCMOS25";
#NET "mezz_onewire_b" LOC = "A19";
#NET "mezz_onewire_b" IOSTANDARD = "LVCMOS25";
......
top/spec/spec_masterFIP.vhd
View file @ eaf3913c
......@@ -147,6 +147,21 @@ entity spec_masterFIP is
-- Bus Speed
speed_b0_i : in std_logic;
speed_b1_i : in std_logic;
-- Bus termination
bus_term_en_n_o : out std_logic;
-- External synchronisation pulse transceiver
ext_sync_term_en_o : out std_logic;
ext_sync_dir_o : out std_logic;
ext_sync_oe_o : out std_logic;
ext_sync_tst_n_o : out std_logic;
ext_sync_i : in std_logic;
-- Power supplies for the ADC
adc_1v8_shdn_n_o : out std_logic;
adc_m5v_shdn_n_o : out std_logic;
adc_5v_en_n_o : out std_logic;
-- FielDrive
fd_rxcdn_i : in std_logic;
......@@ -184,11 +199,10 @@ architecture rtl of spec_masterFIP is
-- Note: All address in sdb and crossbar are BYTE addresses!
-- Master ports on the wishbone crossbar
constant c_NUM_WB_MASTERS : integer := 4;
constant c_NUM_WB_MASTERS : integer := 3;
constant c_WB_SLAVE_SPEC_ONEWIRE: integer := 0; -- Carrier onewire interface
constant c_WB_SLAVE_SPEC_INFO : integer := 1; -- Info on SPEC control and status registers
constant c_WB_SLAVE_VIC : integer := 2; -- Interrupt controller
constant c_WB_SLAVE_MASTERFIP : integer := 3; -- TDC core configuration
constant c_WB_SLAVE_MASTERFIP : integer := 2; -- TDC core configuration
-- SDB header address
constant c_SDB_ADDRESS : t_wishbone_address := x"00000000";
......@@ -197,21 +211,13 @@ architecture rtl of spec_masterFIP is
constant c_NUM_WB_SLAVES : integer := 1;
constant c_MASTER_GENNUM : integer := 0;
constant c_FMC_MASTERFIP_SDB_BRIDGE : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"0001FFFF", x"00000000");
constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(5 downto 0) :=
constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(4 downto 0) :=
(0 => f_sdb_embed_device (c_ONEWIRE_SDB_DEVICE, x"00010000"),
1 => f_sdb_embed_device (c_SPEC_INFO_SDB_DEVICE, x"00020000"),
2 => f_sdb_embed_device (c_xwb_vic_sdb, x"00030000"), -- c_xwb_vic_sdb described in the wishbone_pkg
3 => f_sdb_embed_bridge (c_FMC_MASTERFIP_SDB_BRIDGE, x"00040000"),
4 => f_sdb_embed_repo_url (c_sdb_repo_url),
5 => f_sdb_embed_synthesis (c_sdb_synthesis_info));
---------------------------------------------------------------------------------------------------
-- VIC CONSTANT --
---------------------------------------------------------------------------------------------------
constant c_VIC_VECTOR_TABLE : t_wishbone_address_array(0 to 0) := (0 => x"00052000");
2 => f_sdb_embed_device (c_MASTERFIP_SDB_DEVICE, x"00030000"),
3 => f_sdb_embed_repo_url (c_SDB_REPO_URL),
4 => f_sdb_embed_synthesis (c_SDB_SYNTHESIS_INFO));
---------------------------------------------------------------------------------------------------
......@@ -392,6 +398,9 @@ begin
csr_dat_i => cnx_slave_out(c_MASTER_GENNUM).dat,
csr_ack_i => cnx_slave_out(c_MASTER_GENNUM).ack,
csr_stall_i => cnx_slave_out(c_MASTER_GENNUM).stall,
csr_err_i => cnx_slave_out(c_MASTER_GENNUM).err,
csr_rty_i => cnx_slave_out(c_MASTER_GENNUM).rty,
csr_int_i => '0',
-- DMA: not used
dma_clk_i => clk_40m_sys,
dma_adr_o => open,
......@@ -400,7 +409,10 @@ begin
dma_sel_o => open,
dma_stb_o => open,
dma_we_o => open,
dma_err_i => '0',
dma_ack_i => '1',
dma_rty_i => '0',
dma_int_i => '0',
dma_dat_i => (others => '0'),
dma_stall_i => '0',
dma_reg_clk_i => clk_40m_sys,
......@@ -422,38 +434,50 @@ begin
---------------------------------------------------------------------------------------------------
-- masterFIP BOARD --
---------------------------------------------------------------------------------------------------
cmp_masterFIP_mezz : fmc_masterFIP_mezz
cmp_masterFIP_mezz : fmc_masterFIP_core
generic map
(g_span => g_span,
g_width => g_width,
values_for_simul => FALSE)
(g_span => 32,
g_width => 32,
values_for_simul => FALSE)
port map
(clk_sys_i => clk_40m_sys,
rst_sys_n_i => rst_sys_n,
fd_rxcdn_i => fd_rxcdn_i,
fd_rxd_i => fd_rxd_i,
fd_txer_i => fd_txer_i,
fd_wdgn_i => fd_wdgn_i,
fd_rstn_o => fd_rstn_o,
fd_txck_o => fd_txck_o,
fd_txd_o => fd_txd_o,
fd_txena_o => fd_txena,
speed_b0_i => speed_b0_i,
speed_b1_i => speed_b1_i,
(clk_i => clk_40m_sys,
rst_i => rst_sys,
-- FielDrive
fd_rxcdn_i => fd_rxcdn_i,
fd_rxd_i => fd_rxd_i,
fd_txer_i => fd_txer_i,
fd_wdgn_i => fd_wdgn_i,
fd_rstn_o => fd_rstn_o,
fd_txck_o => fd_txck_o,
fd_txd_o => fd_txd_o,
fd_txena_o => fd_txena,
-- Bus bit rate
speed_b0_i => speed_b0_i,
speed_b1_i => speed_b1_i,
-- Bus termination
bus_term_en_n_o => bus_term_en_n_o,
-- External synchronisation pulse transceiver
ext_sync_term_en_o => ext_sync_term_en_o,
ext_sync_dir_o => ext_sync_dir_o,
ext_sync_oe_o => ext_sync_oe_o,
ext_sync_tst_n_o => ext_sync_tst_n_o,
ext_sync_i => ext_sync_i,
-- Power supplies for the ADC
adc_1v8_shdn_n_o => adc_1v8_shdn_n_o,
adc_m5v_shdn_n_o => adc_m5v_shdn_n_o,
adc_5v_en_n_o => adc_5v_en_n_o,
-- WISHBONE interface with the GN4124 core
wb_adr_i => cnx_master_out(c_WB_SLAVE_MASTERFIP).adr,
wb_dat_i => cnx_master_out(c_WB_SLAVE_MASTERFIP).dat,
wb_stb_i => cnx_master_out(c_WB_SLAVE_MASTERFIP).stb,
wb_we_i => cnx_master_out(c_WB_SLAVE_MASTERFIP).we,
wb_cyc_i => cnx_master_out(c_WB_SLAVE_MASTERFIP).cyc,
wb_sel_i => cnx_master_out(c_WB_SLAVE_MASTERFIP).sel,
wb_dat_o => cnx_master_in(c_WB_SLAVE_MASTERFIP).dat,
wb_ack_o => cnx_master_in(c_WB_SLAVE_MASTERFIP).ack,
wb_stall_o => cnx_master_in(c_WB_SLAVE_MASTERFIP).stall,
-- Interrupt line from EIC
wb_irq_o => fmc_eic_irq,
wb_adr_i => "00" & cnx_master_out(c_WB_SLAVE_MASTERFIP).adr(31 downto 2),
wb_dat_i => cnx_master_out(c_WB_SLAVE_MASTERFIP).dat,
wb_stb_i => cnx_master_out(c_WB_SLAVE_MASTERFIP).stb,
wb_we_i => cnx_master_out(c_WB_SLAVE_MASTERFIP).we,
wb_cyc_i => cnx_master_out(c_WB_SLAVE_MASTERFIP).cyc,
wb_sel_i => cnx_master_out(c_WB_SLAVE_MASTERFIP).sel,
wb_dat_o => cnx_master_in(c_WB_SLAVE_MASTERFIP).dat,
wb_ack_o => cnx_master_in(c_WB_SLAVE_MASTERFIP).ack,
wb_stall_o => cnx_master_in(c_WB_SLAVE_MASTERFIP).stall,
-- Aux
aux_o => aux);
aux_o => aux);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Unused wishbone signals
cnx_master_in(c_WB_SLAVE_MASTERFIP).err <= '0';
......@@ -474,7 +498,7 @@ begin
port map (
clk_i => clk_40m_sys,
rst_n_i => rst_sys_n,
pulse_i => aux(2),
pulse_i => aux(0),
extended_o => rx_err);
cmp_rx_act_extend_p : gc_extend_pulse
......@@ -486,23 +510,6 @@ begin
pulse_i => aux(1),
extended_o => rx_act);
---------------------------------------------------------------------------------------------------
-- VIC --
---------------------------------------------------------------------------------------------------
cmp_vic : xwb_vic
generic map
(g_interface_mode => PIPELINED,
g_address_granularity => BYTE,
g_num_interrupts => 1,
g_init_vectors => c_VIC_VECTOR_TABLE)
port map
(clk_sys_i => clk_40m_sys,
rst_n_i => rst_sys_n,
slave_i => cnx_master_out(c_WB_SLAVE_VIC),
slave_o => cnx_master_in(c_WB_SLAVE_VIC),
irqs_i(0) => fmc_eic_irq,
irq_master_o => irq_to_gn4124);
---------------------------------------------------------------------------------------------------
-- Carrier 1-wire MASTER DS18B20 (thermometer + unique ID) --
......@@ -525,7 +532,7 @@ begin
owr_i => carrier_owr_i);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
carrier_onewire_b <= '0' when carrier_owr_en(0) = '1' else 'Z';
carrier_onewire_b <= '0' when carrier_owr_en(0) = '1' else 'Z';
carrier_owr_i(0) <= carrier_onewire_b;
......
top/spec_wrnode/spec_top.ucf
View file @ eaf3913c
......@@ -201,6 +201,38 @@ NET "speed_b1_i" LOC = AB5;
NET "speed_b1_i" IOSTANDARD = "LVCMOS25";
NET "bus_term_en_n_o" LOC = Y13;
NET "bus_term_en_n_o" IOSTANDARD = "LVCMOS25";
NET "ext_sync_term_en_o" LOC = AB13;
NET "ext_sync_term_en_o" IOSTANDARD = "LVCMOS25";
NET "ext_sync_i" LOC = T8;
NET "ext_sync_i" IOSTANDARD = "LVCMOS25";
NET "ext_sync_tst_n_o" LOC = U8;
NET "ext_sync_tst_n_o" IOSTANDARD = "LVCMOS25";
NET "ext_sync_oe_o" LOC = W6;
NET "ext_sync_oe_o" IOSTANDARD = "LVCMOS25";
NET "ext_sync_dir_o" LOC = Y6;
NET "ext_sync_dir_o" IOSTANDARD = "LVCMOS25";
NET "adc_1v8_shdn_n_o" LOC = V17;
NET "adc_1v8_shdn_n_o" IOSTANDARD = "LVCMOS25";
NET "adc_m5v_shdn_n_o" LOC = W18;
NET "adc_m5v_shdn_n_o" IOSTANDARD = "LVCMOS25";
NET "adc_5v_en_n_o" LOC = R9;
NET "adc_5v_en_n_o" IOSTANDARD = "LVCMOS25";
NET "led_tx_err_n_o" LOC = C19;
NET "led_tx_err_n_o" IOSTANDARD = "LVCMOS25";
......
top/spec_wrnode/spec_top.vhd
View file @ eaf3913c
......@@ -6,7 +6,7 @@
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT
-- Created : 2014-04-01
-- Last update: 2015-10-06
-- Last update: 2015-08-14
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -45,6 +45,7 @@
library ieee;
use ieee.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.wishbone_pkg.all;
......@@ -106,7 +107,7 @@ entity spec_top is
tx_error : in std_logic; -- transmit error
vc_rdy : in std_logic_vector(1 downto 0); -- channel ready
-- font panel leds
-- front panel leds
led_red : out std_logic;
led_green : out std_logic;
......@@ -119,6 +120,20 @@ entity spec_top is
-- Bus Speed
speed_b0_i : in std_logic;
speed_b1_i : in std_logic;
-- Bus termination
bus_term_en_n_o : out std_logic; -- 150 Ohms termination of the bus -- check again
-- External synchronisation pulse transceiver
ext_sync_term_en_o : out std_logic; -- enable 50 Ohms termination of the pulse
ext_sync_dir_o : out std_logic; -- transceiver direction
ext_sync_oe_o : out std_logic; -- transceiver output enable
ext_sync_tst_n_o : out std_logic; -- emulation of the LEMO input
ext_sync_i : in std_logic; -- sync pulse
-- Power supplies for the ADC
adc_1v8_shdn_n_o : out std_logic;
adc_m5v_shdn_n_o : out std_logic;
adc_5v_en_n_o : out std_logic;
-- FielDrive
fd_rxcdn_i : in std_logic;
......@@ -153,16 +168,16 @@ architecture rtl of spec_top is
(
out_slot_count => 4,
out_slot_config => (
0 => (width => 128, entries => 4), -- control CPU 0 (to host)
1 => (width => 128, entries => 4), -- control CPU 1 (to host)
2 => (width => 128, entries => 4), -- log CPU 0
3 => (width => 128, entries => 4), -- log CPU 1
0 => (width => 128, entries => 8), -- control CPU 0 (to host)
1 => (width => 128, entries => 8), -- control CPU 1 (to host)
2 => (width => 16, entries => 128), -- log CPU 0
3 => (width => 16, entries => 128), -- log CPU 1
others => (0, 0)),
in_slot_count => 2,
in_slot_config => (
0 => (width => 128, entries => 4), -- control CPU 0 (from host)
1 => (width => 128, entries => 4), -- control CPU 1 (from host)
0 => (width => 32, entries => 8), -- control CPU 0 (from host)
1 => (width => 32, entries => 8), -- control CPU 1 (from host)
others => (0, 0)
)
);
......@@ -176,12 +191,12 @@ architecture rtl of spec_top is
(
out_slot_count => 1,
out_slot_config => (
0 => (width => 128, entries => 4), -- TDC remote out
0 => (width => 128, entries => 16), -- TDC remote out
others => (0, 0)),
in_slot_count => 1,
in_slot_config => (
0 => (width => 128, entries => 4), -- FD remote in
0 => (width => 128, entries => 16), -- FD remote in
others => (0, 0)
)
......@@ -191,7 +206,7 @@ architecture rtl of spec_top is
(
app_id => x"0f1dc03e",
cpu_count => 2,
cpu_memsizes => (65536, 65536, 0, 0, 0, 0, 0, 0),
cpu_memsizes => (32768, 32768, 0, 0, 0, 0, 0, 0),
hmq_config => c_hmq_config,
rmq_config => c_rmq_config,
shared_mem_size => 65536
......@@ -214,6 +229,10 @@ architecture rtl of spec_top is
signal rx_err, rx_act, fd_txena : std_logic;
signal aux : std_logic_vector(7 downto 0);
-- LEDs
signal led_clk_40m_divider : unsigned(22 downto 0);
signal led_clk_40m_aux : std_logic_vector(7 downto 0);
begin
U_Node_Template : spec_node_template
......@@ -274,38 +293,45 @@ begin
fmc0_host_irq_i => '0'
);
cmp_masterFIP_mezz : fmc_masterFIP_mezz
cmp_masterFIP_core : fmc_masterFIP_core
generic map
(g_span => 32,
g_width => 32,
values_for_simul => g_simulation)
(g_span => 32,
g_width => 32,
values_for_simul => g_simulation)
port map
(clk_sys_i => clk_sys,
rst_sys_n_i => rst_n_sys,
fd_rxcdn_i => fd_rxcdn_i,
fd_rxd_i => fd_rxd_i,
fd_txer_i => fd_txer_i,
fd_wdgn_i => fd_wdgn_i,
fd_rstn_o => fd_rstn_o,
fd_txck_o => fd_txck_o,
fd_txd_o => fd_txd_o,
fd_txena_o => fd_txena,
speed_b0_i => speed_b0_i,
speed_b1_i => speed_b1_i,
(clk_i => clk_sys,
rst_i => not(rst_n_sys),
fd_rxcdn_i => fd_rxcdn_i,
fd_rxd_i => fd_rxd_i,
fd_txer_i => fd_txer_i,
fd_wdgn_i => fd_wdgn_i,
fd_rstn_o => fd_rstn_o,
fd_txck_o => fd_txck_o,
fd_txd_o => fd_txd_o,
fd_txena_o => fd_txena,
speed_b0_i => speed_b0_i,
speed_b1_i => speed_b1_i,
bus_term_en_n_o => bus_term_en_n_o,
ext_sync_term_en_o => ext_sync_term_en_o,
ext_sync_dir_o => ext_sync_dir_o,
ext_sync_oe_o => ext_sync_oe_o,
ext_sync_tst_n_o => ext_sync_tst_n_o,
ext_sync_i => ext_sync_i,
adc_1v8_shdn_n_o => adc_1v8_shdn_n_o,
adc_m5v_shdn_n_o => adc_m5v_shdn_n_o,
adc_5v_en_n_o => adc_5v_en_n_o,
-- WISHBONE interface with the GN4124 core
wb_adr_i => fmc_dp_wb_out.adr,
wb_dat_i => fmc_dp_wb_out.dat,
wb_stb_i => fmc_dp_wb_out.stb,
wb_we_i => fmc_dp_wb_out.we,
wb_cyc_i => fmc_dp_wb_out.cyc,
wb_sel_i => fmc_dp_wb_out.sel,
wb_dat_o => fmc_dp_wb_in.dat,
wb_ack_o => fmc_dp_wb_in.ack,
wb_stall_o => fmc_dp_wb_in.stall,
-- Interrupt line from EIC
wb_irq_o => open,
wb_adr_i => fmc_dp_wb_out.adr,
wb_dat_i => fmc_dp_wb_out.dat,
wb_stb_i => fmc_dp_wb_out.stb,
wb_we_i => fmc_dp_wb_out.we,
wb_cyc_i => fmc_dp_wb_out.cyc,
wb_sel_i => fmc_dp_wb_out.sel,
wb_dat_o => fmc_dp_wb_in.dat,
wb_ack_o => fmc_dp_wb_in.ack,
wb_stall_o => fmc_dp_wb_in.stall,
-- Aux
aux_o => aux);
aux_o => aux);
fmc_dp_wb_in.err <= '0';
......@@ -314,8 +340,8 @@ begin
fd_txena_o <= fd_txena;
-- LEDs font panel
led_tx_err_n_o <= fd_txer_i;
-- LEDs front panel
--led_tx_err_n_o <= fd_txer_i;
led_tx_act_n_o <= fd_txena;
led_rx_err_n_o <= rx_err;
led_rx_act_n_o <= rx_act;
......@@ -336,7 +362,30 @@ begin
clk_i => clk_sys,
rst_n_i => rst_n_sys,
pulse_i => aux(1),
extended_o => rx_act);
extended_o => rx_act);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
clk_40m_sys_drive_led: process (clk_sys)
begin
if rising_edge(clk_sys) then
if(rst_n_sys = '0') then
led_clk_40m_aux <= "01111111";
led_clk_40m_divider <= (others => '0');
else
led_clk_40m_divider <= led_clk_40m_divider+ 1;
if(led_clk_40m_divider = 0) then
led_clk_40m_aux <= led_clk_40m_aux(6 downto 0) & led_clk_40m_aux(7);
end if;
end if;
end if;
end process;
-- -- -- -- --
led_tx_err_n_o <= led_clk_40m_aux(0);
end rtl;
......
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