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MasterFIP - Gateware
Commit c83385d9 authored by kblantos's avatar kblantos
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Fix hanging when MISO FIFO is full. Needs HW test. Clear from unused signals

parent c27ee562
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Showing with 4 additions and 13 deletions
rtl/mt_profip_translator.vhd
View file @ c83385d9
......@@ -112,7 +112,6 @@ architecture rtl of mt_profip_translator is
signal s_spi_mosi_data : std_logic_vector(g_data_width - 1 downto 0);
signal s_spi_miso_data : std_logic_vector(g_data_width - 1 downto 0);
signal s_mosi_data : std_logic_vector(g_data_width - 1 downto 0);
-- signal s_wr_control : std_logic_vector(7 downto 0); --! stores the CONTROL byte from MOSI
signal s_wr_rmq_id : std_logic_vector(7 downto 0); --! stores the RMQ ID byte from MOSI
signal s_wr_data_len : std_logic_vector(7 downto 0); --! stores the LENGTH byte from MOSI
signal s_wr_data_cnt : unsigned(7 downto 0); --! counts the number of data bytes from MOSI
......@@ -552,11 +551,6 @@ begin
s_miso_fifo_data_in(5) <= (rmq_snk_i(0)(5).hdr & rmq_snk_i(0)(5).valid & rmq_snk_i(0)(5).last & rmq_snk_i(0)(5).error & rmq_snk_i(0)(5).data);
s_miso_fifo_data_in(6) <= (rmq_snk_i(1)(0).hdr & rmq_snk_i(1)(0).valid & rmq_snk_i(1)(0).last & rmq_snk_i(1)(0).error & rmq_snk_i(1)(0).data);
--! Selection of WRITE or READ to/from RMQ: this is the first 32-bits that ERTEC sends when the CS goes LOW
--! this is selected by wr_control(0). So we have:
--! wr_control(0) = '0' --> WRITE to RMQ
--! wr_control(0) = '1' --> READ from RMQ
----------------------------------------------------------------------------
--! RX: MASTERFIP TRANSLATOR --> MT (RMQ)
----------------------------------------------------------------------------
......@@ -577,7 +571,6 @@ begin
begin
if s_rst_n = '0' then
s_wr_state <= IDLE;
-- s_wr_control <= (others => '0');
s_wr_data_len <= (others => '0');
s_wr_header_cnt <= (others => '1');
s_wr_data_cnt <= (others => '0');
......@@ -591,12 +584,10 @@ begin
when IDLE =>
if (rmq_src_i.ready = '1' and s_mosi_rd_en = '1') then
s_wr_state <= BASIC_INFO;
-- s_wr_control <= s_mosi_fifo_data(31 downto 24);
s_wr_data_len <= s_mosi_fifo_data(15 downto 8);
s_wr_header_cnt <= (others => '1');
else
s_wr_state <= IDLE;
-- s_wr_control <= (others => '0');
s_wr_data_len <= (others => '0');
s_wr_header_cnt <= (others => '1');
s_wr_data_cnt <= (others => '0');
......@@ -606,10 +597,10 @@ begin
----------------------------------------------------------------
--! STATE BASIC_INFO
when BASIC_INFO =>
if (rmq_src_i.ready = '1' and s_mosi_rd_en = '1' and s_operation = '0') then --s_wr_control(0) = '0') then
if (rmq_src_i.ready = '1' and s_mosi_rd_en = '1' and s_operation = '0') then
s_wr_data_cnt <= unsigned(s_wr_data_len); -- assign the width of payload in bytes
s_wr_state <= HEADER_1;
elsif (s_spi_cs_n = '1' or s_operation = '1') then --s_wr_control(0) = '1') then
elsif (s_spi_cs_n = '1' or s_operation = '1') then
s_wr_state <= END_OF_FRAME;
s_fail <= '1';
else
......@@ -805,7 +796,7 @@ begin
s_data_valid <= '1';
s_rd_state <= RD_HEADER;
s_spi_miso_data <= s_miso_data_reg;
elsif s_miso_fifo_rd_empty(s_rmq_id) = '1' and s_ready = '1' then
elsif s_miso_fifo_rd_empty(s_rmq_id) = '1' then
s_data_valid <= '1';
s_rd_state <= ERROR_STATE;
elsif s_spi_cs_n = '1' then
......@@ -913,7 +904,7 @@ begin
--! STATE RD_INTERRUPT
when RD_INTERRUPT =>
s_data_valid <= '0';
if s_miso_fifo_data_out(s_rmq_id)(34) = '1' and s_miso_fifo_data_out(s_rmq_id)(33) = '1' then -- valid & last
if s_miso_fifo_rd_empty(s_rmq_id) = '1' and s_ready = '1' then -- valid & last
s_rd_state <= END_OF_FRAME;
else
s_rd_state <= RD_INTERRUPT;
......
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