Addition of 125MHz extra clock from SVEC PLL in order to be able to handle…

Addition of 125MHz extra clock from SVEC PLL in order to be able to handle higher SPI clock frequency. Simulation and build OK. HW test needed

Addition of 125MHz extra clock from SVEC PLL in order to be able to handle…
Addition of 125MHz extra clock from SVEC PLL in order to be able to handle higher SPI clock frequency. Simulation and build OK. HW test needed
c27ee562 · kblantos · 8657ed23 · c27ee562 · c27ee562 · c27ee562
Commit c27ee562 authored Mar 16, 2023 by kblantos
4 changed files
--- a/rtl/mt_profip_translator.vhd
+++ b/rtl/mt_profip_translator.vhd
--- a/rtl/rmq_stream_fifo.vhd
+++ b/rtl/rmq_stream_fifo.vhd
@@ -22,10 +22,10 @@ use work.gencores_pkg.all;
 --============================================================================--
 entity rmq_stream_fifo is
    generic (
-        g_DATA_WIDTH                : natural;
-        g_CDC_ENABLE                : natural range 0 to 1;
-        g_FIFO_DEPTH                : natural := 128;
-        g_show_ahead                : boolean := true
+        g_DATA_WIDTH        : natural;
+        g_CDC_ENABLE        : natural range 0 to 1;
+        g_FIFO_DEPTH        : natural := 128;
+        g_show_ahead        : boolean := true
    );
    port (
        rst_n_i             : in  std_logic;                --! FPGA reset
@@ -154,9 +154,9 @@ begin
        );
    end generate gen_CDC_true;

-    rmq_src_o.data <= s_fifo_output(g_DATA_WIDTH-1 downto 0);
-    rmq_src_o.hdr <= s_fifo_output(g_DATA_WIDTH+2);
-    rmq_src_o.last <= s_fifo_output(g_DATA_WIDTH+1);
+    rmq_src_o.data  <= s_fifo_output(g_DATA_WIDTH-1 downto 0);
+    rmq_src_o.hdr   <= s_fifo_output(g_DATA_WIDTH+2);
+    rmq_src_o.last  <= s_fifo_output(g_DATA_WIDTH+1);
    rmq_src_o.error <= s_fifo_output(g_DATA_WIDTH);
    rmq_src_o.valid <= not (s_output_empty);


--- a/top/svec/svec_masterfip_mt_urv.ucf
+++ b/top/svec/svec_masterfip_mt_urv.ucf
@@ -174,6 +174,10 @@ NET "ertec_uart_rx_o" LOC = "AF23";
 NET "ertec_uart_rx_o" IOSTANDARD = "LVCMOS25";

 #PIN "cmp_mt_profip_translator/cmp_mosi_async_fifo/empty_int_BUFG.O" CLOCK_DEDICATED_ROUTE = FALSE;
-TIMESPEC "TS_exception_cdc"= FROM "cmp_spi_rmq_bridge/clk_i" TO "cmp_spi_rmq_bridge/spi_sample_clk_i" TIG;
-TIMESPEC "TS_exception_cdc_2"= FROM "cmp_spi_rmq_bridge/spi_sample_clk_i" TO "cmp_spi_rmq_bridge/clk_i" TIG;
+TIMESPEC "TS_exception_cdc"= FROM "cmp_mt_profip_translator/clk_i" TO "cmp_mt_profip_translator/spi_sample_clk_i" TIG;
+TIMESPEC "TS_exception_cdc_2"= FROM "cmp_mt_profip_translator/spi_sample_clk_i" TO "cmp_mt_profip_translator/clk_i" TIG;
 #TIMESPEC "TS_exception666_3"= FROM "cmp_spi_rmq_bridge/spi_sample_clk_i/s_tx_reg_31" TO "cmp_spi_rmq_bridge/spi_miso_o" 15 ns DATAPATHONLY;
+
+# Reset false path
+NET "*/s_rst_n" TIG;
+
--- a/top/svec/svec_masterfip_mt_urv.vhd
+++ b/top/svec/svec_masterfip_mt_urv.vhd
-- vsg_off
-- vsg_off
 ---------------------------------------------------------------------------------------------------
 -- SPDX-FileCopyrightText: 2022 CERN (home.cern)                                                  |
 --                                                                                                |
@@ -406,6 +404,7 @@ architecture rtl of svec_masterfip_mt_urv is
  signal clk_62m5_sys     : std_logic;
  signal local_reset_n    : std_logic;
  signal rst_n_sys        : std_logic;
+  signal clk_125m_sys     : std_logic; -- for CDC in SPI
  signal s_rmq_id         : std_logic_vector(7 downto 0);
  signal console_irq      : std_logic;
  signal hmq_in_irq       : std_logic;
@@ -472,12 +471,13 @@ begin
      g_data_width        => 32,
      g_cpol              => 0,
      g_cpha              => 1,
-      g_cdc_enable        => 0,
+      g_cdc_enable        => 1,
      g_input_fifo_depth  => 4,
      g_output_fifo_depth => 4)
    port map(
      clk_i            => clk_62m5_sys,
      rst_n_i          => local_reset_n,
+      spi_sample_clk_i => clk_125m_sys,
      ertec_rst_i      => ertec_rst_i,
      rmq_status_o     => s_rmq_status,
      rmq_id_o         => s_rmq_id,
@@ -771,7 +771,7 @@ begin
      --  Clocks and reset.
      clk_sys_62m5_o      => clk_62m5_sys, -- we only need the 62.5MHz that svec provides
      rst_sys_62m5_n_o    => local_reset_n,
-      clk_ref_125m_o      => open,
+      clk_ref_125m_o      => clk_125m_sys,
      rst_ref_125m_n_o    => open,
      --  Interrupts
      irq_user_i(6)       => hmq_in_irq,