Skip to content

M
MasterFIP - Gateware
Commit ab937ea1 authored by Evangelia Gousiou's avatar Evangelia Gousiou
Browse files
Options

new architecture of masterfip; only the ser/des in vhdl and then the WRNC will… 

new architecture of masterfip; only the ser/des in vhdl and then the WRNC will do all the logic; in this commit there is no WRNC, it is a test design for the ser/des.
parent c273e939
Expand all Hide whitespace changes
Inline Side-by-side
Showing with 2082 additions and 901 deletions
rtl/fmc_masterFIP_core.vhd
View file @ ab937ea1
This diff is collapsed.
rtl/fmc_masterFIP_mezzanine.vhd
View file @ ab937ea1
......@@ -99,7 +99,7 @@ entity fmc_masterFIP_mezzanine is
values_for_simul : boolean := FALSE);
port
-- TDC core
(-- Clock & reset 62M5
(-- Clock & reset 40MHz
clk_sys_i : in std_logic; -- 40 MHz clock
rst_sys_n_i : in std_logic; -- reset for 40 MHz logic
-- FielDrive
......@@ -112,7 +112,7 @@ entity fmc_masterFIP_mezzanine is
fd_txd_o : out std_logic;
fd_txena_o : out std_logic;
-- Aux
activate_loop_p_o : out std_logic;
tx_start_p_o : out std_logic;
-- WISHBONE interface with the GN4124/VME_core
-- for the core configuration | data retrieval | core interrupts | 1Wire | I2C
wb_adr_i : in std_logic_vector(31 downto 0);
......@@ -214,10 +214,10 @@ begin
-- CSR WISHBONE CROSSBAR --
---------------------------------------------------------------------------------------------------
-- CSR wishbone address decoder
-- 0x10000 -> mezzanine board 1-Wire
-- 0x10000 -> mezzanine board 1-Wire -not used
-- 0x11000 -> masterFIP core configuration and data
-- 0x12000 -> EIC
-- 0x13000 -> mezzanine board EEPROM I2C
-- 0x13000 -> mezzanine board EEPROM I2C -not used
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
cmp_sdb_crossbar : xwb_sdb_crossbar
......@@ -253,7 +253,7 @@ begin
---------------------------------------------------------------------------------------------------
-- masterFIP CORE --
---------------------------------------------------------------------------------------------------
cmp_tdc_core: fmc_masterFIP_core
cmp_masterfip_core: fmc_masterFIP_core
generic map
(g_span => g_span,
g_width => g_width,
......@@ -274,13 +274,15 @@ begin
-- Interrupts
irq_p_o => irq_p,
-- Aux
activate_loop_p_o => activate_loop_p_o,
tx_start_p_o => tx_start_p_o,
-- WISHBONE CSR for core configuration
wb_adr_i => wb_adr,
wb_dat_i => cnx_master_out(c_WB_SLAVE_CORE_CONFIG).dat,
wb_stb_i => cnx_master_out(c_WB_SLAVE_CORE_CONFIG).stb,
wb_sel_i => cnx_master_out(c_WB_SLAVE_CORE_CONFIG).sel,
wb_we_i => cnx_master_out(c_WB_SLAVE_CORE_CONFIG).we,
wb_cyc_i => cnx_master_out(c_WB_SLAVE_CORE_CONFIG).cyc,
wb_stall_o => cnx_master_in(c_WB_SLAVE_CORE_CONFIG).stall,
wb_dat_o => cnx_master_in(c_WB_SLAVE_CORE_CONFIG).dat,
wb_ack_o => cnx_master_in(c_WB_SLAVE_CORE_CONFIG).ack);
......@@ -292,12 +294,11 @@ begin
-- Unused wishbone signals
cnx_master_in(c_WB_SLAVE_CORE_CONFIG).err <= '0';
cnx_master_in(c_WB_SLAVE_CORE_CONFIG).rty <= '0';
cnx_master_in(c_WB_SLAVE_CORE_CONFIG).stall <= '0';
cnx_master_in(c_WB_SLAVE_CORE_CONFIG).int <= '0';
---------------------------------------------------------------------------------------------------
-- TDC Mezzanine Board UniqueID&Thermometer OneWire --
-- masterFIP Mezzanine Board UniqueID&Thermometer OneWire --
---------------------------------------------------------------------------------------------------
cmp_fmc_onewire : xwb_onewire_master
generic map
......@@ -354,7 +355,7 @@ irq_p_o <= irq_p;
---------------------------------------------------------------------------------------------------
-- TDC Mezzanine Board EEPROM I2C --
-- masterFIP Mezzanine Board EEPROM I2C --
---------------------------------------------------------------------------------------------------
cmp_I2C_master : xwb_i2c_master
generic map
......
rtl/fmc_masterfip_csr.vhd 0 → 100644
View file @ ab937ea1
This diff is collapsed.
rtl/masterFIP_pkg.vhd
View file @ ab937ea1
This diff is collapsed.
rtl/wf_cons_bytes_processor.vhd
View file @ ab937ea1
This diff is collapsed.
rtl/wf_crc.vhd
View file @ ab937ea1
......@@ -73,7 +73,7 @@ entity wf_crc is port(
uclk_i : in std_logic; -- 40 MHz clock
-- Signal from the wf_reset_unit
nfip_rst_i : in std_logic; -- nanoFIP internal reset
core_rst_i : in std_logic; -- nanoFIP internal reset
-- Signals from the wf_rx_deserializer/ wf_tx_serializer units
data_bit_i : in std_logic; -- incoming data bit stream
......@@ -130,7 +130,7 @@ begin
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
if core_rst_i = '1' then
s_q <= (others => '0');
else
......
rtl/wf_fd_receiver.vhd
View file @ ab937ea1
......@@ -104,7 +104,7 @@ entity wf_fd_receiver is port(
fd_rxd_a_i : in std_logic; -- receiver data
-- Signal from the wf_reset_unit
nfip_rst_i : in std_logic; -- nanoFIP internal reset
core_rst_i : in std_logic; -- nanoFIP internal reset
-- Signal from the wf_engine_control unit
rx_rst_i : in std_logic; -- reset during production or
......@@ -115,7 +115,7 @@ entity wf_fd_receiver is port(
-- OUTPUTS
-- Signals to the wf_engine_control and wf_consumption
rx_byte_o : out std_logic_vector (7 downto 0); -- retrieved data byte
rx_tx_byte_o : out std_logic_vector (7 downto 0); -- retrieved data byte
rx_byte_ready_p_o : out std_logic; -- pulse indicating a new retrieved data byte
rx_fss_crc_fes_ok_p_o : out std_logic; -- indication of a frame (ID_DAT or RP_DAT) with
-- correct FSS, FES & CRC; pulse upon FES detection
......@@ -152,7 +152,7 @@ begin
FIELDRIVE_Receiver_Deglitcher: wf_rx_deglitcher
port map(
uclk_i => uclk_i,
nfip_rst_i => nfip_rst_i,
core_rst_i => core_rst_i,
fd_rxd_a_i => fd_rxd_a_i,
-----------------------------------------------------------------
fd_rxd_filt_o => s_fd_rxd_filt,
......@@ -172,7 +172,7 @@ begin
port map(
uclk_i => uclk_i,
rate_i => rate_i,
nfip_rst_i => nfip_rst_i,
core_rst_i => core_rst_i,
fd_rxd_edge_p_i => s_rxd_filt_edge_p,
rx_osc_rst_i => s_rx_osc_rst,
-----------------------------------------------------------------
......@@ -191,7 +191,7 @@ begin
FIELDRIVE_Receiver_Deserializer: wf_rx_deserializer
port map(
uclk_i => uclk_i,
nfip_rst_i => nfip_rst_i,
core_rst_i => core_rst_i,
rx_rst_i => rx_rst_i,
sample_bit_p_i => s_sample_bit_p,
sample_manch_bit_p_i => s_sample_manch_bit_p,
......@@ -202,7 +202,7 @@ begin
fd_rxd_i => s_fd_rxd_filt,
-----------------------------------------------------------------
byte_ready_p_o => rx_byte_ready_p_o,
byte_o => rx_byte_o,
tx_byte_o => rx_tx_byte_o,
fss_crc_fes_ok_p_o => rx_fss_crc_fes_ok_p_o,
rx_osc_rst_o => s_rx_osc_rst,
fss_received_p_o => rx_fss_received_p_o,
......
rtl/wf_fd_transmitter.vhd
View file @ ab937ea1
......@@ -97,22 +97,25 @@ entity wf_fd_transmitter is port(
rate_i : in std_logic_vector (1 downto 0); -- WorldFIP bit rate
-- Signal from the wf_reset_unit
nfip_rst_i : in std_logic; -- nanoFIP internal reset
core_rst_i : in std_logic; -- nanoFIP internal reset
tx_bytes_num_i : in std_logic_vector (7 downto 0);
-- Signals from the wf_production unit
tx_byte_i : in std_logic_vector (7 downto 0); -- byte to be delivered
-- Signals from the wf_engine_control
tx_start_p_i : in std_logic; -- indication for the start of the production
tx_byte_request_accept_p_i : in std_logic; -- indication that a byte is ready to be delivered
tx_last_data_byte_p_i : in std_logic; -- indication of he last data byte
-- (CRC & FES not included)
-- structure with 32 words of 32-bit each
tx_frame_i : in tx_frame_t;
-- control byte
tx_ctrl_byte_i : in std_logic_vector (7 downto 0);
-- OUTPUTS
tx_byte_index_o : out std_logic_vector (7 downto 0);
-- Signal to the wf_engine_control
tx_byte_request_p_o : out std_logic; -- request for a new byte to be transmitted; pulse
-- at the end of the transmission of a previous byte
tx_completed_p_o : out std_logic; -- pulse upon termination of a transmission
-- (CRC & FES included)
......@@ -147,7 +150,7 @@ begin
port map(
uclk_i => uclk_i,
rate_i => rate_i,
nfip_rst_i => nfip_rst_i,
core_rst_i => core_rst_i,
tx_osc_rst_p_i => s_tx_osc_rst_p,
-----------------------------------------------
tx_clk_o => tx_clk_o,
......@@ -163,18 +166,19 @@ begin
tx_serializer: wf_tx_serializer
port map(
uclk_i => uclk_i,
nfip_rst_i => nfip_rst_i,
core_rst_i => core_rst_i,
tx_start_p_i => tx_start_p_i,
byte_request_accept_p_i => tx_byte_request_accept_p_i,
byte_i => tx_byte_i,
last_byte_p_i => tx_last_data_byte_p_i,
tx_bytes_num_i => tx_bytes_num_i,
tx_byte_i => tx_byte_i,
tx_sched_p_buff_i => s_tx_clk_p_buff,
tx_frame_i => tx_frame_i,
tx_ctrl_byte_i => tx_ctrl_byte_i,
-----------------------------------------------
tx_byte_request_p_o => tx_byte_request_p_o,
tx_byte_index_o => tx_byte_index_o,
tx_completed_p_o => tx_completed_p_o,
tx_data_o => tx_data_o,
tx_osc_rst_p_o => s_tx_osc_rst_p,
tx_enable_o => tx_enable_o );
tx_enable_o => tx_enable_o);
-----------------------------------------------
......
rtl/wf_prod_bytes_retriever.vhd
View file @ ab937ea1
This diff is collapsed.
rtl/wf_rx_deglitcher.vhd
View file @ ab937ea1
......@@ -66,7 +66,7 @@ entity wf_rx_deglitcher is port(
uclk_i : in std_logic; -- 40 MHz clock
-- Signal from the wf_reset_unit
nfip_rst_i : in std_logic; -- nanoFIP internal reset
core_rst_i : in std_logic; -- nanoFIP internal reset
-- nanoFIP FIELDRIVE (synchronized with uclk)
fd_rxd_a_i : in std_logic; -- receiver data
......@@ -109,7 +109,7 @@ begin
FD_RXD_synchronizer: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
if core_rst_i = '1' then
s_fd_rxd_synch <= (others => '0');
else
......@@ -132,7 +132,7 @@ begin
FD_RXD_deglitcher: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
if core_rst_i = '1' then
s_filt_c <= to_unsigned (c_DEGLITCH_THRESHOLD, s_filt_c'length) srl 1;-- middle value
s_fd_rxd_filt <= '0';
s_fd_rxd_filt_d1 <= '0';
......
rtl/wf_rx_deserializer.vhd
View file @ ab937ea1
......@@ -126,7 +126,7 @@ entity wf_rx_deserializer is port(
uclk_i : in std_logic; -- 40 MHz clock
-- Signal from the wf_reset_unit
nfip_rst_i : in std_logic; -- nanoFIP internal reset
core_rst_i : in std_logic; -- nanoFIP internal reset
-- Signal from the wf_engine_control unit
rx_rst_i : in std_logic; -- reset during production or
......@@ -149,7 +149,7 @@ entity wf_rx_deserializer is port(
-- OUTPUTS
-- Signals to the wf_consumption and the wf_engine_control units
byte_o : out std_logic_vector (7 downto 0) ; -- retrieved data byte
tx_byte_o : out std_logic_vector (7 downto 0) ; -- retrieved data byte
byte_ready_p_o : out std_logic; -- pulse indicating a new retrieved data byte
fss_crc_fes_ok_p_o : out std_logic; -- indication of a frame (ID_DAT or RP_DAT) with
-- correct FSS, FES and CRC
......@@ -218,7 +218,7 @@ begin
Deserializer_FSM_Sync: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' or rx_rst_i = '1' or s_session_timedout = '1' then
if core_rst_i = '1' or rx_rst_i = '1' or s_session_timedout = '1' then
rx_st <= IDLE;
else
rx_st <= nx_rx_st;
......@@ -415,7 +415,7 @@ begin
Append_Bit_To_Byte: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
if core_rst_i = '1' then
s_byte_ready_p_d1 <= '0';
s_sample_manch_bit_p_d1 <= '0';
s_byte <= (others => '0');
......@@ -447,7 +447,7 @@ begin
generic map(g_counter_lgth => 4)
port map(
uclk_i => uclk_i,
counter_rst_i => nfip_rst_i,
counter_rst_i => core_rst_i,
counter_top_i => s_manch_bit_index_top,
counter_load_i => s_manch_bit_index_load_p,
counter_decr_i => s_manch_bit_index_decr_p,
......@@ -517,7 +517,7 @@ begin
CRC_Verification : wf_crc
port map(
uclk_i => uclk_i,
nfip_rst_i => nfip_rst_i,
core_rst_i => core_rst_i,
start_crc_p_i => s_receiving_fsd,
data_bit_ready_p_i => s_write_bit_to_byte_p,
data_bit_i => fd_rxd_i,
......@@ -535,7 +535,7 @@ begin
CRC_OK_pulse_delay: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' or s_receiving_bytes = '0' then
if core_rst_i = '1' or s_receiving_bytes = '0' then
s_CRC_ok_p_d <= '0';
s_CRC_ok_p_found <= '0';
else
......@@ -571,7 +571,7 @@ begin
generic map(g_counter_lgth => c_SESSION_TIMEOUT_C_LGTH)
port map(
uclk_i => uclk_i,
counter_rst_i => nfip_rst_i,
counter_rst_i => core_rst_i,
counter_top_i => (others => '1'),
counter_load_i => s_idle,
counter_decr_i => '1', -- on each uclk tick
......@@ -596,7 +596,7 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- output signals concurrent assignments :
byte_o <= s_byte;
tx_byte_o <= s_byte;
byte_ready_p_o <= s_byte_ready_p_d1;
rx_osc_rst_o <= s_idle;
fss_received_p_o <= s_receiving_fsd and s_fsd_last_bit;
......
rtl/wf_rx_osc.vhd
View file @ ab937ea1
......@@ -85,7 +85,7 @@ entity wf_rx_osc is port(
rate_i : in std_logic_vector (1 downto 0); -- WorldFIP bit rate
-- Signal from the wf_reset_unit
nfip_rst_i : in std_logic; -- nanoFIP internal reset
core_rst_i : in std_logic; -- nanoFIP internal reset
-- Signal from the wf_deglitcher unit
fd_rxd_edge_p_i : in std_logic; -- indication of an edge on fd_rxd
......@@ -172,11 +172,11 @@ begin
s_period_c_is_full <= '1' when s_period_c = s_period -1 else '0'; -- counter full indicator
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- counter reinitialized: if nfip_rst_i is active or
-- counter reinitialized: if core_rst_i is active or
-- if rx_osc_rst_i is active or
-- if an edge is detected in the expected window or
-- if it fills up
s_period_c_reinit <= nfip_rst_i or rx_osc_rst_i or (s_signif_edge_window and fd_rxd_edge_p_i)
s_period_c_reinit <= core_rst_i or rx_osc_rst_i or (s_signif_edge_window and fd_rxd_edge_p_i)
or s_period_c_is_full;
......@@ -218,7 +218,7 @@ begin
begin
if rising_edge (uclk_i) then
if (nfip_rst_i = '1') then
if (core_rst_i = '1') then
s_manch_clk <= '0';
s_bit_clk <= '0';
s_bit_clk_d1 <= '0';
......
rtl/wf_tx_osc.vhd
View file @ ab937ea1
......@@ -78,7 +78,7 @@ entity wf_tx_osc is
rate_i : in std_logic_vector (1 downto 0); -- WorldFIP bit rate
-- Signal from the wf_reset_unit
nfip_rst_i : in std_logic; -- nanoFIP internal reset
core_rst_i : in std_logic; -- nanoFIP internal reset
-- Signals from the wf_engine_control
tx_osc_rst_p_i : in std_logic; -- transmitter timeout
......@@ -142,10 +142,10 @@ begin
------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- counter reinitialized : if the nfip_rst_i is active or
-- counter reinitialized : if the core_rst_i is active or
-- if the tx_osc_rst_p_i is active or
-- if it fills up
s_period_c_reinit <= nfip_rst_i or tx_osc_rst_p_i or s_period_c_is_full;
s_period_c_reinit <= core_rst_i or tx_osc_rst_p_i or s_period_c_is_full;
......@@ -180,7 +180,7 @@ begin
clk_Signals_Construction: process (uclk_i)
begin
if rising_edge (uclk_i) then
if (nfip_rst_i = '1') or (tx_osc_rst_p_i = '1') then
if (core_rst_i = '1') or (tx_osc_rst_p_i = '1') then
s_tx_sched_p_buff <= (others => '0');
s_tx_clk_d1 <= '0';
else
......
rtl/wf_tx_serializer.vhd
View file @ ab937ea1
This diff is collapsed.
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment