first commit in the masterFIP-gw repo

c273e939 · unknown · c273e939 · c273e939 · c273e939 · c273e939
Commit c273e939 authored Jul 31, 2014 by unknown
629 changed files
--- a/ip_cores/VMEcore/Manifest.py
+++ b/ip_cores/VMEcore/Manifest.py
+files = [ "VME64xCore_Top.vhd",
+          "vme64x_pack.vhd",
+          "VME_Access_Decode.vhd",
+          "VME_Am_Match.vhd",
+          "VME_bus.vhd",
+          "VME_CR_CSR_Space.vhd",
+          "VME_CR_pack.vhd",
+          "VME_CSR_pack.vhd",
+          "VME_CRAM.vhd",
+          "VME_Funct_Match.vhd",
+          "VME_Init.vhd",
+          "VME_IRQ_Controller.vhd",
+          "VME_SharedComps.vhd",
+          "VME_swapper.vhd",
+          "VME_Wb_master.vhd"]
--- a/ip_cores/VMEcore/VME64xCore_Top.vhd
+++ b/ip_cores/VMEcore/VME64xCore_Top.vhd
--- a/ip_cores/VMEcore/VME_Access_Decode.vhd
+++ b/ip_cores/VMEcore/VME_Access_Decode.vhd
--- a/ip_cores/VMEcore/VME_Am_Match.vhd
+++ b/ip_cores/VMEcore/VME_Am_Match.vhd
+--_______________________________________________________________________________________
+--                             VME TO WB INTERFACE
+--
+--                                CERN,BE/CO-HT 
+--______________________________________________________________________________________
+-- File:                       VME_Am_Match.vhd
+--______________________________________________________________________________________
+-- Description: this component checks if the AM match. 
+-- If it is the correspondent AmMatch's bit is asserted. This condition is necessary but 
+-- not sufficient to select the function and access the board.
+-- If DFS = '0' the function supports only access modes with the same address width; 
+-- 1 function --> only 1 address width;
+-- with address width I mean A16, A24, A32 or A64.
+-- is sufficient check the AMCAP; AmMatch(i) <= s_FUNC_AMCAP(i)(to_integer(unsigned(Am))).
+-- If DFS = '1' the function supports access modes with different address widths so AmMatch(i)
+-- is asserted only if ADER[7:2] = AM and s_FUNC_AMCAP(i)(to_integer(unsigned(Am)))='1'.
+-- If ADER(i)'s XAM bit is asserted than AmMatch(i) is asserted only if AM = 0x20 and if the 
+-- XAMCAP(i)(to_integer(unsigned(XAm))) = '1' and if DFS = '1' also ADER[9:2] must be equal 
+-- to XAM[7:0] lines.
+--______________________________________________________________________________________
+-- Authors:                                   
+--               Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)                             
+--               Davide Pedretti       (Davide.Pedretti@cern.ch)  
+-- Date         11/2012                                                                           
+-- Version      v0.03 
+--______________________________________________________________________________________
+--                               GNU LESSER GENERAL PUBLIC LICENSE                                
+--                              ------------------------------------    
+-- Copyright (c) 2009 - 2011 CERN                           
+-- This source file is free software; you can redistribute it and/or modify it 
+-- under the terms of the GNU Lesser General Public License as published by the 
+-- Free Software Foundation; either version 2.1 of the License, or (at your option) 
+-- any later version. This source is distributed in the hope that it will be useful, 
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for 
+-- more details. You should have received a copy of the GNU Lesser General Public 
+-- License along with this source; if not, download it from 
+-- http://www.gnu.org/licenses/lgpl-2.1.html                     
+----------------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+use work.vme64x_pack.all;
+
+--===========================================================================
+-- Entity declaration
+--===========================================================================
+
+entity VME_Am_Match is
+   Port ( clk_i          : in  std_logic;
+          reset          : in  std_logic;
+          mainFSMreset   : in  std_logic;
+          Ader0          : in  std_logic_vector (31 downto 0);
+          Ader1          : in  std_logic_vector (31 downto 0);
+          Ader2          : in  std_logic_vector (31 downto 0);
+          Ader3          : in  std_logic_vector (31 downto 0);
+          Ader4          : in  std_logic_vector (31 downto 0);
+          Ader5          : in  std_logic_vector (31 downto 0);
+          Ader6          : in  std_logic_vector (31 downto 0);			  
+          Ader7          : in  std_logic_vector (31 downto 0);	
+          AmCap0         : in  std_logic_vector (63 downto 0);
+          AmCap1         : in  std_logic_vector (63 downto 0);
+          AmCap2         : in  std_logic_vector (63 downto 0);
+          AmCap3         : in  std_logic_vector (63 downto 0);
+          AmCap4         : in  std_logic_vector (63 downto 0);
+          AmCap5         : in  std_logic_vector (63 downto 0);
+          AmCap6         : in  std_logic_vector (63 downto 0);
+          AmCap7         : in  std_logic_vector (63 downto 0);
+          XAmCap0        : in  std_logic_vector (255 downto 0);
+          XAmCap1        : in  std_logic_vector (255 downto 0);
+          XAmCap2        : in  std_logic_vector (255 downto 0);
+          XAmCap3        : in  std_logic_vector (255 downto 0);
+          XAmCap4        : in  std_logic_vector (255 downto 0);
+          XAmCap5        : in  std_logic_vector (255 downto 0);
+          XAmCap6        : in  std_logic_vector (255 downto 0);
+          XAmCap7        : in  std_logic_vector (255 downto 0);
+          Am             : in  std_logic_vector (5 downto 0);
+          XAm            : in  std_logic_vector (7 downto 0);  
+          DFS_i          : in  std_logic_vector (7 downto 0);
+          decode         : in  std_logic;
+          AmMatch        : out std_logic_vector (7 downto 0));
+end VME_Am_Match;
+--===========================================================================
+-- Architecture declaration
+--===========================================================================
+architecture Behavioral of VME_Am_Match is
+   signal s_FUNC_ADER    : t_FUNC_32b_array;
+   signal s_FUNC_AMCAP   : t_FUNC_64b_array;
+   signal s_FUNC_XAMCAP  : t_FUNC_256b_array;
+   signal s_amcap_match  : std_logic_vector(7 downto 0);
+   signal s_xamcap_match : std_logic_vector(7 downto 0);
+--===========================================================================
+-- Architecture begin
+--===========================================================================
+begin
+
+   s_FUNC_ADER(0)   <= unsigned(Ader0);
+   s_FUNC_ADER(1)   <= unsigned(Ader1);
+   s_FUNC_ADER(2)   <= unsigned(Ader2);
+   s_FUNC_ADER(3)   <= unsigned(Ader3);
+   s_FUNC_ADER(4)   <= unsigned(Ader4);
+   s_FUNC_ADER(5)   <= unsigned(Ader5);
+   s_FUNC_ADER(6)   <= unsigned(Ader6);
+   s_FUNC_ADER(7)   <= unsigned(Ader7);
+
+   s_FUNC_AMCAP(0)  <= unsigned(AmCap0);
+   s_FUNC_AMCAP(1)  <= unsigned(AmCap1);
+   s_FUNC_AMCAP(2)  <= unsigned(AmCap2);
+   s_FUNC_AMCAP(3)  <= unsigned(AmCap3);
+   s_FUNC_AMCAP(4)  <= unsigned(AmCap4);
+   s_FUNC_AMCAP(5)  <= unsigned(AmCap5);
+   s_FUNC_AMCAP(6)  <= unsigned(AmCap6);
+   s_FUNC_AMCAP(7)  <= unsigned(AmCap7);
+
+   s_FUNC_XAMCAP(0) <= unsigned(XAmCap0);
+   s_FUNC_XAMCAP(1) <= unsigned(XAmCap1);
+   s_FUNC_XAMCAP(2) <= unsigned(XAmCap2);
+   s_FUNC_XAMCAP(3) <= unsigned(XAmCap3);
+   s_FUNC_XAMCAP(4) <= unsigned(XAmCap4);
+   s_FUNC_XAMCAP(5) <= unsigned(XAmCap5);
+   s_FUNC_XAMCAP(6) <= unsigned(XAmCap6);
+   s_FUNC_XAMCAP(7) <= unsigned(XAmCap7);
+
+   p_AMmatch : process(clk_i)
+   begin
+      if rising_edge(clk_i) then  
+         if mainFSMreset = '1' or reset = '1' then
+            AmMatch <= (others => '0');
+         elsif decode = '1' then	  
+            for i in AmMatch'range loop
+               if DFS_i(i) = '1' then
+                  if s_FUNC_ADER(i)(XAM_MODE) = '0' then
+                     if unsigned(s_FUNC_ADER(i)(7 downto 2)) = unsigned(Am) then
+                        AmMatch(i) <= s_amcap_match(i);                   
+                     else
+                        AmMatch(i) <= '0';
+                     end if;
+                  else
+                     if (unsigned(XAm) = unsigned(s_FUNC_ADER(i)(9 downto 2))) then
+                        AmMatch(i) <= s_xamcap_match(i) and s_amcap_match(i);                 
+                     else
+                        AmMatch(i) <= '0';
+                     end if;
+                  end if;
+               else  
+                  if s_FUNC_ADER(i)(XAM_MODE) = '1' then
+                     AmMatch(i) <= s_xamcap_match(i) and s_amcap_match(i);                        				
+                  else
+                     AmMatch(i) <= s_amcap_match(i);              
+                  end if;
+               end if;		
+            end loop;
+         end if;	
+      end if;
+   end process;
+------------------------------------------------------
+-- Check if the AM is in the AMCAP register
+   process(s_FUNC_AMCAP, Am)
+   begin
+      s_amcap_match <= (others => '0');
+      for i in 0 to 7 loop
+         s_amcap_match(i) <= s_FUNC_AMCAP(i)(to_integer(unsigned(Am)));  
+      end loop;
+   end process;
+-------------------------------------------------------
+-- Check if the XAM is in the XAMCAP register    
+   process(s_FUNC_XAMCAP, XAm)
+   begin
+      s_xamcap_match <= (others => '0');
+      for i in 0 to 7 loop    
+         s_xamcap_match(i) <= s_FUNC_XAMCAP(i)(to_integer(unsigned(XAm)));
+      end loop;
+   end process;
+------------------------------------------------------
+end Behavioral;
+--===========================================================================
+-- Architecture end
+--===========================================================================
--- a/ip_cores/VMEcore/VME_CRAM.vhd
+++ b/ip_cores/VMEcore/VME_CRAM.vhd
+--______________________________________________________________________________|
+--                             VME TO WB INTERFACE                              |
+--                                                                              |
+--                                CERN,BE/CO-HT                                 |
+--______________________________________________________________________________|
+-- File:                        VME_CRAM.vhd                                  |
+--______________________________________________________________________________|
+-- Description: RAM memory
+--______________________________________________________________________________
+-- Authors:                                      
+--               Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)                             
+--               Davide Pedretti       (Davide.Pedretti@cern.ch)  
+-- Date         11/2012                                                                           
+-- Version      v0.03  
+--______________________________________________________________________________
+--                               GNU LESSER GENERAL PUBLIC LICENSE                                
+--                              ------------------------------------    
+-- Copyright (c) 2009 - 2011 CERN                           
+-- This source file is free software; you can redistribute it and/or modify it under the terms of 
+-- the GNU Lesser General Public License as published by the Free Software Foundation; either     
+-- version 2.1 of the License, or (at your option) any later version.                             
+-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;       
+-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.     
+-- See the GNU Lesser General Public License for more details.                                    
+-- You should have received a copy of the GNU Lesser General Public License along with this       
+-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html                     
+---------------------------------------------------------------------------------------
+                                                               
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+use work.vme64x_pack.all;
+--===========================================================================
+-- Entity declaration
+--===========================================================================
+ entity VME_CRAM is
+ generic (dl : integer; 		
+ 			 al : integer := f_log2_size(c_CRAM_SIZE) 		
+			 );    
+ port (clk  : in std_logic; 			
+ 	we   : in std_logic; 				
+ 	aw    : in std_logic_vector(al - 1 downto 0); 	 
+ 	di   : in std_logic_vector(dl - 1 downto 0); 
+ 	dw  : out std_logic_vector(dl - 1 downto 0)
+	);   	 
+ end VME_CRAM; 
+ 												
+--===========================================================================
+-- Architecture declaration
+--===========================================================================
+ architecture syn of VME_CRAM is 
+ 
+ type ram_type is array (2**al - 1 downto 0) of std_logic_vector (dl - 1 downto 0); 
+ signal CRAM : ram_type; 
+
+--===========================================================================
+-- Architecture begin
+--===========================================================================
+begin 
+
+ process (clk) 
+ begin 
+ 	if (clk'event and clk = '1') then  
+ 		if (we = '1') then 
+ 			CRAM(conv_integer(aw)) <= di; 
+ 		end if; 
+		dw <= CRAM(conv_integer(aw));
+ 	end if; 
+ end process; 
+ 
+ end syn;
+--===========================================================================
+-- Architecture end
+--===========================================================================
+ 
--- a/ip_cores/VMEcore/VME_CR_CSR_Space.vhd
+++ b/ip_cores/VMEcore/VME_CR_CSR_Space.vhd
--- a/ip_cores/VMEcore/VME_CR_pack.vhd
+++ b/ip_cores/VMEcore/VME_CR_pack.vhd
--- a/ip_cores/VMEcore/VME_CSR_pack.vhd
+++ b/ip_cores/VMEcore/VME_CSR_pack.vhd
+--________________________________________________________________________________________________
+--                             VME TO WB INTERFACE
+--
+--                                CERN,BE/CO-HT 
+--________________________________________________________________________________________________
+-- File:                         VME_CSR_pack.vhd
+--________________________________________________________________________________________________
+-- Description: This file defines the default configuration of the CSR space after power-up or 
+-- software reset.
+--______________________________________________________________________________
+-- Authors:                                      
+--               Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)                             
+--               Davide Pedretti       (Davide.Pedretti@cern.ch)  
+-- Date         06/2012                                                                           
+-- Version      v0.02  
+--______________________________________________________________________________
+--                               GNU LESSER GENERAL PUBLIC LICENSE                                
+--                              ------------------------------------    
+-- Copyright (c) 2009 - 2011 CERN                           
+-- This source file is free software; you can redistribute it and/or modify it 
+-- under the terms of the GNU Lesser General Public License as published by the 
+-- Free Software Foundation; either version 2.1 of the License, or (at your option) 
+-- any later version. This source is distributed in the hope that it will be useful, 
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for 
+-- more details. You should have received a copy of the GNU Lesser General Public 
+-- License along with this source; if not, download it from 
+-- http://www.gnu.org/licenses/lgpl-2.1.html                     
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.numeric_std.all;
+
+use work.vme64x_pack.all;
+package VME_CSR_pack is
+
+constant c_csr_array : 	t_CSRarray :=
+(
+BAR  => x"00", --CR/CSR BAR
+BIT_SET_CLR_REG  => x"00", --Bit set register -- 0x10=module enable
+USR_BIT_SET_CLR_REG  => x"00", --Bit clear register
+CRAM_OWNER  => x"00", --CRAM_OWNER
+
+FUNC0_ADER_0 =>x"00",  --A32_S   "24"
+FUNC0_ADER_1 =>x"00",  --        "00"
+FUNC0_ADER_2 =>x"00",  --        "00"
+FUNC0_ADER_3 =>x"00",  --        "c0"
+
+FUNC1_ADER_0 =>x"00",  --A24_S   "e4"
+FUNC1_ADER_1 =>x"00",  --        "00"
+FUNC1_ADER_2 =>x"00",  --        "c0" 
+FUNC1_ADER_3 =>x"00",  --        "00"  
+
+FUNC2_ADER_0 =>x"00",   --A16_S  "a4"
+FUNC2_ADER_1 =>x"00",  --        "c0"
+FUNC2_ADER_2 =>x"00",  --        "00"
+FUNC2_ADER_3 =>x"00",  --        "00"
+
+FUNC3_ADER_0 =>x"00",   --A64_S  "04"
+FUNC3_ADER_1 =>x"00",
+FUNC3_ADER_2 =>x"00",
+FUNC3_ADER_3 =>x"00",
+
+FUNC4_ADER_0 =>x"00",   --used for decoding the FUNC3
+FUNC4_ADER_1 =>x"00",   --used for decoding the FUNC3
+FUNC4_ADER_2 =>x"00",   --used for decoding the FUNC3
+FUNC4_ADER_3 =>x"00",   --used for decoding the FUNC3 "c0"
+
+FUNC5_ADER_0 =>x"00",
+FUNC5_ADER_1 =>x"00",
+FUNC5_ADER_2 =>x"00",
+FUNC5_ADER_3 =>x"00",
+
+FUNC6_ADER_0 =>x"00",
+FUNC6_ADER_1 =>x"00",
+FUNC6_ADER_2 =>x"00",
+FUNC6_ADER_3 =>x"00",
+
+IRQ_Vector   =>x"00",  --"00" because each Slot has a different IRQ Vector
+                       -- and the VME Master should set this value
+IRQ_level    =>x"02",
+WB32bits     =>x"01",  -- 32 bit WB of default
+others => (others => '0'));
+end VME_CSR_pack;                                                                
+
+
+
+
+
+
+
+ 
+
+
+
+
+
+
+
+
+
+
+
+
--- a/ip_cores/VMEcore/VME_Funct_Match.vhd
+++ b/ip_cores/VMEcore/VME_Funct_Match.vhd
--- a/ip_cores/VMEcore/VME_IRQ_Controller.vhd
+++ b/ip_cores/VMEcore/VME_IRQ_Controller.vhd
--- a/ip_cores/VMEcore/VME_Init.vhd
+++ b/ip_cores/VMEcore/VME_Init.vhd
--- a/ip_cores/VMEcore/VME_SharedComps.vhd
+++ b/ip_cores/VMEcore/VME_SharedComps.vhd
+--_______________________________________________________________________________________
+--                             VME TO WB INTERFACE
+--
+--                                CERN,BE/CO-HT 
+--_______________________________________________________________________________________
+-- File:                       VME_SharedComps.vhd
+--_______________________________________________________________________________________
+-- Description: This component implements the rising and falling edge detection and the 
+-- tripple and double sample entities
+--_______________________________________________________________________________________
+-- Authors:                                     
+--               Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)                             
+--               Davide Pedretti       (Davide.Pedretti@cern.ch)  
+-- Date         11/2012                                                                           
+-- Version      v0.03  
+--_______________________________________________________________________________________
+--                               GNU LESSER GENERAL PUBLIC LICENSE                                
+--                              ------------------------------------    
+-- Copyright (c) 2009 - 2011 CERN                           
+-- This source file is free software; you can redistribute it and/or modify it 
+-- under the terms of the GNU Lesser General Public License as published by the 
+-- Free Software Foundation; either version 2.1 of the License, or (at your option) 
+-- any later version. This source is distributed in the hope that it will be useful, 
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for 
+-- more details. You should have received a copy of the GNU Lesser General Public 
+-- License along with this source; if not, download it from 
+-- http://www.gnu.org/licenses/lgpl-2.1.html                     
+----------------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+-- tripple sample sig_i signals to avoid metastable states
+entity SigInputSample is
+	port (
+		sig_i, clk_i: in std_logic;
+		sig_o: out std_logic );
+end SigInputSample;
+
+architecture RTL of SigInputSample is
+	signal s_1: std_logic;
+	signal s_2: std_logic;
+begin
+	process(clk_i)
+	begin
+		if rising_edge(clk_i) then
+			s_1   <= sig_i;
+			s_2   <= s_1;
+			sig_o <= s_2;
+		end if;
+	end process;
+end RTL;
+
+-- *************************************************** 
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+-- double sample sig_i signals to avoid metastable states
+entity DoubleSigInputSample is
+	port (
+		sig_i, clk_i: in std_logic;
+		sig_o: out std_logic );
+end DoubleSigInputSample;
+
+architecture RTL of DoubleSigInputSample is
+	signal s_1: std_logic;
+--	signal s_2: std_logic;
+begin
+	process(clk_i)
+	begin
+		if rising_edge(clk_i) then
+			s_1     <= sig_i;
+			sig_o   <= s_1;
+		end if;
+	end process;
+end RTL;
+--***************************************************
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+entity SingleRegInputSample is 
+	generic(
+		width: natural:=8
+		);
+	port (
+		reg_i: in std_logic_vector(width-1 downto 0);
+		reg_o: out std_logic_vector(width-1 downto 0);
+		clk_i: in std_logic 
+		);
+end SingleRegInputSample;
+
+architecture RTL of SingleRegInputSample is
+begin
+	process(clk_i)
+	begin
+		if rising_edge(clk_i) then
+			reg_o <= reg_i;		 
+		end if;
+	end process;
+end RTL;
+-- ***************************************************
+--FlipFlopD
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+entity FlipFlopD is
+	port (
+		reset, sig_i, clk_i, enable: in std_logic;
+		sig_o: out std_logic );
+end FlipFlopD;
+
+architecture RTL of FlipFlopD is
+--	signal s_1: std_logic;
+--	signal s_2: std_logic;
+begin
+	process(clk_i)
+	begin
+		if rising_edge(clk_i) then
+		   if reset = '1' then
+			   sig_o <= '0';
+			elsif enable = '1' then	
+			sig_o     <= sig_i;
+			--sig_o   <= s_1;
+		   end if;
+		end if;	
+	end process;
+end RTL;
+--Register 32 bits
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+entity Reg32bit is
+	port (
+		reset, clk_i, enable: in std_logic;
+		di : in std_logic_vector(31 downto 0);
+		do: out std_logic_vector(31 downto 0)
+		);
+end Reg32bit;
+architecture RTL of Reg32bit is
+--signal s_reg : std_logic_vector(31 downto 0);
+begin
+	process(clk_i)
+	begin
+		if rising_edge(clk_i) then
+		   if reset = '0' then 
+			     do <= (others => '0');
+				  --s_reg <= (others => '0');
+			elsif enable = '1' then	
+			     do <= di;
+			--s_reg <= di;
+			end if;
+		end if;	
+		--do <= s_reg;
+	end process;
+end RTL;
+
+--
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+-- detect rising edge
+entity RisEdgeDetection is
+	port (
+		sig_i, clk_i: in std_logic;
+		RisEdge_o: out std_logic );
+end RisEdgeDetection;
+
+architecture RTL of RisEdgeDetection is
+	signal s_1: std_logic;
+begin
+	process(clk_i)
+	begin
+		if rising_edge(clk_i) then
+			
+			s_1 <= sig_i;
+			
+			if s_1 = '0' and sig_i = '1' then
+				RisEdge_o <= '1';
+			else
+				RisEdge_o <= '0';
+			end if;
+			
+		end if;
+	end process;
+end RTL;   
+
+-- ***************************************************   
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+-- detect falling edge
+entity FallingEdgeDetection is
+	port (
+		sig_i, clk_i: in std_logic;
+		FallEdge_o: out std_logic );
+end FallingEdgeDetection;
+
+architecture RTL of FallingEdgeDetection is
+	signal s_1: std_logic;
+begin
+	process(clk_i)
+	begin
+		if rising_edge(clk_i) then
+			
+			s_1 <= sig_i;
+			
+			if s_1 = '1' and sig_i = '0' then
+				FallEdge_o <= '1';
+			else
+				FallEdge_o <= '0';
+			end if;
+			
+		end if;
+	end process;
+end RTL;
+
+-- ***************************************************
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+-- give pulse (sigEdge_o) at rising and falling edge
+entity EdgeDetection is
+	port (
+		sig_i, 
+		clk_i: in std_logic;
+		sigEdge_o: out std_logic
+		);
+end EdgeDetection;
+
+architecture RTL of EdgeDetection is
+	signal s_1: std_logic;
+begin
+	process(clk_i)
+	begin
+		if rising_edge(clk_i) then
+			
+			s_1 <= sig_i;
+			
+			if (s_1 = '0' and sig_i = '1') or (s_1 = '1' and sig_i = '0') then
+				sigEdge_o <= '1';
+			else
+				sigEdge_o <= '0';
+			end if;
+			
+		end if;
+	end process;
+end RTL;
+
+-- ***************************************************
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+-- triple sample input register reg_i to avoid metastable states
+-- and catching of transition values
+entity RegInputSample is 
+	generic(
+		width: natural:=8
+		);
+	port (
+		reg_i: in std_logic_vector(width-1 downto 0);
+		reg_o: out std_logic_vector(width-1 downto 0);
+		clk_i: in std_logic 
+		);
+end RegInputSample;
+
+architecture RTL of RegInputSample is
+	signal reg_1, reg_2: std_logic_vector(width-1 downto 0);
+begin
+	process(clk_i)
+	begin
+		if rising_edge(clk_i) then
+			reg_1 <= reg_i;
+			reg_2 <= reg_1;	
+			reg_o <= reg_2;	 
+
+		end if;
+	end process;
+end RTL;
+
+
+-- ***************************************************
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+-- triple sample input register reg_i to avoid metastable states
+-- and catching of transition values
+entity DoubleRegInputSample is 
+	generic(
+		width: natural:=8
+		);
+	port (
+		reg_i: in std_logic_vector(width-1 downto 0);
+		reg_o: out std_logic_vector(width-1 downto 0);
+		clk_i: in std_logic 
+		);
+end DoubleRegInputSample;
+
+architecture RTL of DoubleRegInputSample is
+	signal reg_1, reg_2: std_logic_vector(width-1 downto 0);
+begin
+	process(clk_i)
+	begin
+		if rising_edge(clk_i) then
+			reg_1 <= reg_i;
+			reg_o <= reg_1;		 
+
+		end if;
+	end process;
+end RTL;
\ No newline at end of file
--- a/ip_cores/VMEcore/VME_Wb_master.vhd
+++ b/ip_cores/VMEcore/VME_Wb_master.vhd
--- a/ip_cores/VMEcore/VME_bus.vhd
+++ b/ip_cores/VMEcore/VME_bus.vhd
--- a/ip_cores/VMEcore/VME_swapper.vhd
+++ b/ip_cores/VMEcore/VME_swapper.vhd
+--______________________________________________________________________________
+--                             VME TO WB INTERFACE
+--
+--                                CERN,BE/CO-HT 
+--______________________________________________________________________________
+-- File:                           VME_swapper.vhd
+--______________________________________________________________________________
+-- Description: 
+--sel= 00 --> No swap
+--sel= 01 --> Swap Byte            eg: 01234567 became 10325476
+--sel= 10 --> Swap Word            eg: 01234567 became 23016745
+--sel= 11 --> Swap Word+ Swap Byte eg: 01234567 became 32107654
+--______________________________________________________________________________
+-- Authors:                                                                    
+--               Davide Pedretti       (Davide.Pedretti@cern.ch)  
+-- Date         11/2012                                                                           
+-- Version      v0.03  
+--______________________________________________________________________________
+--                               GNU LESSER GENERAL PUBLIC LICENSE                                
+--                              ------------------------------------    
+-- Copyright (c) 2009 - 2011 CERN                           
+-- This source file is free software; you can redistribute it and/or modify it 
+-- under the terms of the GNU Lesser General Public License as published by the 
+-- Free Software Foundation; either version 2.1 of the License, or (at your option) 
+-- any later version. This source is distributed in the hope that it will be useful, 
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for 
+-- more details. You should have received a copy of the GNU Lesser General Public 
+-- License along with this source; if not, download it from 
+-- http://www.gnu.org/licenses/lgpl-2.1.html                     
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+--===========================================================================
+-- Entity declaration
+--===========================================================================
+entity VME_swapper is
+    Port ( d_i : in  STD_LOGIC_VECTOR (63 downto 0);
+	        sel : in  STD_LOGIC_VECTOR (2 downto 0);
+           d_o : out  STD_LOGIC_VECTOR (63 downto 0));
+end VME_swapper;
+--===========================================================================
+-- Architecture declaration
+--===========================================================================
+architecture Behavioral of VME_swapper is
+signal Byte0_i : std_logic_vector(7 downto 0);
+signal Byte1_i : std_logic_vector(7 downto 0);
+signal Byte2_i : std_logic_vector(7 downto 0);
+signal Byte3_i : std_logic_vector(7 downto 0);
+signal Byte4_i : std_logic_vector(7 downto 0);
+signal Byte5_i : std_logic_vector(7 downto 0);
+signal Byte6_i : std_logic_vector(7 downto 0);
+signal Byte7_i : std_logic_vector(7 downto 0);
+signal Byte0_o : std_logic_vector(7 downto 0);
+signal Byte1_o : std_logic_vector(7 downto 0);
+signal Byte2_o : std_logic_vector(7 downto 0);
+signal Byte3_o : std_logic_vector(7 downto 0);
+signal Byte4_o : std_logic_vector(7 downto 0);
+signal Byte5_o : std_logic_vector(7 downto 0);
+signal Byte6_o : std_logic_vector(7 downto 0);
+signal Byte7_o : std_logic_vector(7 downto 0);
+--===========================================================================
+-- Architecture begin
+--===========================================================================
+begin
+
+process (sel,Byte0_i,Byte1_i,Byte2_i,Byte3_i,Byte7_i)
+begin
+   case sel is
+      when "000"  => Byte0_o <= Byte0_i;
+      when "001"  => Byte0_o <= Byte1_i;
+      when "010"  => Byte0_o <= Byte2_i;
+      when "011"  => Byte0_o <= Byte3_i;
+		when "100"  => Byte0_o <= Byte7_i;
+      when others => Byte0_o <= Byte0_i;
+   end case;
+end process;
+
+process (sel,Byte0_i,Byte1_i,Byte2_i,Byte3_i,Byte6_i)
+begin
+   case sel is
+      when "000"  => Byte1_o <= Byte1_i;
+      when "001"  => Byte1_o <= Byte0_i;
+      when "010"  => Byte1_o <= Byte3_i;
+      when "011"  => Byte1_o <= Byte2_i;
+		when "100"  => Byte1_o <= Byte6_i;
+      when others => Byte1_o <= Byte1_i;
+   end case;
+end process;
+
+process (sel,Byte0_i,Byte1_i,Byte2_i,Byte3_i,Byte5_i)
+begin
+   case sel is
+      when "000"   => Byte2_o   <= Byte2_i;
+      when "001"   => Byte2_o   <= Byte3_i;
+      when "010"   => Byte2_o   <= Byte0_i;
+      when "011"   => Byte2_o   <= Byte1_i;
+		when "100"   => Byte2_o   <= Byte5_i;
+      when others  => Byte2_o   <= Byte2_i;
+   end case;
+end process;
+
+process (sel,Byte0_i,Byte1_i,Byte2_i,Byte3_i,Byte4_i)
+begin
+   case sel is
+      when "000"  => Byte3_o <= Byte3_i;
+      when "001"  => Byte3_o <= Byte2_i;
+      when "010"  => Byte3_o <= Byte1_i;
+      when "011"  => Byte3_o <= Byte0_i;
+		when "100"  => Byte3_o <= Byte4_i;
+      when others => Byte3_o <= Byte3_i;
+   end case;
+end process;
+
+process (sel,Byte4_i,Byte5_i,Byte6_i,Byte7_i,Byte3_i)
+begin
+   case sel is
+      when "000"  => Byte4_o <= Byte4_i;
+      when "001"  => Byte4_o <= Byte5_i;
+      when "010"  => Byte4_o <= Byte6_i;
+      when "011"  => Byte4_o <= Byte7_i;
+		when "100"  => Byte4_o <= Byte3_i;
+      when others => Byte4_o <= Byte4_i;
+   end case;
+end process;
+
+process (sel,Byte4_i,Byte5_i,Byte6_i,Byte7_i,Byte2_i)
+begin
+   case sel is
+      when "000"  => Byte5_o <= Byte5_i;
+      when "001"  => Byte5_o <= Byte4_i;
+      when "010"  => Byte5_o <= Byte7_i;
+      when "011"  => Byte5_o <= Byte6_i;
+		when "100"  => Byte5_o <= Byte2_i;
+      when others => Byte5_o <= Byte5_i;
+   end case;
+end process;
+
+process (sel,Byte4_i,Byte5_i,Byte6_i,Byte7_i,Byte1_i)
+begin
+   case sel is
+      when "000"  => Byte6_o <= Byte6_i;
+      when "001"  => Byte6_o <= Byte7_i;
+      when "010"  => Byte6_o <= Byte4_i;
+      when "011"  => Byte6_o <= Byte5_i;
+		when "100"  => Byte6_o <= Byte1_i;
+      when others => Byte6_o <= Byte6_i;
+   end case;
+end process;
+
+process (sel,Byte4_i,Byte5_i,Byte6_i,Byte7_i,Byte0_i)
+begin
+   case sel is
+      when "000"  => Byte7_o <= Byte7_i;
+      when "001"  => Byte7_o <= Byte6_i;
+      when "010"  => Byte7_o <= Byte5_i;
+      when "011"  => Byte7_o <= Byte4_i;
+		when "100"  => Byte7_o <= Byte0_i;
+      when others => Byte7_o <= Byte7_i;
+   end case;
+end process;
+
+Byte0_i           <= d_i(7 downto 0);
+Byte1_i           <= d_i(15 downto 8);
+Byte2_i           <= d_i(23 downto 16);
+Byte3_i           <= d_i(31 downto 24);
+Byte4_i           <= d_i(39 downto 32);
+Byte5_i           <= d_i(47 downto 40);
+Byte6_i           <= d_i(55 downto 48);
+Byte7_i           <= d_i(63 downto 56);
+d_o(7 downto 0)   <= Byte0_o;
+d_o(15 downto 8)  <= Byte1_o;
+d_o(23 downto 16) <= Byte2_o;
+d_o(31 downto 24) <= Byte3_o;
+d_o(39 downto 32) <= Byte4_o;
+d_o(47 downto 40) <= Byte5_o;
+d_o(55 downto 48) <= Byte6_o;
+d_o(63 downto 56) <= Byte7_o;
+
+end Behavioral;
+--===========================================================================
+-- Architecture end
+--===========================================================================
--- a/ip_cores/VMEcore/vme64x_pack.vhd
+++ b/ip_cores/VMEcore/vme64x_pack.vhd
--- a/ip_cores/common/Manifest.py
+++ b/ip_cores/common/Manifest.py
+files = [	"gencores_pkg.vhd",
+                "gc_crc_gen.vhd",
+                "gc_moving_average.vhd",
+                "gc_extend_pulse.vhd",
+                "gc_delay_gen.vhd",
+                "gc_dual_pi_controller.vhd",
+                "gc_reset.vhd",
+                "gc_serial_dac.vhd",
+                "gc_sync_ffs.vhd",
+                "gc_arbitrated_mux.vhd",
+                "gc_pulse_synchronizer.vhd",
+                "gc_frequency_meter.vhd",
+                "gc_dual_clock_ram.vhd",
+                "gc_wfifo.vhd"];
--- a/ip_cores/common/gc_arbitrated_mux.vhd
+++ b/ip_cores/common/gc_arbitrated_mux.vhd
--- a/ip_cores/common/gc_big_adder.vhd
+++ b/ip_cores/common/gc_big_adder.vhd
--- a/ip_cores/common/gc_crc_gen.vhd
+++ b/ip_cores/common/gc_crc_gen.vhd
--- a/ip_cores/common/gc_delay_gen.vhd
+++ b/ip_cores/common/gc_delay_gen.vhd
+-------------------------------------------------------------------------------
+-- Title      : Simple delay line generator
+-- Project    : White Rabbit
+-------------------------------------------------------------------------------
+-- File       : gc_delay_gen.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-Co-HT
+-- Created    : 2010-02-25
+-- Last update: 2011-04-29
+-- Platform   : FPGA-generic
+-- Standard   : VHDL '87
+------------------------------------------------------------------------------
+-- Description: Simple N-bit delay line with programmable delay.
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2009 - 2010 CERN
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author          Description
+-- 2010-02-25  1.0      twlostow        Created
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use work.gencores_pkg.all;
+
+entity gc_delay_gen is
+  generic(
+    g_delay_cycles : in natural;
+    g_data_width   : in natural
+    );
+
+  port(clk_i   : in  std_logic;  
+       rst_n_i : in  std_logic;  
+       d_i     : in  std_logic_vector(g_data_width - 1 downto 0);
+       q_o     : out std_logic_vector(g_data_width - 1 downto 0)
+       );
+end gc_delay_gen;
+
+
+architecture behavioral of gc_delay_gen is
+
+  type t_dly_array is array (0 to g_delay_cycles) of std_logic_vector(g_data_width -1 downto 0);
+  signal dly : t_dly_array;
+begin  -- behavioral
+
+  p_delay_proc : process (clk_i, rst_n_i)
+  begin  -- process delay_proc
+    if rst_n_i = '0' then               -- asynchronous reset (active low)
+      genrst : for i in 1 to g_delay_cycles loop
+        dly(i) <= (others => '0');
+      end loop;
+    elsif rising_edge(clk_i) then       -- rising clock edge
+      dly(0) <= d_i;
+      gendly : for i in 0 to g_delay_cycles-1 loop
+        dly(i+1) <= dly(i);
+      end loop;
+    end if;
+  end process p_delay_proc;
+
+  q_o <= dly(g_delay_cycles);
+  
+end behavioral;
--- a/ip_cores/common/gc_dual_clock_ram.vhd
+++ b/ip_cores/common/gc_dual_clock_ram.vhd
--- a/ip_cores/common/gc_dual_pi_controller.vhd
+++ b/ip_cores/common/gc_dual_pi_controller.vhd
--- a/ip_cores/common/gc_extend_pulse.vhd
+++ b/ip_cores/common/gc_extend_pulse.vhd
--- a/ip_cores/common/gc_frequency_meter.vhd
+++ b/ip_cores/common/gc_frequency_meter.vhd
--- a/ip_cores/common/gc_fsm_watchdog.vhd
+++ b/ip_cores/common/gc_fsm_watchdog.vhd
--- a/ip_cores/common/gc_glitch_filt.vhd
+++ b/ip_cores/common/gc_glitch_filt.vhd
--- a/ip_cores/common/gc_i2c_slave.vhd
+++ b/ip_cores/common/gc_i2c_slave.vhd
--- a/ip_cores/common/gc_moving_average.vhd
+++ b/ip_cores/common/gc_moving_average.vhd
--- a/ip_cores/common/gc_prio_encoder.vhd
+++ b/ip_cores/common/gc_prio_encoder.vhd
--- a/ip_cores/common/gc_pulse_synchronizer.vhd
+++ b/ip_cores/common/gc_pulse_synchronizer.vhd
--- a/ip_cores/common/gc_pulse_synchronizer2.vhd
+++ b/ip_cores/common/gc_pulse_synchronizer2.vhd
--- a/ip_cores/common/gc_reset.vhd
+++ b/ip_cores/common/gc_reset.vhd
--- a/ip_cores/common/gc_rr_arbiter.vhd
+++ b/ip_cores/common/gc_rr_arbiter.vhd
--- a/ip_cores/common/gc_serial_dac.vhd
+++ b/ip_cores/common/gc_serial_dac.vhd
--- a/ip_cores/common/gc_sync_ffs.vhd
+++ b/ip_cores/common/gc_sync_ffs.vhd
--- a/ip_cores/common/gc_wfifo.vhd
+++ b/ip_cores/common/gc_wfifo.vhd
--- a/ip_cores/common/gc_word_packer.vhd
+++ b/ip_cores/common/gc_word_packer.vhd
--- a/ip_cores/common/gencores_pkg.vhd
+++ b/ip_cores/common/gencores_pkg.vhd
--- a/ip_cores/genrams/.gitignore
+++ b/ip_cores/genrams/.gitignore
+coregen_ip
\ No newline at end of file
--- a/ip_cores/genrams/Manifest.py
+++ b/ip_cores/genrams/Manifest.py
+
+files = [
+	"genram_pkg.vhd", 
+	"memory_loader_pkg.vhd", 
+	"generic_shiftreg_fifo.vhd",
+	"inferred_sync_fifo.vhd",
+	"inferred_async_fifo.vhd"];
+
+if (target == "altera"):
+	modules = {"local" : "altera"}
+elif (target == "xilinx" and syn_device[0:4].upper()=="XC6V"):
+	modules = {"local" : ["xilinx", "xilinx/virtex6"]}
+elif (target == "xilinx"):
+	modules = {"local" : ["xilinx", "generic"]}
--- a/ip_cores/genrams/altera/Manifest.py
+++ b/ip_cores/genrams/altera/Manifest.py
+files = [
+"generic_async_fifo.vhd",
+"generic_simple_dpram.vhd",
+"generic_dpram.vhd",
+"generic_spram.vhd",
+"generic_sync_fifo.vhd",
+"gc_shiftreg.vhd"]
--- a/ip_cores/genrams/altera/gc_shiftreg.vhd
+++ b/ip_cores/genrams/altera/gc_shiftreg.vhd
--- a/ip_cores/genrams/altera/generic_async_fifo.vhd
+++ b/ip_cores/genrams/altera/generic_async_fifo.vhd
--- a/ip_cores/genrams/altera/generic_dpram.vhd
+++ b/ip_cores/genrams/altera/generic_dpram.vhd
--- a/ip_cores/genrams/altera/generic_simple_dpram.vhd
+++ b/ip_cores/genrams/altera/generic_simple_dpram.vhd
--- a/ip_cores/genrams/altera/generic_spram.vhd
+++ b/ip_cores/genrams/altera/generic_spram.vhd
--- a/ip_cores/genrams/altera/generic_sync_fifo.vhd
+++ b/ip_cores/genrams/altera/generic_sync_fifo.vhd
--- a/ip_cores/genrams/generic/Manifest.py
+++ b/ip_cores/genrams/generic/Manifest.py
+files = ["generic_async_fifo.vhd",
+"generic_sync_fifo.vhd"]
--- a/ip_cores/genrams/generic/generic_async_fifo.vhd
+++ b/ip_cores/genrams/generic/generic_async_fifo.vhd
--- a/ip_cores/genrams/generic/generic_sync_fifo.vhd
+++ b/ip_cores/genrams/generic/generic_sync_fifo.vhd
--- a/ip_cores/genrams/generic_shiftreg_fifo.vhd
+++ b/ip_cores/genrams/generic_shiftreg_fifo.vhd
--- a/ip_cores/genrams/genram_pkg.vhd
+++ b/ip_cores/genrams/genram_pkg.vhd
--- a/ip_cores/genrams/inferred_async_fifo.vhd
+++ b/ip_cores/genrams/inferred_async_fifo.vhd
--- a/ip_cores/genrams/inferred_sync_fifo.vhd
+++ b/ip_cores/genrams/inferred_sync_fifo.vhd
--- a/ip_cores/genrams/memory_loader_pkg.vhd
+++ b/ip_cores/genrams/memory_loader_pkg.vhd
--- a/ip_cores/genrams/xilinx/Manifest.py
+++ b/ip_cores/genrams/xilinx/Manifest.py
+files = [
+"generic_dpram.vhd",
+"generic_dpram_sameclock.vhd",
+"generic_dpram_dualclock.vhd",
+"generic_simple_dpram.vhd",
+"generic_spram.vhd",
+"gc_shiftreg.vhd"]
+
--- a/ip_cores/genrams/xilinx/gc_shiftreg.vhd
+++ b/ip_cores/genrams/xilinx/gc_shiftreg.vhd
--- a/ip_cores/genrams/xilinx/generic_dpram.vhd
+++ b/ip_cores/genrams/xilinx/generic_dpram.vhd
--- a/ip_cores/genrams/xilinx/generic_dpram_dualclock.vhd
+++ b/ip_cores/genrams/xilinx/generic_dpram_dualclock.vhd
--- a/ip_cores/genrams/xilinx/generic_dpram_sameclock.vhd
+++ b/ip_cores/genrams/xilinx/generic_dpram_sameclock.vhd
--- a/ip_cores/genrams/xilinx/generic_simple_dpram.vhd
+++ b/ip_cores/genrams/xilinx/generic_simple_dpram.vhd
--- a/ip_cores/genrams/xilinx/generic_spram.vhd
+++ b/ip_cores/genrams/xilinx/generic_spram.vhd
--- a/ip_cores/genrams/xilinx/virtex6/Manifest.py
+++ b/ip_cores/genrams/xilinx/virtex6/Manifest.py
+files =["v6_fifo_pkg.vhd", "v6_hwfifo_wrapper.vhd", "generic_async_fifo.vhd", "generic_sync_fifo.vhd"];
--- a/ip_cores/genrams/xilinx/virtex6/generic_async_fifo.vhd
+++ b/ip_cores/genrams/xilinx/virtex6/generic_async_fifo.vhd
--- a/ip_cores/genrams/xilinx/virtex6/generic_sync_fifo.vhd
+++ b/ip_cores/genrams/xilinx/virtex6/generic_sync_fifo.vhd
--- a/ip_cores/genrams/xilinx/virtex6/v6_fifo_pkg.vhd
+++ b/ip_cores/genrams/xilinx/virtex6/v6_fifo_pkg.vhd
--- a/ip_cores/genrams/xilinx/virtex6/v6_hwfifo_wrapper.vhd
+++ b/ip_cores/genrams/xilinx/virtex6/v6_hwfifo_wrapper.vhd
--- a/ip_cores/gnum_core/Manifest.py
+++ b/ip_cores/gnum_core/Manifest.py
--- a/ip_cores/gnum_core/dma_controller.vhd
+++ b/ip_cores/gnum_core/dma_controller.vhd
--- a/ip_cores/gnum_core/dma_controller_wb_slave.vhd
+++ b/ip_cores/gnum_core/dma_controller_wb_slave.vhd
--- a/ip_cores/gnum_core/l2p_arbiter.vhd
+++ b/ip_cores/gnum_core/l2p_arbiter.vhd
--- a/ip_cores/gnum_core/l2p_dma_master.vhd
+++ b/ip_cores/gnum_core/l2p_dma_master.vhd
--- a/ip_cores/gnum_core/obs/dma_controller.vhd
+++ b/ip_cores/gnum_core/obs/dma_controller.vhd
--- a/ip_cores/gnum_core/obs/dma_controller_wb_slave.vhd
+++ b/ip_cores/gnum_core/obs/dma_controller_wb_slave.vhd
--- a/ip_cores/gnum_core/obs/genram_pkg.vhd
+++ b/ip_cores/gnum_core/obs/genram_pkg.vhd
--- a/ip_cores/gnum_core/obs/gn4124_core.vhd
+++ b/ip_cores/gnum_core/obs/gn4124_core.vhd
--- a/ip_cores/gnum_core/obs/gn4124_core_pkg.vhd
+++ b/ip_cores/gnum_core/obs/gn4124_core_pkg.vhd
--- a/ip_cores/gnum_core/obs/l2p_arbiter.vhd
+++ b/ip_cores/gnum_core/obs/l2p_arbiter.vhd
--- a/ip_cores/gnum_core/obs/l2p_dma_master.vhd
+++ b/ip_cores/gnum_core/obs/l2p_dma_master.vhd
--- a/ip_cores/gnum_core/obs/l2p_ser.vhd
+++ b/ip_cores/gnum_core/obs/l2p_ser.vhd
--- a/ip_cores/gnum_core/obs/p2l_decode32.vhd
+++ b/ip_cores/gnum_core/obs/p2l_decode32.vhd
--- a/ip_cores/gnum_core/obs/p2l_des.vhd
+++ b/ip_cores/gnum_core/obs/p2l_des.vhd
--- a/ip_cores/gnum_core/obs/p2l_dma_master.vhd
+++ b/ip_cores/gnum_core/obs/p2l_dma_master.vhd
--- a/ip_cores/gnum_core/obs/pulse_sync_rtl.vhd
+++ b/ip_cores/gnum_core/obs/pulse_sync_rtl.vhd
--- a/ip_cores/gnum_core/obs/serdes_1_to_n_clk_pll_s2_diff.vhd
+++ b/ip_cores/gnum_core/obs/serdes_1_to_n_clk_pll_s2_diff.vhd
--- a/ip_cores/gnum_core/obs/serdes_1_to_n_data_s2_se.vhd
+++ b/ip_cores/gnum_core/obs/serdes_1_to_n_data_s2_se.vhd
--- a/ip_cores/gnum_core/obs/serdes_n_to_1_s2_diff.vhd
+++ b/ip_cores/gnum_core/obs/serdes_n_to_1_s2_diff.vhd
--- a/ip_cores/gnum_core/obs/serdes_n_to_1_s2_se.vhd
+++ b/ip_cores/gnum_core/obs/serdes_n_to_1_s2_se.vhd
--- a/ip_cores/gnum_core/obs/wbmaster32.vhd
+++ b/ip_cores/gnum_core/obs/wbmaster32.vhd
--- a/ip_cores/gnum_core/obs/xilinx_cores/_xmsgs/pn_parser.xmsgs
+++ b/ip_cores/gnum_core/obs/xilinx_cores/_xmsgs/pn_parser.xmsgs
--- a/ip_cores/gnum_core/obs/xilinx_cores/coregen.cgc
+++ b/ip_cores/gnum_core/obs/xilinx_cores/coregen.cgc
--- a/ip_cores/gnum_core/obs/xilinx_cores/coregen.cgp
+++ b/ip_cores/gnum_core/obs/xilinx_cores/coregen.cgp
--- a/ip_cores/gnum_core/obs/xilinx_cores/fifo_32x512.gise
+++ b/ip_cores/gnum_core/obs/xilinx_cores/fifo_32x512.gise
--- a/ip_cores/gnum_core/obs/xilinx_cores/fifo_32x512.ncf
+++ b/ip_cores/gnum_core/obs/xilinx_cores/fifo_32x512.ncf
--- a/ip_cores/gnum_core/obs/xilinx_cores/fifo_32x512.ndf
+++ b/ip_cores/gnum_core/obs/xilinx_cores/fifo_32x512.ndf
--- a/ip_cores/gnum_core/obs/xilinx_cores/fifo_32x512.ngc
+++ b/ip_cores/gnum_core/obs/xilinx_cores/fifo_32x512.ngc
--- a/ip_cores/gnum_core/obs/xilinx_cores/fifo_32x512.vhd
+++ b/ip_cores/gnum_core/obs/xilinx_cores/fifo_32x512.vhd
--- a/ip_cores/gnum_core/obs/xilinx_cores/fifo_32x512.vho
+++ b/ip_cores/gnum_core/obs/xilinx_cores/fifo_32x512.vho
--- a/ip_cores/gnum_core/obs/xilinx_cores/fifo_32x512.xco
+++ b/ip_cores/gnum_core/obs/xilinx_cores/fifo_32x512.xco
--- a/ip_cores/gnum_core/obs/xilinx_cores/fifo_32x512.xise
+++ b/ip_cores/gnum_core/obs/xilinx_cores/fifo_32x512.xise
--- a/ip_cores/gnum_core/obs/xilinx_cores/fifo_64x512.gise
+++ b/ip_cores/gnum_core/obs/xilinx_cores/fifo_64x512.gise
--- a/ip_cores/gnum_core/obs/xilinx_cores/fifo_64x512.ncf
+++ b/ip_cores/gnum_core/obs/xilinx_cores/fifo_64x512.ncf
--- a/ip_cores/gnum_core/obs/xilinx_cores/fifo_64x512.ndf
+++ b/ip_cores/gnum_core/obs/xilinx_cores/fifo_64x512.ndf
--- a/ip_cores/gnum_core/obs/xilinx_cores/fifo_64x512.ngc
+++ b/ip_cores/gnum_core/obs/xilinx_cores/fifo_64x512.ngc
--- a/ip_cores/gnum_core/obs/xilinx_cores/fifo_64x512.vhd
+++ b/ip_cores/gnum_core/obs/xilinx_cores/fifo_64x512.vhd
--- a/ip_cores/gnum_core/obs/xilinx_cores/fifo_64x512.vho
+++ b/ip_cores/gnum_core/obs/xilinx_cores/fifo_64x512.vho
--- a/ip_cores/gnum_core/obs/xilinx_cores/fifo_64x512.xco
+++ b/ip_cores/gnum_core/obs/xilinx_cores/fifo_64x512.xco
--- a/ip_cores/gnum_core/obs/xilinx_cores/fifo_64x512.xise
+++ b/ip_cores/gnum_core/obs/xilinx_cores/fifo_64x512.xise
--- a/ip_cores/gnum_core/obs/xilinx_cores/generic_async_fifo_wrapper.vhd
+++ b/ip_cores/gnum_core/obs/xilinx_cores/generic_async_fifo_wrapper.vhd
--- a/ip_cores/gnum_core/obs/xilinx_cores/ngc2edif.log
+++ b/ip_cores/gnum_core/obs/xilinx_cores/ngc2edif.log
--- a/ip_cores/gnum_core/p2l_decode32.vhd
+++ b/ip_cores/gnum_core/p2l_decode32.vhd
--- a/ip_cores/gnum_core/p2l_dma_master.vhd
+++ b/ip_cores/gnum_core/p2l_dma_master.vhd
--- a/ip_cores/gnum_core/spartan6/Manifest.py
+++ b/ip_cores/gnum_core/spartan6/Manifest.py
--- a/ip_cores/gnum_core/spartan6/gn4124_core.vhd
+++ b/ip_cores/gnum_core/spartan6/gn4124_core.vhd
--- a/ip_cores/gnum_core/spartan6/gn4124_core_pkg.vhd
+++ b/ip_cores/gnum_core/spartan6/gn4124_core_pkg.vhd
--- a/ip_cores/gnum_core/spartan6/l2p_ser.vhd
+++ b/ip_cores/gnum_core/spartan6/l2p_ser.vhd
--- a/ip_cores/gnum_core/spartan6/p2l_des.vhd
+++ b/ip_cores/gnum_core/spartan6/p2l_des.vhd
--- a/ip_cores/gnum_core/spartan6/pulse_sync_rtl.vhd
+++ b/ip_cores/gnum_core/spartan6/pulse_sync_rtl.vhd
--- a/ip_cores/gnum_core/spartan6/serdes_1_to_n_clk_pll_s2_diff.vhd
+++ b/ip_cores/gnum_core/spartan6/serdes_1_to_n_clk_pll_s2_diff.vhd
--- a/ip_cores/gnum_core/spartan6/serdes_1_to_n_data_s2_se.vhd
+++ b/ip_cores/gnum_core/spartan6/serdes_1_to_n_data_s2_se.vhd
--- a/ip_cores/gnum_core/spartan6/serdes_n_to_1_s2_diff.vhd
+++ b/ip_cores/gnum_core/spartan6/serdes_n_to_1_s2_diff.vhd
--- a/ip_cores/gnum_core/spartan6/serdes_n_to_1_s2_se.vhd
+++ b/ip_cores/gnum_core/spartan6/serdes_n_to_1_s2_se.vhd
--- a/ip_cores/gnum_core/wbmaster32.vhd
+++ b/ip_cores/gnum_core/wbmaster32.vhd
--- a/ip_cores/mem_core/_xmsgs/pn_parser.xmsgs
+++ b/ip_cores/mem_core/_xmsgs/pn_parser.xmsgs
--- a/ip_cores/mem_core/blk_mem_circ_buff_v6_4.gise
+++ b/ip_cores/mem_core/blk_mem_circ_buff_v6_4.gise
--- a/ip_cores/mem_core/blk_mem_circ_buff_v6_4.ncf
+++ b/ip_cores/mem_core/blk_mem_circ_buff_v6_4.ncf
--- a/ip_cores/mem_core/blk_mem_circ_buff_v6_4.ndf
+++ b/ip_cores/mem_core/blk_mem_circ_buff_v6_4.ndf
--- a/ip_cores/mem_core/blk_mem_circ_buff_v6_4.ngc
+++ b/ip_cores/mem_core/blk_mem_circ_buff_v6_4.ngc
--- a/ip_cores/mem_core/blk_mem_circ_buff_v6_4.vhd
+++ b/ip_cores/mem_core/blk_mem_circ_buff_v6_4.vhd
--- a/ip_cores/mem_core/blk_mem_circ_buff_v6_4.vho
+++ b/ip_cores/mem_core/blk_mem_circ_buff_v6_4.vho
--- a/ip_cores/mem_core/blk_mem_circ_buff_v6_4.xco
+++ b/ip_cores/mem_core/blk_mem_circ_buff_v6_4.xco
--- a/ip_cores/mem_core/blk_mem_circ_buff_v6_4.xise
+++ b/ip_cores/mem_core/blk_mem_circ_buff_v6_4.xise
--- a/ip_cores/mem_core/blk_mem_circ_buff_v6_4_flist.txt
+++ b/ip_cores/mem_core/blk_mem_circ_buff_v6_4_flist.txt
--- a/ip_cores/mem_core/blk_mem_circ_buff_v6_4_xmdf.tcl
+++ b/ip_cores/mem_core/blk_mem_circ_buff_v6_4_xmdf.tcl
--- a/ip_cores/mem_core/blk_mem_gen_ds512.pdf
+++ b/ip_cores/mem_core/blk_mem_gen_ds512.pdf
--- a/ip_cores/mem_core/blk_mem_gen_readme.txt
+++ b/ip_cores/mem_core/blk_mem_gen_readme.txt
--- a/ip_cores/mem_core/blk_mem_gen_v6_1.gise
+++ b/ip_cores/mem_core/blk_mem_gen_v6_1.gise
--- a/ip_cores/mem_core/blk_mem_gen_v6_1.ncf
+++ b/ip_cores/mem_core/blk_mem_gen_v6_1.ncf
--- a/ip_cores/mem_core/blk_mem_gen_v6_1.ngc
+++ b/ip_cores/mem_core/blk_mem_gen_v6_1.ngc
--- a/ip_cores/mem_core/blk_mem_gen_v6_1.vhd
+++ b/ip_cores/mem_core/blk_mem_gen_v6_1.vhd
--- a/ip_cores/mem_core/blk_mem_gen_v6_1.vho
+++ b/ip_cores/mem_core/blk_mem_gen_v6_1.vho
--- a/ip_cores/mem_core/blk_mem_gen_v6_1.xco
+++ b/ip_cores/mem_core/blk_mem_gen_v6_1.xco
--- a/ip_cores/mem_core/blk_mem_gen_v6_1.xise
+++ b/ip_cores/mem_core/blk_mem_gen_v6_1.xise
--- a/ip_cores/mem_core/blk_mem_gen_v6_1_flist.txt
+++ b/ip_cores/mem_core/blk_mem_gen_v6_1_flist.txt
--- a/ip_cores/mem_core/blk_mem_gen_v6_1_xmdf.tcl
+++ b/ip_cores/mem_core/blk_mem_gen_v6_1_xmdf.tcl
--- a/ip_cores/mem_core/blk_mem_gen_v6_2.gise
+++ b/ip_cores/mem_core/blk_mem_gen_v6_2.gise
--- a/ip_cores/mem_core/blk_mem_gen_v6_2.ncf
+++ b/ip_cores/mem_core/blk_mem_gen_v6_2.ncf
--- a/ip_cores/mem_core/blk_mem_gen_v6_2.ngc
+++ b/ip_cores/mem_core/blk_mem_gen_v6_2.ngc
--- a/ip_cores/mem_core/blk_mem_gen_v6_2.vhd
+++ b/ip_cores/mem_core/blk_mem_gen_v6_2.vhd
--- a/ip_cores/mem_core/blk_mem_gen_v6_2.vho
+++ b/ip_cores/mem_core/blk_mem_gen_v6_2.vho
--- a/ip_cores/mem_core/blk_mem_gen_v6_2.xco
+++ b/ip_cores/mem_core/blk_mem_gen_v6_2.xco
--- a/ip_cores/mem_core/blk_mem_gen_v6_2.xise
+++ b/ip_cores/mem_core/blk_mem_gen_v6_2.xise
--- a/ip_cores/mem_core/blk_mem_gen_v6_2_flist.txt
+++ b/ip_cores/mem_core/blk_mem_gen_v6_2_flist.txt
--- a/ip_cores/mem_core/blk_mem_gen_v6_2_readme.txt
+++ b/ip_cores/mem_core/blk_mem_gen_v6_2_readme.txt
--- a/ip_cores/mem_core/blk_mem_gen_v6_2_xmdf.tcl
+++ b/ip_cores/mem_core/blk_mem_gen_v6_2_xmdf.tcl
--- a/ip_cores/mem_core/blk_mem_gen_v6_3.gise
+++ b/ip_cores/mem_core/blk_mem_gen_v6_3.gise
--- a/ip_cores/mem_core/blk_mem_gen_v6_3.ncf
+++ b/ip_cores/mem_core/blk_mem_gen_v6_3.ncf
--- a/ip_cores/mem_core/blk_mem_gen_v6_3.ngc
+++ b/ip_cores/mem_core/blk_mem_gen_v6_3.ngc
--- a/ip_cores/mem_core/blk_mem_gen_v6_3.vhd
+++ b/ip_cores/mem_core/blk_mem_gen_v6_3.vhd
--- a/ip_cores/mem_core/blk_mem_gen_v6_3.vho
+++ b/ip_cores/mem_core/blk_mem_gen_v6_3.vho
--- a/ip_cores/mem_core/blk_mem_gen_v6_3.xco
+++ b/ip_cores/mem_core/blk_mem_gen_v6_3.xco
--- a/ip_cores/mem_core/blk_mem_gen_v6_3.xise
+++ b/ip_cores/mem_core/blk_mem_gen_v6_3.xise
--- a/ip_cores/mem_core/blk_mem_gen_v6_3_flist.txt
+++ b/ip_cores/mem_core/blk_mem_gen_v6_3_flist.txt
--- a/ip_cores/mem_core/blk_mem_gen_v6_3_xmdf.tcl
+++ b/ip_cores/mem_core/blk_mem_gen_v6_3_xmdf.tcl
--- a/ip_cores/mem_core/circular_buffer_coregen.cgc
+++ b/ip_cores/mem_core/circular_buffer_coregen.cgc
--- a/ip_cores/mem_core/circular_buffer_coregen.cgp
+++ b/ip_cores/mem_core/circular_buffer_coregen.cgp
--- a/ip_cores/mem_core/coregen.cgp
+++ b/ip_cores/mem_core/coregen.cgp
--- a/ip_cores/mem_core/coregen.log
+++ b/ip_cores/mem_core/coregen.log
--- a/ip_cores/mem_core/ngc2edif.log
+++ b/ip_cores/mem_core/ngc2edif.log
--- a/ip_cores/mem_core/summary.log
+++ b/ip_cores/mem_core/summary.log
--- a/ip_cores/platform/Manifest.py
+++ b/ip_cores/platform/Manifest.py
--- a/ip_cores/platform/altera/Manifest.py
+++ b/ip_cores/platform/altera/Manifest.py
--- a/ip_cores/platform/altera/flash/Manifest.py
+++ b/ip_cores/platform/altera/flash/Manifest.py
--- a/ip_cores/platform/altera/flash/altera_flash_pkg.vhd
+++ b/ip_cores/platform/altera/flash/altera_flash_pkg.vhd
--- a/ip_cores/platform/altera/flash/altera_spi.vhd
+++ b/ip_cores/platform/altera/flash/altera_spi.vhd
--- a/ip_cores/platform/altera/flash/flash_top.vhd
+++ b/ip_cores/platform/altera/flash/flash_top.vhd
--- a/ip_cores/platform/altera/networks/.gitignore
+++ b/ip_cores/platform/altera/networks/.gitignore
--- a/ip_cores/platform/altera/networks/Manifest.py
+++ b/ip_cores/platform/altera/networks/Manifest.py
--- a/ip_cores/platform/altera/networks/altera_networks_pkg.vhd
+++ b/ip_cores/platform/altera/networks/altera_networks_pkg.vhd
--- a/ip_cores/platform/altera/networks/arria2gx.tcl
+++ b/ip_cores/platform/altera/networks/arria2gx.tcl
--- a/ip_cores/platform/altera/networks/arria2gx/dual_region.txt
+++ b/ip_cores/platform/altera/networks/arria2gx/dual_region.txt
--- a/ip_cores/platform/altera/networks/arria2gx/global_region.txt
+++ b/ip_cores/platform/altera/networks/arria2gx/global_region.txt
--- a/ip_cores/platform/altera/networks/arria2gx/single_region.txt
+++ b/ip_cores/platform/altera/networks/arria2gx/single_region.txt
--- a/ip_cores/platform/altera/networks/arria2gx_networks.qip
+++ b/ip_cores/platform/altera/networks/arria2gx_networks.qip
--- a/ip_cores/platform/altera/networks/arria5.tcl
+++ b/ip_cores/platform/altera/networks/arria5.tcl
--- a/ip_cores/platform/altera/networks/arria5/dual_region.txt
+++ b/ip_cores/platform/altera/networks/arria5/dual_region.txt
--- a/ip_cores/platform/altera/networks/arria5/global_region.txt
+++ b/ip_cores/platform/altera/networks/arria5/global_region.txt
--- a/ip_cores/platform/altera/networks/arria5/single_region.txt
+++ b/ip_cores/platform/altera/networks/arria5/single_region.txt
--- a/ip_cores/platform/altera/networks/arria5_networks.qip
+++ b/ip_cores/platform/altera/networks/arria5_networks.qip
--- a/ip_cores/platform/altera/wb_pcie/.gitignore
+++ b/ip_cores/platform/altera/wb_pcie/.gitignore
--- a/ip_cores/platform/altera/wb_pcie/Manifest.py
+++ b/ip_cores/platform/altera/wb_pcie/Manifest.py
--- a/ip_cores/platform/altera/wb_pcie/arria2.tcl
+++ b/ip_cores/platform/altera/wb_pcie/arria2.tcl
--- a/ip_cores/platform/altera/wb_pcie/arria2_pcie.qip
+++ b/ip_cores/platform/altera/wb_pcie/arria2_pcie.qip
--- a/ip_cores/platform/altera/wb_pcie/arria2_pcie_hip.txt
+++ b/ip_cores/platform/altera/wb_pcie/arria2_pcie_hip.txt
--- a/ip_cores/platform/altera/wb_pcie/arria2_pcie_reconf.txt
+++ b/ip_cores/platform/altera/wb_pcie/arria2_pcie_reconf.txt
--- a/ip_cores/platform/altera/wb_pcie/arria5.tcl
+++ b/ip_cores/platform/altera/wb_pcie/arria5.tcl
--- a/ip_cores/platform/altera/wb_pcie/arria5_pcie.qip
+++ b/ip_cores/platform/altera/wb_pcie/arria5_pcie.qip
--- a/ip_cores/platform/altera/wb_pcie/arria5_pcie_hip.txt
+++ b/ip_cores/platform/altera/wb_pcie/arria5_pcie_hip.txt
--- a/ip_cores/platform/altera/wb_pcie/arria5_pcie_reconf.txt
+++ b/ip_cores/platform/altera/wb_pcie/arria5_pcie_reconf.txt
--- a/ip_cores/platform/altera/wb_pcie/pcie_32to64.vhd
+++ b/ip_cores/platform/altera/wb_pcie/pcie_32to64.vhd
--- a/ip_cores/platform/altera/wb_pcie/pcie_64to32.vhd
+++ b/ip_cores/platform/altera/wb_pcie/pcie_64to32.vhd
--- a/ip_cores/platform/altera/wb_pcie/pcie_altera.vhd
+++ b/ip_cores/platform/altera/wb_pcie/pcie_altera.vhd
--- a/ip_cores/platform/altera/wb_pcie/pcie_tlp.vhd
+++ b/ip_cores/platform/altera/wb_pcie/pcie_tlp.vhd
--- a/ip_cores/platform/altera/wb_pcie/pcie_wb.vhd
+++ b/ip_cores/platform/altera/wb_pcie/pcie_wb.vhd
--- a/ip_cores/platform/altera/wb_pcie/pcie_wb_pkg.vhd
+++ b/ip_cores/platform/altera/wb_pcie/pcie_wb_pkg.vhd
--- a/ip_cores/platform/xilinx/Manifest.py
+++ b/ip_cores/platform/xilinx/Manifest.py
--- a/ip_cores/platform/xilinx/wb_xil_multiboot/Manifest.py
+++ b/ip_cores/platform/xilinx/wb_xil_multiboot/Manifest.py
--- a/ip_cores/platform/xilinx/wb_xil_multiboot/multiboot_fsm.vhd
+++ b/ip_cores/platform/xilinx/wb_xil_multiboot/multiboot_fsm.vhd
--- a/ip_cores/platform/xilinx/wb_xil_multiboot/multiboot_regs.vhd
+++ b/ip_cores/platform/xilinx/wb_xil_multiboot/multiboot_regs.vhd
--- a/ip_cores/platform/xilinx/wb_xil_multiboot/multiboot_regs.wb
+++ b/ip_cores/platform/xilinx/wb_xil_multiboot/multiboot_regs.wb
--- a/ip_cores/platform/xilinx/wb_xil_multiboot/spi_master.vhd
+++ b/ip_cores/platform/xilinx/wb_xil_multiboot/spi_master.vhd
--- a/ip_cores/platform/xilinx/wb_xil_multiboot/wb_xil_multiboot.vhd
+++ b/ip_cores/platform/xilinx/wb_xil_multiboot/wb_xil_multiboot.vhd
--- a/ip_cores/platform/xilinx/wb_xilinx_fpga_loader/Manifest.py
+++ b/ip_cores/platform/xilinx/wb_xilinx_fpga_loader/Manifest.py
--- a/ip_cores/platform/xilinx/wb_xilinx_fpga_loader/build_wb.sh
+++ b/ip_cores/platform/xilinx/wb_xilinx_fpga_loader/build_wb.sh
--- a/ip_cores/platform/xilinx/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd
+++ b/ip_cores/platform/xilinx/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd
--- a/ip_cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd
+++ b/ip_cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd
--- a/ip_cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.vhd
+++ b/ip_cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.vhd
--- a/ip_cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.wb
+++ b/ip_cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.wb
--- a/ip_cores/platform/xilinx/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd
+++ b/ip_cores/platform/xilinx/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd
--- a/ip_cores/svec_leds/bicolor_led_ctrl.vhd
+++ b/ip_cores/svec_leds/bicolor_led_ctrl.vhd
--- a/ip_cores/svec_leds/bicolor_led_ctrl_pkg.vhd
+++ b/ip_cores/svec_leds/bicolor_led_ctrl_pkg.vhd
--- a/ip_cores/wishbone/Manifest.py
+++ b/ip_cores/wishbone/Manifest.py
--- a/ip_cores/wishbone/carrier_csr.vhd
+++ b/ip_cores/wishbone/carrier_csr.vhd
--- a/ip_cores/wishbone/wb_async_bridge/Manifest.py
+++ b/ip_cores/wishbone/wb_async_bridge/Manifest.py
--- a/ip_cores/wishbone/wb_async_bridge/wb_async_bridge.vhd
+++ b/ip_cores/wishbone/wb_async_bridge/wb_async_bridge.vhd
--- a/ip_cores/wishbone/wb_async_bridge/xwb_async_bridge.vhd
+++ b/ip_cores/wishbone/wb_async_bridge/xwb_async_bridge.vhd
--- a/ip_cores/wishbone/wb_bus_fanout/Manifest.py
+++ b/ip_cores/wishbone/wb_bus_fanout/Manifest.py
--- a/ip_cores/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd
+++ b/ip_cores/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd
--- a/ip_cores/wishbone/wb_clock_crossing/Manifest.py
+++ b/ip_cores/wishbone/wb_clock_crossing/Manifest.py
--- a/ip_cores/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd
+++ b/ip_cores/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd
--- a/ip_cores/wishbone/wb_conmax/Manifest.py
+++ b/ip_cores/wishbone/wb_conmax/Manifest.py
--- a/ip_cores/wishbone/wb_conmax/wb_conmax_arb.vhd
+++ b/ip_cores/wishbone/wb_conmax/wb_conmax_arb.vhd
--- a/ip_cores/wishbone/wb_conmax/wb_conmax_master_if.vhd
+++ b/ip_cores/wishbone/wb_conmax/wb_conmax_master_if.vhd
--- a/ip_cores/wishbone/wb_conmax/wb_conmax_msel.vhd
+++ b/ip_cores/wishbone/wb_conmax/wb_conmax_msel.vhd
--- a/ip_cores/wishbone/wb_conmax/wb_conmax_pri_dec.vhd
+++ b/ip_cores/wishbone/wb_conmax/wb_conmax_pri_dec.vhd
--- a/ip_cores/wishbone/wb_conmax/wb_conmax_pri_enc.vhd
+++ b/ip_cores/wishbone/wb_conmax/wb_conmax_pri_enc.vhd
--- a/ip_cores/wishbone/wb_conmax/wb_conmax_rf.vhd
+++ b/ip_cores/wishbone/wb_conmax/wb_conmax_rf.vhd
--- a/ip_cores/wishbone/wb_conmax/wb_conmax_slave_if.vhd
+++ b/ip_cores/wishbone/wb_conmax/wb_conmax_slave_if.vhd
--- a/ip_cores/wishbone/wb_conmax/wb_conmax_top.vhd
+++ b/ip_cores/wishbone/wb_conmax/wb_conmax_top.vhd
--- a/ip_cores/wishbone/wb_conmax/wbconmax_pkg.vhd
+++ b/ip_cores/wishbone/wb_conmax/wbconmax_pkg.vhd
--- a/ip_cores/wishbone/wb_conmax/xwb_conmax.vhd
+++ b/ip_cores/wishbone/wb_conmax/xwb_conmax.vhd
--- a/ip_cores/wishbone/wb_crossbar/Manifest.py
+++ b/ip_cores/wishbone/wb_crossbar/Manifest.py
--- a/ip_cores/wishbone/wb_crossbar/sdb_rom.vhd
+++ b/ip_cores/wishbone/wb_crossbar/sdb_rom.vhd
--- a/ip_cores/wishbone/wb_crossbar/xwb_crossbar.vhd
+++ b/ip_cores/wishbone/wb_crossbar/xwb_crossbar.vhd
--- a/ip_cores/wishbone/wb_crossbar/xwb_register_link.vhd
+++ b/ip_cores/wishbone/wb_crossbar/xwb_register_link.vhd
--- a/ip_cores/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd
+++ b/ip_cores/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd
--- a/ip_cores/wishbone/wb_dma/Manifest.py
+++ b/ip_cores/wishbone/wb_dma/Manifest.py
--- a/ip_cores/wishbone/wb_dma/xwb_dma.vhd
+++ b/ip_cores/wishbone/wb_dma/xwb_dma.vhd
--- a/ip_cores/wishbone/wb_dma/xwb_streamer.vhd
+++ b/ip_cores/wishbone/wb_dma/xwb_streamer.vhd
--- a/ip_cores/wishbone/wb_dpram/Manifest.py
+++ b/ip_cores/wishbone/wb_dpram/Manifest.py
--- a/ip_cores/wishbone/wb_dpram/xwb_dpram.vhd
+++ b/ip_cores/wishbone/wb_dpram/xwb_dpram.vhd
--- a/ip_cores/wishbone/wb_gpio_port/Manifest.py
+++ b/ip_cores/wishbone/wb_gpio_port/Manifest.py
--- a/ip_cores/wishbone/wb_gpio_port/wb_gpio_port.vhd
+++ b/ip_cores/wishbone/wb_gpio_port/wb_gpio_port.vhd
--- a/ip_cores/wishbone/wb_gpio_port/xwb_gpio_port.vhd
+++ b/ip_cores/wishbone/wb_gpio_port/xwb_gpio_port.vhd
--- a/ip_cores/wishbone/wb_i2c_bridge/Manifest.py
+++ b/ip_cores/wishbone/wb_i2c_bridge/Manifest.py
--- a/ip_cores/wishbone/wb_i2c_bridge/wb_i2c_bridge.vhd
+++ b/ip_cores/wishbone/wb_i2c_bridge/wb_i2c_bridge.vhd
--- a/ip_cores/wishbone/wb_i2c_master/Manifest.py
+++ b/ip_cores/wishbone/wb_i2c_master/Manifest.py
--- a/ip_cores/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd
+++ b/ip_cores/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd
--- a/ip_cores/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd
+++ b/ip_cores/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd
--- a/ip_cores/wishbone/wb_i2c_master/i2c_master_top.vhd
+++ b/ip_cores/wishbone/wb_i2c_master/i2c_master_top.vhd
--- a/ip_cores/wishbone/wb_i2c_master/wb_i2c_master.vhd
+++ b/ip_cores/wishbone/wb_i2c_master/wb_i2c_master.vhd
--- a/ip_cores/wishbone/wb_i2c_master/xwb_i2c_master.vhd
+++ b/ip_cores/wishbone/wb_i2c_master/xwb_i2c_master.vhd
--- a/ip_cores/wishbone/wb_irq/Manifest.py
+++ b/ip_cores/wishbone/wb_irq/Manifest.py
--- a/ip_cores/wishbone/wb_irq/irqm_core.vhd
+++ b/ip_cores/wishbone/wb_irq/irqm_core.vhd
--- a/ip_cores/wishbone/wb_irq/msidemo/Makefile
+++ b/ip_cores/wishbone/wb_irq/msidemo/Makefile
--- a/ip_cores/wishbone/wb_irq/msidemo/crt0.S
+++ b/ip_cores/wishbone/wb_irq/msidemo/crt0.S
--- a/ip_cores/wishbone/wb_irq/msidemo/display.c
+++ b/ip_cores/wishbone/wb_irq/msidemo/display.c
--- a/ip_cores/wishbone/wb_irq/msidemo/display.h
+++ b/ip_cores/wishbone/wb_irq/msidemo/display.h
--- a/ip_cores/wishbone/wb_irq/msidemo/eca-msi.sh
+++ b/ip_cores/wishbone/wb_irq/msidemo/eca-msi.sh
--- a/ip_cores/wishbone/wb_irq/msidemo/irq.c
+++ b/ip_cores/wishbone/wb_irq/msidemo/irq.c
--- a/ip_cores/wishbone/wb_irq/msidemo/irq.h
+++ b/ip_cores/wishbone/wb_irq/msidemo/irq.h
--- a/ip_cores/wishbone/wb_irq/msidemo/linker.ld
+++ b/ip_cores/wishbone/wb_irq/msidemo/linker.ld
--- a/ip_cores/wishbone/wb_irq/msidemo/main.c
+++ b/ip_cores/wishbone/wb_irq/msidemo/main.c
--- a/ip_cores/wishbone/wb_irq/wb_irq_lm32.vhd
+++ b/ip_cores/wishbone/wb_irq/wb_irq_lm32.vhd
--- a/ip_cores/wishbone/wb_irq/wb_irq_master.vhd
+++ b/ip_cores/wishbone/wb_irq/wb_irq_master.vhd
--- a/ip_cores/wishbone/wb_irq/wb_irq_pkg.vhd
+++ b/ip_cores/wishbone/wb_irq/wb_irq_pkg.vhd
--- a/ip_cores/wishbone/wb_irq/wb_irq_slave.vhd
+++ b/ip_cores/wishbone/wb_irq/wb_irq_slave.vhd
--- a/ip_cores/wishbone/wb_irq/wb_irq_timer.vhd
+++ b/ip_cores/wishbone/wb_irq/wb_irq_timer.vhd
--- a/ip_cores/wishbone/wb_irq_controller/irq_controller.vhd
+++ b/ip_cores/wishbone/wb_irq_controller/irq_controller.vhd
--- a/ip_cores/wishbone/wb_irq_controller/irq_controller_regs.vhd
+++ b/ip_cores/wishbone/wb_irq_controller/irq_controller_regs.vhd
--- a/ip_cores/wishbone/wb_lm32/Manifest.py
+++ b/ip_cores/wishbone/wb_lm32/Manifest.py
--- a/ip_cores/wishbone/wb_lm32/README.txt
+++ b/ip_cores/wishbone/wb_lm32/README.txt
--- a/ip_cores/wishbone/wb_lm32/gen_lmcores.py
+++ b/ip_cores/wishbone/wb_lm32/gen_lmcores.py
--- a/ip_cores/wishbone/wb_lm32/generated/lm32_allprofiles.v
+++ b/ip_cores/wishbone/wb_lm32/generated/lm32_allprofiles.v
--- a/ip_cores/wishbone/wb_lm32/generated/xwb_lm32.vhd
+++ b/ip_cores/wishbone/wb_lm32/generated/xwb_lm32.vhd
--- a/ip_cores/wishbone/wb_lm32/lm32.profiles
+++ b/ip_cores/wishbone/wb_lm32/lm32.profiles
--- a/ip_cores/wishbone/wb_lm32/platform/altera/jtag_tap.v
+++ b/ip_cores/wishbone/wb_lm32/platform/altera/jtag_tap.v
--- a/ip_cores/wishbone/wb_lm32/platform/generic/jtag_tap.v
+++ b/ip_cores/wishbone/wb_lm32/platform/generic/jtag_tap.v
--- a/ip_cores/wishbone/wb_lm32/platform/generic/lm32_multiplier.v
+++ b/ip_cores/wishbone/wb_lm32/platform/generic/lm32_multiplier.v
--- a/ip_cores/wishbone/wb_lm32/platform/spartan6/jtag_tap.v
+++ b/ip_cores/wishbone/wb_lm32/platform/spartan6/jtag_tap.v
--- a/ip_cores/wishbone/wb_lm32/platform/spartan6/lm32_multiplier.v
+++ b/ip_cores/wishbone/wb_lm32/platform/spartan6/lm32_multiplier.v
--- a/ip_cores/wishbone/wb_lm32/src/jtag_cores.v
+++ b/ip_cores/wishbone/wb_lm32/src/jtag_cores.v
--- a/ip_cores/wishbone/wb_lm32/src/lm32_adder.v
+++ b/ip_cores/wishbone/wb_lm32/src/lm32_adder.v
--- a/ip_cores/wishbone/wb_lm32/src/lm32_addsub.v
+++ b/ip_cores/wishbone/wb_lm32/src/lm32_addsub.v
--- a/ip_cores/wishbone/wb_lm32/src/lm32_cpu.v
+++ b/ip_cores/wishbone/wb_lm32/src/lm32_cpu.v
--- a/ip_cores/wishbone/wb_lm32/src/lm32_dcache.v
+++ b/ip_cores/wishbone/wb_lm32/src/lm32_dcache.v
--- a/ip_cores/wishbone/wb_lm32/src/lm32_debug.v
+++ b/ip_cores/wishbone/wb_lm32/src/lm32_debug.v
--- a/ip_cores/wishbone/wb_lm32/src/lm32_decoder.v
+++ b/ip_cores/wishbone/wb_lm32/src/lm32_decoder.v
--- a/ip_cores/wishbone/wb_lm32/src/lm32_dp_ram.v
+++ b/ip_cores/wishbone/wb_lm32/src/lm32_dp_ram.v
--- a/ip_cores/wishbone/wb_lm32/src/lm32_dp_ram.vhd
+++ b/ip_cores/wishbone/wb_lm32/src/lm32_dp_ram.vhd
--- a/ip_cores/wishbone/wb_lm32/src/lm32_functions.v
+++ b/ip_cores/wishbone/wb_lm32/src/lm32_functions.v
--- a/ip_cores/wishbone/wb_lm32/src/lm32_icache.v
+++ b/ip_cores/wishbone/wb_lm32/src/lm32_icache.v
--- a/ip_cores/wishbone/wb_lm32/src/lm32_include.v
+++ b/ip_cores/wishbone/wb_lm32/src/lm32_include.v
--- a/ip_cores/wishbone/wb_lm32/src/lm32_instruction_unit.v
+++ b/ip_cores/wishbone/wb_lm32/src/lm32_instruction_unit.v
--- a/ip_cores/wishbone/wb_lm32/src/lm32_interrupt.v
+++ b/ip_cores/wishbone/wb_lm32/src/lm32_interrupt.v
--- a/ip_cores/wishbone/wb_lm32/src/lm32_jtag.v
+++ b/ip_cores/wishbone/wb_lm32/src/lm32_jtag.v
--- a/ip_cores/wishbone/wb_lm32/src/lm32_load_store_unit.v
+++ b/ip_cores/wishbone/wb_lm32/src/lm32_load_store_unit.v
--- a/ip_cores/wishbone/wb_lm32/src/lm32_logic_op.v
+++ b/ip_cores/wishbone/wb_lm32/src/lm32_logic_op.v
--- a/ip_cores/wishbone/wb_lm32/src/lm32_mc_arithmetic.v
+++ b/ip_cores/wishbone/wb_lm32/src/lm32_mc_arithmetic.v
--- a/ip_cores/wishbone/wb_lm32/src/lm32_ram.v
+++ b/ip_cores/wishbone/wb_lm32/src/lm32_ram.v
--- a/ip_cores/wishbone/wb_lm32/src/lm32_ram.vhd
+++ b/ip_cores/wishbone/wb_lm32/src/lm32_ram.vhd
--- a/ip_cores/wishbone/wb_lm32/src/lm32_shifter.v
+++ b/ip_cores/wishbone/wb_lm32/src/lm32_shifter.v
--- a/ip_cores/wishbone/wb_lm32/src/lm32_top.v
+++ b/ip_cores/wishbone/wb_lm32/src/lm32_top.v
--- a/ip_cores/wishbone/wb_onewire_master/Manifest.py
+++ b/ip_cores/wishbone/wb_onewire_master/Manifest.py
--- a/ip_cores/wishbone/wb_onewire_master/sockit_owm.v
+++ b/ip_cores/wishbone/wb_onewire_master/sockit_owm.v
--- a/ip_cores/wishbone/wb_onewire_master/wb_onewire_master.vhd
+++ b/ip_cores/wishbone/wb_onewire_master/wb_onewire_master.vhd
--- a/ip_cores/wishbone/wb_onewire_master/xwb_onewire_master.vhd
+++ b/ip_cores/wishbone/wb_onewire_master/xwb_onewire_master.vhd
--- a/ip_cores/wishbone/wb_serial_lcd/Manifest.py
+++ b/ip_cores/wishbone/wb_serial_lcd/Manifest.py
--- a/ip_cores/wishbone/wb_serial_lcd/wb_serial_lcd.vhd
+++ b/ip_cores/wishbone/wb_serial_lcd/wb_serial_lcd.vhd
--- a/ip_cores/wishbone/wb_simple_pwm/Manifest.py
+++ b/ip_cores/wishbone/wb_simple_pwm/Manifest.py
--- a/ip_cores/wishbone/wb_simple_pwm/simple_pwm_wb.vhd
+++ b/ip_cores/wishbone/wb_simple_pwm/simple_pwm_wb.vhd
--- a/ip_cores/wishbone/wb_simple_pwm/simple_pwm_wb.wb
+++ b/ip_cores/wishbone/wb_simple_pwm/simple_pwm_wb.wb
--- a/ip_cores/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd
+++ b/ip_cores/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd
--- a/ip_cores/wishbone/wb_simple_pwm/wb_simple_pwm.vhd
+++ b/ip_cores/wishbone/wb_simple_pwm/wb_simple_pwm.vhd
--- a/ip_cores/wishbone/wb_simple_pwm/xwb_simple_pwm.vhd
+++ b/ip_cores/wishbone/wb_simple_pwm/xwb_simple_pwm.vhd
--- a/ip_cores/wishbone/wb_simple_timer/Manifest.py
+++ b/ip_cores/wishbone/wb_simple_timer/Manifest.py
--- a/ip_cores/wishbone/wb_simple_timer/wb_tics.vhd
+++ b/ip_cores/wishbone/wb_simple_timer/wb_tics.vhd
--- a/ip_cores/wishbone/wb_simple_timer/xwb_tics.vhd
+++ b/ip_cores/wishbone/wb_simple_timer/xwb_tics.vhd
--- a/ip_cores/wishbone/wb_slave_adapter/Manifest.py
+++ b/ip_cores/wishbone/wb_slave_adapter/Manifest.py
--- a/ip_cores/wishbone/wb_slave_adapter/wb_slave_adapter.vhd
+++ b/ip_cores/wishbone/wb_slave_adapter/wb_slave_adapter.vhd
--- a/ip_cores/wishbone/wb_spi/Manifest.py
+++ b/ip_cores/wishbone/wb_spi/Manifest.py
--- a/ip_cores/wishbone/wb_spi/spi_clgen.v
+++ b/ip_cores/wishbone/wb_spi/spi_clgen.v
--- a/ip_cores/wishbone/wb_spi/spi_defines.v
+++ b/ip_cores/wishbone/wb_spi/spi_defines.v
--- a/ip_cores/wishbone/wb_spi/spi_shift.v
+++ b/ip_cores/wishbone/wb_spi/spi_shift.v
--- a/ip_cores/wishbone/wb_spi/spi_top.v
+++ b/ip_cores/wishbone/wb_spi/spi_top.v
--- a/ip_cores/wishbone/wb_spi/timescale.v
+++ b/ip_cores/wishbone/wb_spi/timescale.v
--- a/ip_cores/wishbone/wb_spi/wb_spi.vhd
+++ b/ip_cores/wishbone/wb_spi/wb_spi.vhd
--- a/ip_cores/wishbone/wb_spi/xwb_spi.vhd
+++ b/ip_cores/wishbone/wb_spi/xwb_spi.vhd
--- a/ip_cores/wishbone/wb_spi_flash/Manifest.py
+++ b/ip_cores/wishbone/wb_spi_flash/Manifest.py
--- a/ip_cores/wishbone/wb_spi_flash/wb_spi_flash.vhd
+++ b/ip_cores/wishbone/wb_spi_flash/wb_spi_flash.vhd
--- a/ip_cores/wishbone/wb_uart/Manifest.py
+++ b/ip_cores/wishbone/wb_uart/Manifest.py
--- a/ip_cores/wishbone/wb_uart/build_wb.sh
+++ b/ip_cores/wishbone/wb_uart/build_wb.sh
--- a/ip_cores/wishbone/wb_uart/simple_uart_pkg.vhd
+++ b/ip_cores/wishbone/wb_uart/simple_uart_pkg.vhd
--- a/ip_cores/wishbone/wb_uart/simple_uart_wb.vhd
+++ b/ip_cores/wishbone/wb_uart/simple_uart_wb.vhd
--- a/ip_cores/wishbone/wb_uart/simple_uart_wb.wb
+++ b/ip_cores/wishbone/wb_uart/simple_uart_wb.wb
--- a/ip_cores/wishbone/wb_uart/uart_async_rx.vhd
+++ b/ip_cores/wishbone/wb_uart/uart_async_rx.vhd
--- a/ip_cores/wishbone/wb_uart/uart_async_tx.vhd
+++ b/ip_cores/wishbone/wb_uart/uart_async_tx.vhd
--- a/ip_cores/wishbone/wb_uart/uart_baud_gen.vhd
+++ b/ip_cores/wishbone/wb_uart/uart_baud_gen.vhd
--- a/ip_cores/wishbone/wb_uart/uart_wb_slave.vhd
+++ b/ip_cores/wishbone/wb_uart/uart_wb_slave.vhd
--- a/ip_cores/wishbone/wb_uart/wb_simple_uart.vhd
+++ b/ip_cores/wishbone/wb_uart/wb_simple_uart.vhd
--- a/ip_cores/wishbone/wb_uart/xwb_simple_uart.vhd
+++ b/ip_cores/wishbone/wb_uart/xwb_simple_uart.vhd
--- a/ip_cores/wishbone/wb_vic/Manifest.py
+++ b/ip_cores/wishbone/wb_vic/Manifest.py
--- a/ip_cores/wishbone/wb_vic/vic_prio_enc.vhd
+++ b/ip_cores/wishbone/wb_vic/vic_prio_enc.vhd
--- a/ip_cores/wishbone/wb_vic/wb_slave_vic.vhd
+++ b/ip_cores/wishbone/wb_vic/wb_slave_vic.vhd
--- a/ip_cores/wishbone/wb_vic/wb_slave_vic.wb
+++ b/ip_cores/wishbone/wb_vic/wb_slave_vic.wb
--- a/ip_cores/wishbone/wb_vic/wb_vic.vhd
+++ b/ip_cores/wishbone/wb_vic/wb_vic.vhd
--- a/ip_cores/wishbone/wb_vic/xwb_vic.vhd
+++ b/ip_cores/wishbone/wb_vic/xwb_vic.vhd
--- a/ip_cores/wishbone/wbgen2/Manifest.py
+++ b/ip_cores/wishbone/wbgen2/Manifest.py
--- a/ip_cores/wishbone/wbgen2/wbgen2_dpssram.vhd
+++ b/ip_cores/wishbone/wbgen2/wbgen2_dpssram.vhd
--- a/ip_cores/wishbone/wbgen2/wbgen2_eic.vhd
+++ b/ip_cores/wishbone/wbgen2/wbgen2_eic.vhd
--- a/ip_cores/wishbone/wbgen2/wbgen2_fifo_async.vhd
+++ b/ip_cores/wishbone/wbgen2/wbgen2_fifo_async.vhd
--- a/ip_cores/wishbone/wbgen2/wbgen2_fifo_sync.vhd
+++ b/ip_cores/wishbone/wbgen2/wbgen2_fifo_sync.vhd
--- a/ip_cores/wishbone/wbgen2/wbgen2_pkg.vhd
+++ b/ip_cores/wishbone/wbgen2/wbgen2_pkg.vhd
--- a/ip_cores/wishbone/wishbone_pkg.vhd
+++ b/ip_cores/wishbone/wishbone_pkg.vhd
--- a/ip_cores/wrabbit/modules/fabric/Manifest.py
+++ b/ip_cores/wrabbit/modules/fabric/Manifest.py
--- a/ip_cores/wrabbit/modules/fabric/wr_fabric_pkg.vhd
+++ b/ip_cores/wrabbit/modules/fabric/wr_fabric_pkg.vhd
--- a/ip_cores/wrabbit/modules/fabric/xwb_fabric_sink.vhd
+++ b/ip_cores/wrabbit/modules/fabric/xwb_fabric_sink.vhd
--- a/ip_cores/wrabbit/modules/fabric/xwb_fabric_source.vhd
+++ b/ip_cores/wrabbit/modules/fabric/xwb_fabric_source.vhd
--- a/ip_cores/wrabbit/modules/fabric/xwrf_mux.vhd
+++ b/ip_cores/wrabbit/modules/fabric/xwrf_mux.vhd
--- a/ip_cores/wrabbit/modules/timing/Manifest.py
+++ b/ip_cores/wrabbit/modules/timing/Manifest.py
--- a/ip_cores/wrabbit/modules/timing/dmtd_phase_meas.vhd
+++ b/ip_cores/wrabbit/modules/timing/dmtd_phase_meas.vhd
--- a/ip_cores/wrabbit/modules/timing/dmtd_with_deglitcher.vhd
+++ b/ip_cores/wrabbit/modules/timing/dmtd_with_deglitcher.vhd
--- a/ip_cores/wrabbit/modules/timing/hpll_period_detect.vhd
+++ b/ip_cores/wrabbit/modules/timing/hpll_period_detect.vhd
--- a/ip_cores/wrabbit/modules/timing/multi_dmtd_with_deglitcher.vhd
+++ b/ip_cores/wrabbit/modules/timing/multi_dmtd_with_deglitcher.vhd
--- a/ip_cores/wrabbit/modules/timing/pulse_gen.vhd
+++ b/ip_cores/wrabbit/modules/timing/pulse_gen.vhd
--- a/ip_cores/wrabbit/modules/timing/pulse_stamper.vhd
+++ b/ip_cores/wrabbit/modules/timing/pulse_stamper.vhd
--- a/ip_cores/wrabbit/modules/wr_dacs/Manifest.py
+++ b/ip_cores/wrabbit/modules/wr_dacs/Manifest.py
--- a/ip_cores/wrabbit/modules/wr_dacs/spec_serial_dac.vhd
+++ b/ip_cores/wrabbit/modules/wr_dacs/spec_serial_dac.vhd
--- a/ip_cores/wrabbit/modules/wr_dacs/spec_serial_dac_arb.vhd
+++ b/ip_cores/wrabbit/modules/wr_dacs/spec_serial_dac_arb.vhd
--- a/ip_cores/wrabbit/modules/wr_eca/.gitignore
+++ b/ip_cores/wrabbit/modules/wr_eca/.gitignore
--- a/ip_cores/wrabbit/modules/wr_eca/Makefile
+++ b/ip_cores/wrabbit/modules/wr_eca/Makefile
--- a/ip_cores/wrabbit/modules/wr_eca/Manifest.py
+++ b/ip_cores/wrabbit/modules/wr_eca/Manifest.py
--- a/ip_cores/wrabbit/modules/wr_eca/eca-ctl.cpp
+++ b/ip_cores/wrabbit/modules/wr_eca/eca-ctl.cpp
--- a/ip_cores/wrabbit/modules/wr_eca/eca-table.cpp
+++ b/ip_cores/wrabbit/modules/wr_eca/eca-table.cpp
--- a/ip_cores/wrabbit/modules/wr_eca/eca.h
+++ b/ip_cores/wrabbit/modules/wr_eca/eca.h
--- a/ip_cores/wrabbit/modules/wr_eca/eca.vhd
+++ b/ip_cores/wrabbit/modules/wr_eca/eca.vhd
--- a/ip_cores/wrabbit/modules/wr_eca/eca_adder.vhd
+++ b/ip_cores/wrabbit/modules/wr_eca/eca_adder.vhd
--- a/ip_cores/wrabbit/modules/wr_eca/eca_channel.vhd
+++ b/ip_cores/wrabbit/modules/wr_eca/eca_channel.vhd
--- a/ip_cores/wrabbit/modules/wr_eca/eca_flags.vhd
+++ b/ip_cores/wrabbit/modules/wr_eca/eca_flags.vhd
--- a/ip_cores/wrabbit/modules/wr_eca/eca_gpio_channel.vhd
+++ b/ip_cores/wrabbit/modules/wr_eca/eca_gpio_channel.vhd
--- a/ip_cores/wrabbit/modules/wr_eca/eca_offset.vhd
+++ b/ip_cores/wrabbit/modules/wr_eca/eca_offset.vhd
--- a/ip_cores/wrabbit/modules/wr_eca/eca_pkg.vhd
+++ b/ip_cores/wrabbit/modules/wr_eca/eca_pkg.vhd
--- a/ip_cores/wrabbit/modules/wr_eca/eca_queue_channel.vhd
+++ b/ip_cores/wrabbit/modules/wr_eca/eca_queue_channel.vhd
--- a/ip_cores/wrabbit/modules/wr_eca/eca_sdp.vhd
+++ b/ip_cores/wrabbit/modules/wr_eca/eca_sdp.vhd
--- a/ip_cores/wrabbit/modules/wr_eca/eca_search.vhd
+++ b/ip_cores/wrabbit/modules/wr_eca/eca_search.vhd
--- a/ip_cores/wrabbit/modules/wr_eca/eca_walker.vhd
+++ b/ip_cores/wrabbit/modules/wr_eca/eca_walker.vhd
--- a/ip_cores/wrabbit/modules/wr_eca/eca_wb_channel.vhd
+++ b/ip_cores/wrabbit/modules/wr_eca/eca_wb_channel.vhd
--- a/ip_cores/wrabbit/modules/wr_eca/eca_wb_event.vhd
+++ b/ip_cores/wrabbit/modules/wr_eca/eca_wb_event.vhd
--- a/ip_cores/wrabbit/modules/wr_eca/eca_wr_time.vhd
+++ b/ip_cores/wrabbit/modules/wr_eca/eca_wr_time.vhd
--- a/ip_cores/wrabbit/modules/wr_eca/lib/hw-channel.cpp
+++ b/ip_cores/wrabbit/modules/wr_eca/lib/hw-channel.cpp
--- a/ip_cores/wrabbit/modules/wr_eca/lib/hw-eca.cpp
+++ b/ip_cores/wrabbit/modules/wr_eca/lib/hw-eca.cpp
--- a/ip_cores/wrabbit/modules/wr_eca/lib/hw-eca.h
+++ b/ip_cores/wrabbit/modules/wr_eca/lib/hw-eca.h
--- a/ip_cores/wrabbit/modules/wr_eca/lib/hw-stream.cpp
+++ b/ip_cores/wrabbit/modules/wr_eca/lib/hw-stream.cpp
--- a/ip_cores/wrabbit/modules/wr_eca/lib/load-table.cpp
+++ b/ip_cores/wrabbit/modules/wr_eca/lib/load-table.cpp
--- a/ip_cores/wrabbit/modules/wr_eca/lib/probe-eca.cpp
+++ b/ip_cores/wrabbit/modules/wr_eca/lib/probe-eca.cpp
--- a/ip_cores/wrabbit/modules/wr_eca/lib/store-table.cpp
+++ b/ip_cores/wrabbit/modules/wr_eca/lib/store-table.cpp
--- a/ip_cores/wrabbit/modules/wr_eca/lib/table.cpp
+++ b/ip_cores/wrabbit/modules/wr_eca/lib/table.cpp
--- a/ip_cores/wrabbit/modules/wr_eca/lib/version.h.in
+++ b/ip_cores/wrabbit/modules/wr_eca/lib/version.h.in
--- a/ip_cores/wrabbit/modules/wr_eca/wr_eca.vhd
+++ b/ip_cores/wrabbit/modules/wr_eca/wr_eca.vhd
--- a/ip_cores/wrabbit/modules/wr_endpoint/Manifest.py
+++ b/ip_cores/wrabbit/modules/wr_endpoint/Manifest.py
--- a/ip_cores/wrabbit/modules/wr_endpoint/build_wb.sh
+++ b/ip_cores/wrabbit/modules/wr_endpoint/build_wb.sh
--- a/ip_cores/wrabbit/modules/wr_endpoint/endpoint_pkg.vhd
+++ b/ip_cores/wrabbit/modules/wr_endpoint/endpoint_pkg.vhd
--- a/ip_cores/wrabbit/modules/wr_endpoint/endpoint_private_pkg.vhd
+++ b/ip_cores/wrabbit/modules/wr_endpoint/endpoint_private_pkg.vhd
--- a/ip_cores/wrabbit/modules/wr_endpoint/ep_1000basex_pcs.vhd
+++ b/ip_cores/wrabbit/modules/wr_endpoint/ep_1000basex_pcs.vhd
--- a/ip_cores/wrabbit/modules/wr_endpoint/ep_autonegotiation.vhd
+++ b/ip_cores/wrabbit/modules/wr_endpoint/ep_autonegotiation.vhd
--- a/ip_cores/wrabbit/modules/wr_endpoint/ep_clock_alignment_fifo.vhd
+++ b/ip_cores/wrabbit/modules/wr_endpoint/ep_clock_alignment_fifo.vhd
--- a/ip_cores/wrabbit/modules/wr_endpoint/ep_crc32_pkg.vhd
+++ b/ip_cores/wrabbit/modules/wr_endpoint/ep_crc32_pkg.vhd
--- a/ip_cores/wrabbit/modules/wr_endpoint/ep_flow_control.vhd
+++ b/ip_cores/wrabbit/modules/wr_endpoint/ep_flow_control.vhd
--- a/ip_cores/wrabbit/modules/wr_endpoint/ep_leds_controller.vhd
+++ b/ip_cores/wrabbit/modules/wr_endpoint/ep_leds_controller.vhd
--- a/ip_cores/wrabbit/modules/wr_endpoint/ep_packet_filter.vhd
+++ b/ip_cores/wrabbit/modules/wr_endpoint/ep_packet_filter.vhd
--- a/ip_cores/wrabbit/modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd
+++ b/ip_cores/wrabbit/modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd
--- a/ip_cores/wrabbit/modules/wr_endpoint/ep_registers_pkg.vhd
+++ b/ip_cores/wrabbit/modules/wr_endpoint/ep_registers_pkg.vhd
--- a/ip_cores/wrabbit/modules/wr_endpoint/ep_rmon_counters.vhd
+++ b/ip_cores/wrabbit/modules/wr_endpoint/ep_rmon_counters.vhd
--- a/ip_cores/wrabbit/modules/wr_endpoint/ep_rtu_header_extract.vhd
+++ b/ip_cores/wrabbit/modules/wr_endpoint/ep_rtu_header_extract.vhd
--- a/ip_cores/wrabbit/modules/wr_endpoint/ep_rx_buffer.vhd
+++ b/ip_cores/wrabbit/modules/wr_endpoint/ep_rx_buffer.vhd
--- a/ip_cores/wrabbit/modules/wr_endpoint/ep_rx_bypass_queue.vhd
+++ b/ip_cores/wrabbit/modules/wr_endpoint/ep_rx_bypass_queue.vhd
--- a/ip_cores/wrabbit/modules/wr_endpoint/ep_rx_crc_size_check.vhd
+++ b/ip_cores/wrabbit/modules/wr_endpoint/ep_rx_crc_size_check.vhd
--- a/ip_cores/wrabbit/modules/wr_endpoint/ep_rx_early_address_match.vhd
+++ b/ip_cores/wrabbit/modules/wr_endpoint/ep_rx_early_address_match.vhd
--- a/ip_cores/wrabbit/modules/wr_endpoint/ep_rx_oob_insert.vhd
+++ b/ip_cores/wrabbit/modules/wr_endpoint/ep_rx_oob_insert.vhd
--- a/ip_cores/wrabbit/modules/wr_endpoint/ep_rx_path.vhd
+++ b/ip_cores/wrabbit/modules/wr_endpoint/ep_rx_path.vhd
--- a/ip_cores/wrabbit/modules/wr_endpoint/ep_rx_pcs_16bit.vhd
+++ b/ip_cores/wrabbit/modules/wr_endpoint/ep_rx_pcs_16bit.vhd
--- a/ip_cores/wrabbit/modules/wr_endpoint/ep_rx_pcs_8bit.vhd
+++ b/ip_cores/wrabbit/modules/wr_endpoint/ep_rx_pcs_8bit.vhd
--- a/ip_cores/wrabbit/modules/wr_endpoint/ep_rx_status_reg_insert.vhd
+++ b/ip_cores/wrabbit/modules/wr_endpoint/ep_rx_status_reg_insert.vhd
--- a/ip_cores/wrabbit/modules/wr_endpoint/ep_rx_vlan_unit.vhd
+++ b/ip_cores/wrabbit/modules/wr_endpoint/ep_rx_vlan_unit.vhd
--- a/ip_cores/wrabbit/modules/wr_endpoint/ep_rx_wb_master.vhd
+++ b/ip_cores/wrabbit/modules/wr_endpoint/ep_rx_wb_master.vhd
--- a/ip_cores/wrabbit/modules/wr_endpoint/ep_sync_detect.vhd
+++ b/ip_cores/wrabbit/modules/wr_endpoint/ep_sync_detect.vhd
--- a/ip_cores/wrabbit/modules/wr_endpoint/ep_sync_detect_16bit.vhd
+++ b/ip_cores/wrabbit/modules/wr_endpoint/ep_sync_detect_16bit.vhd
--- a/ip_cores/wrabbit/modules/wr_endpoint/ep_timestamping_unit.vhd
+++ b/ip_cores/wrabbit/modules/wr_endpoint/ep_timestamping_unit.vhd
--- a/ip_cores/wrabbit/modules/wr_endpoint/ep_ts_counter.vhd
+++ b/ip_cores/wrabbit/modules/wr_endpoint/ep_ts_counter.vhd
--- a/ip_cores/wrabbit/modules/wr_endpoint/ep_tx_framer.vhd
+++ b/ip_cores/wrabbit/modules/wr_endpoint/ep_tx_framer.vhd
--- a/ip_cores/wrabbit/modules/wr_endpoint/ep_tx_header_processor.vhd
+++ b/ip_cores/wrabbit/modules/wr_endpoint/ep_tx_header_processor.vhd
--- a/ip_cores/wrabbit/modules/wr_endpoint/ep_tx_pcs_16bit.vhd
+++ b/ip_cores/wrabbit/modules/wr_endpoint/ep_tx_pcs_16bit.vhd
--- a/ip_cores/wrabbit/modules/wr_endpoint/ep_tx_pcs_8bit.vhd
+++ b/ip_cores/wrabbit/modules/wr_endpoint/ep_tx_pcs_8bit.vhd
--- a/ip_cores/wrabbit/modules/wr_endpoint/ep_wishbone_controller.vhd
+++ b/ip_cores/wrabbit/modules/wr_endpoint/ep_wishbone_controller.vhd
--- a/ip_cores/wrabbit/modules/wr_endpoint/ep_wishbone_controller.wb
+++ b/ip_cores/wrabbit/modules/wr_endpoint/ep_wishbone_controller.wb
--- a/ip_cores/wrabbit/modules/wr_endpoint/pcs_regs.wb
+++ b/ip_cores/wrabbit/modules/wr_endpoint/pcs_regs.wb
--- a/ip_cores/wrabbit/modules/wr_endpoint/wr_endpoint.vhd
+++ b/ip_cores/wrabbit/modules/wr_endpoint/wr_endpoint.vhd
--- a/ip_cores/wrabbit/modules/wr_endpoint/xwr_endpoint.vhd
+++ b/ip_cores/wrabbit/modules/wr_endpoint/xwr_endpoint.vhd
--- a/ip_cores/wrabbit/modules/wr_mini_nic/Manifest.py
+++ b/ip_cores/wrabbit/modules/wr_mini_nic/Manifest.py
--- a/ip_cores/wrabbit/modules/wr_mini_nic/build_wb.sh
+++ b/ip_cores/wrabbit/modules/wr_mini_nic/build_wb.sh
--- a/ip_cores/wrabbit/modules/wr_mini_nic/mini_nic.wb
+++ b/ip_cores/wrabbit/modules/wr_mini_nic/mini_nic.wb
--- a/ip_cores/wrabbit/modules/wr_mini_nic/minic_packet_buffer.vhd
+++ b/ip_cores/wrabbit/modules/wr_mini_nic/minic_packet_buffer.vhd
--- a/ip_cores/wrabbit/modules/wr_mini_nic/minic_wb_slave.vhd
+++ b/ip_cores/wrabbit/modules/wr_mini_nic/minic_wb_slave.vhd
--- a/ip_cores/wrabbit/modules/wr_mini_nic/minic_wbgen2_pkg.vhd
+++ b/ip_cores/wrabbit/modules/wr_mini_nic/minic_wbgen2_pkg.vhd
--- a/ip_cores/wrabbit/modules/wr_mini_nic/wr_mini_nic.vhd
+++ b/ip_cores/wrabbit/modules/wr_mini_nic/wr_mini_nic.vhd
--- a/ip_cores/wrabbit/modules/wr_mini_nic/xwr_mini_nic.vhd
+++ b/ip_cores/wrabbit/modules/wr_mini_nic/xwr_mini_nic.vhd
--- a/ip_cores/wrabbit/modules/wr_pps_gen/Manifest.py
+++ b/ip_cores/wrabbit/modules/wr_pps_gen/Manifest.py
--- a/ip_cores/wrabbit/modules/wr_pps_gen/build_wb.sh
+++ b/ip_cores/wrabbit/modules/wr_pps_gen/build_wb.sh
--- a/ip_cores/wrabbit/modules/wr_pps_gen/pps_gen_regs.h
+++ b/ip_cores/wrabbit/modules/wr_pps_gen/pps_gen_regs.h
--- a/ip_cores/wrabbit/modules/wr_pps_gen/pps_gen_wb.vhd
+++ b/ip_cores/wrabbit/modules/wr_pps_gen/pps_gen_wb.vhd
--- a/ip_cores/wrabbit/modules/wr_pps_gen/pps_gen_wb.wb
+++ b/ip_cores/wrabbit/modules/wr_pps_gen/pps_gen_wb.wb
--- a/ip_cores/wrabbit/modules/wr_pps_gen/wr_pps_gen.vhd
+++ b/ip_cores/wrabbit/modules/wr_pps_gen/wr_pps_gen.vhd
--- a/ip_cores/wrabbit/modules/wr_pps_gen/xwr_pps_gen.vhd
+++ b/ip_cores/wrabbit/modules/wr_pps_gen/xwr_pps_gen.vhd
--- a/ip_cores/wrabbit/modules/wr_si57x_interface/Manifest.py
+++ b/ip_cores/wrabbit/modules/wr_si57x_interface/Manifest.py
--- a/ip_cores/wrabbit/modules/wr_si57x_interface/si570_if_wb.vhd
+++ b/ip_cores/wrabbit/modules/wr_si57x_interface/si570_if_wb.vhd
--- a/ip_cores/wrabbit/modules/wr_si57x_interface/si570_if_wb.wb
+++ b/ip_cores/wrabbit/modules/wr_si57x_interface/si570_if_wb.wb
--- a/ip_cores/wrabbit/modules/wr_si57x_interface/si570_if_wbgen2_pkg.vhd
+++ b/ip_cores/wrabbit/modules/wr_si57x_interface/si570_if_wbgen2_pkg.vhd
--- a/ip_cores/wrabbit/modules/wr_si57x_interface/wr_si57x_interface.vhd
+++ b/ip_cores/wrabbit/modules/wr_si57x_interface/wr_si57x_interface.vhd
--- a/ip_cores/wrabbit/modules/wr_si57x_interface/xwr_si57x_interface.vhd
+++ b/ip_cores/wrabbit/modules/wr_si57x_interface/xwr_si57x_interface.vhd
--- a/ip_cores/wrabbit/modules/wr_softpll_ng/Manifest.py
+++ b/ip_cores/wrabbit/modules/wr_softpll_ng/Manifest.py
--- a/ip_cores/wrabbit/modules/wr_softpll_ng/build_wb.sh
+++ b/ip_cores/wrabbit/modules/wr_softpll_ng/build_wb.sh
--- a/ip_cores/wrabbit/modules/wr_softpll_ng/softpll_pkg.vhd
+++ b/ip_cores/wrabbit/modules/wr_softpll_ng/softpll_pkg.vhd
--- a/ip_cores/wrabbit/modules/wr_softpll_ng/spll_bangbang_pd.vhd
+++ b/ip_cores/wrabbit/modules/wr_softpll_ng/spll_bangbang_pd.vhd
--- a/ip_cores/wrabbit/modules/wr_softpll_ng/spll_period_detect.vhd
+++ b/ip_cores/wrabbit/modules/wr_softpll_ng/spll_period_detect.vhd
--- a/ip_cores/wrabbit/modules/wr_softpll_ng/spll_wb_slave.vhd
+++ b/ip_cores/wrabbit/modules/wr_softpll_ng/spll_wb_slave.vhd
--- a/ip_cores/wrabbit/modules/wr_softpll_ng/spll_wb_slave.wb
+++ b/ip_cores/wrabbit/modules/wr_softpll_ng/spll_wb_slave.wb
--- a/ip_cores/wrabbit/modules/wr_softpll_ng/spll_wbgen2_pkg.vhd
+++ b/ip_cores/wrabbit/modules/wr_softpll_ng/spll_wbgen2_pkg.vhd
--- a/ip_cores/wrabbit/modules/wr_softpll_ng/wr_softpll_ng.vhd
+++ b/ip_cores/wrabbit/modules/wr_softpll_ng/wr_softpll_ng.vhd
--- a/ip_cores/wrabbit/modules/wr_softpll_ng/xwr_softpll_ng.vhd
+++ b/ip_cores/wrabbit/modules/wr_softpll_ng/xwr_softpll_ng.vhd
--- a/ip_cores/wrabbit/modules/wr_tbi_phy/Manifest.py
+++ b/ip_cores/wrabbit/modules/wr_tbi_phy/Manifest.py
--- a/ip_cores/wrabbit/modules/wr_tbi_phy/dec_8b10b.vhd
+++ b/ip_cores/wrabbit/modules/wr_tbi_phy/dec_8b10b.vhd
--- a/ip_cores/wrabbit/modules/wr_tbi_phy/disparity_gen_pkg.vhd
+++ b/ip_cores/wrabbit/modules/wr_tbi_phy/disparity_gen_pkg.vhd
--- a/ip_cores/wrabbit/modules/wr_tbi_phy/enc_8b10b.vhd
+++ b/ip_cores/wrabbit/modules/wr_tbi_phy/enc_8b10b.vhd
--- a/ip_cores/wrabbit/modules/wr_tbi_phy/wr_tbi_phy.vhd
+++ b/ip_cores/wrabbit/modules/wr_tbi_phy/wr_tbi_phy.vhd
--- a/ip_cores/wrabbit/modules/wr_tlu/Manifest.py
+++ b/ip_cores/wrabbit/modules/wr_tlu/Manifest.py
--- a/ip_cores/wrabbit/modules/wr_tlu/fake_timestamp.vhd
+++ b/ip_cores/wrabbit/modules/wr_tlu/fake_timestamp.vhd
--- a/ip_cores/wrabbit/modules/wr_tlu/wb_cores_pkg_gsi.vhd
+++ b/ip_cores/wrabbit/modules/wr_tlu/wb_cores_pkg_gsi.vhd
--- a/ip_cores/wrabbit/modules/wr_tlu/wb_timestamp_latch.vhd
+++ b/ip_cores/wrabbit/modules/wr_tlu/wb_timestamp_latch.vhd
--- a/ip_cores/wrabbit/modules/wrc_core/Manifest.py
+++ b/ip_cores/wrabbit/modules/wrc_core/Manifest.py
--- a/ip_cores/wrabbit/modules/wrc_core/build_wb.sh
+++ b/ip_cores/wrabbit/modules/wrc_core/build_wb.sh
--- a/ip_cores/wrabbit/modules/wrc_core/wb_reset.vhd
+++ b/ip_cores/wrabbit/modules/wrc_core/wb_reset.vhd
--- a/ip_cores/wrabbit/modules/wrc_core/wr_core.vhd
+++ b/ip_cores/wrabbit/modules/wrc_core/wr_core.vhd
--- a/ip_cores/wrabbit/modules/wrc_core/wrc_dpram.vhd
+++ b/ip_cores/wrabbit/modules/wrc_core/wrc_dpram.vhd
--- a/ip_cores/wrabbit/modules/wrc_core/wrc_periph.vhd
+++ b/ip_cores/wrabbit/modules/wrc_core/wrc_periph.vhd
--- a/ip_cores/wrabbit/modules/wrc_core/wrc_syscon_pkg.vhd
+++ b/ip_cores/wrabbit/modules/wrc_core/wrc_syscon_pkg.vhd
--- a/ip_cores/wrabbit/modules/wrc_core/wrc_syscon_regs.h
+++ b/ip_cores/wrabbit/modules/wrc_core/wrc_syscon_regs.h
--- a/ip_cores/wrabbit/modules/wrc_core/wrc_syscon_wb.vhd
+++ b/ip_cores/wrabbit/modules/wrc_core/wrc_syscon_wb.vhd
--- a/ip_cores/wrabbit/modules/wrc_core/wrc_syscon_wb.wb
+++ b/ip_cores/wrabbit/modules/wrc_core/wrc_syscon_wb.wb
--- a/ip_cores/wrabbit/modules/wrc_core/wrcore_pkg.vhd
+++ b/ip_cores/wrabbit/modules/wrc_core/wrcore_pkg.vhd
--- a/ip_cores/wrabbit/modules/wrc_core/xwr_core.vhd
+++ b/ip_cores/wrabbit/modules/wrc_core/xwr_core.vhd
--- a/ip_cores/wrabbit/modules/wrc_core/xwr_syscon_wb.vhd
+++ b/ip_cores/wrabbit/modules/wrc_core/xwr_syscon_wb.vhd
--- a/ip_cores/wrabbit/platform/Manifest.py
+++ b/ip_cores/wrabbit/platform/Manifest.py
--- a/ip_cores/wrabbit/platform/altera/Manifest.py
+++ b/ip_cores/wrabbit/platform/altera/Manifest.py
--- a/ip_cores/wrabbit/platform/altera/altera_butis.vhd
+++ b/ip_cores/wrabbit/platform/altera/altera_butis.vhd
--- a/ip_cores/wrabbit/platform/altera/altera_phase.vhd
+++ b/ip_cores/wrabbit/platform/altera/altera_phase.vhd
--- a/ip_cores/wrabbit/platform/altera/altera_pkg.vhd
+++ b/ip_cores/wrabbit/platform/altera/altera_pkg.vhd
--- a/ip_cores/wrabbit/platform/altera/altera_reset.vhd
+++ b/ip_cores/wrabbit/platform/altera/altera_reset.vhd
--- a/ip_cores/wrabbit/platform/altera/arria2_pll/.gitignore
+++ b/ip_cores/wrabbit/platform/altera/arria2_pll/.gitignore
--- a/ip_cores/wrabbit/platform/altera/arria2_pll/Manifest.py
+++ b/ip_cores/wrabbit/platform/altera/arria2_pll/Manifest.py
--- a/ip_cores/wrabbit/platform/altera/arria2_pll/arria2_pll.qip
+++ b/ip_cores/wrabbit/platform/altera/arria2_pll/arria2_pll.qip
--- a/ip_cores/wrabbit/platform/altera/arria2_pll/arria2_pll.tcl
+++ b/ip_cores/wrabbit/platform/altera/arria2_pll/arria2_pll.tcl
--- a/ip_cores/wrabbit/platform/altera/arria2_pll/dmtd_pll.txt
+++ b/ip_cores/wrabbit/platform/altera/arria2_pll/dmtd_pll.txt
--- a/ip_cores/wrabbit/platform/altera/arria2_pll/ref_pll.txt
+++ b/ip_cores/wrabbit/platform/altera/arria2_pll/ref_pll.txt
--- a/ip_cores/wrabbit/platform/altera/arria2_pll/sys_pll.txt
+++ b/ip_cores/wrabbit/platform/altera/arria2_pll/sys_pll.txt
--- a/ip_cores/wrabbit/platform/altera/arria5_pll/.gitignore
+++ b/ip_cores/wrabbit/platform/altera/arria5_pll/.gitignore
--- a/ip_cores/wrabbit/platform/altera/arria5_pll/Manifest.py
+++ b/ip_cores/wrabbit/platform/altera/arria5_pll/Manifest.py
--- a/ip_cores/wrabbit/platform/altera/arria5_pll/arria5_pll.qip
+++ b/ip_cores/wrabbit/platform/altera/arria5_pll/arria5_pll.qip
--- a/ip_cores/wrabbit/platform/altera/arria5_pll/arria5_pll.tcl
+++ b/ip_cores/wrabbit/platform/altera/arria5_pll/arria5_pll.tcl
--- a/ip_cores/wrabbit/platform/altera/arria5_pll/dmtd_pll5.txt
+++ b/ip_cores/wrabbit/platform/altera/arria5_pll/dmtd_pll5.txt
--- a/ip_cores/wrabbit/platform/altera/arria5_pll/ref_pll5.txt
+++ b/ip_cores/wrabbit/platform/altera/arria5_pll/ref_pll5.txt
--- a/ip_cores/wrabbit/platform/altera/arria5_pll/sys_pll5.txt
+++ b/ip_cores/wrabbit/platform/altera/arria5_pll/sys_pll5.txt
--- a/ip_cores/wrabbit/platform/altera/wr_arria2_phy/.gitignore
+++ b/ip_cores/wrabbit/platform/altera/wr_arria2_phy/.gitignore
--- a/ip_cores/wrabbit/platform/altera/wr_arria2_phy/Manifest.py
+++ b/ip_cores/wrabbit/platform/altera/wr_arria2_phy/Manifest.py
--- a/ip_cores/wrabbit/platform/altera/wr_arria2_phy/arria2_phy.txt
+++ b/ip_cores/wrabbit/platform/altera/wr_arria2_phy/arria2_phy.txt
--- a/ip_cores/wrabbit/platform/altera/wr_arria2_phy/arria2_phy_reconf.txt
+++ b/ip_cores/wrabbit/platform/altera/wr_arria2_phy/arria2_phy_reconf.txt
--- a/ip_cores/wrabbit/platform/altera/wr_arria2_phy/wr_arria2_phy.qip
+++ b/ip_cores/wrabbit/platform/altera/wr_arria2_phy/wr_arria2_phy.qip
--- a/ip_cores/wrabbit/platform/altera/wr_arria2_phy/wr_arria2_phy.tcl
+++ b/ip_cores/wrabbit/platform/altera/wr_arria2_phy/wr_arria2_phy.tcl
--- a/ip_cores/wrabbit/platform/altera/wr_arria2_phy/wr_arria2_phy.vhd
+++ b/ip_cores/wrabbit/platform/altera/wr_arria2_phy/wr_arria2_phy.vhd
--- a/ip_cores/wrabbit/platform/altera/wr_arria5_phy/.gitignore
+++ b/ip_cores/wrabbit/platform/altera/wr_arria5_phy/.gitignore
--- a/ip_cores/wrabbit/platform/altera/wr_arria5_phy/Manifest.py
+++ b/ip_cores/wrabbit/platform/altera/wr_arria5_phy/Manifest.py
--- a/ip_cores/wrabbit/platform/altera/wr_arria5_phy/arria5_phy.txt
+++ b/ip_cores/wrabbit/platform/altera/wr_arria5_phy/arria5_phy.txt
--- a/ip_cores/wrabbit/platform/altera/wr_arria5_phy/arria5_phy_reconf.txt
+++ b/ip_cores/wrabbit/platform/altera/wr_arria5_phy/arria5_phy_reconf.txt
--- a/ip_cores/wrabbit/platform/altera/wr_arria5_phy/wr_arria5_phy.qip
+++ b/ip_cores/wrabbit/platform/altera/wr_arria5_phy/wr_arria5_phy.qip
--- a/ip_cores/wrabbit/platform/altera/wr_arria5_phy/wr_arria5_phy.tcl
+++ b/ip_cores/wrabbit/platform/altera/wr_arria5_phy/wr_arria5_phy.tcl
--- a/ip_cores/wrabbit/platform/altera/wr_arria5_phy/wr_arria5_phy.vhd
+++ b/ip_cores/wrabbit/platform/altera/wr_arria5_phy/wr_arria5_phy.vhd
--- a/ip_cores/wrabbit/platform/xilinx/Manifest.py
+++ b/ip_cores/wrabbit/platform/xilinx/Manifest.py
--- a/ip_cores/wrabbit/platform/xilinx/chipscope/Manifest.py
+++ b/ip_cores/wrabbit/platform/xilinx/chipscope/Manifest.py
--- a/ip_cores/wrabbit/platform/xilinx/chipscope/chipscope_icon.ngc
+++ b/ip_cores/wrabbit/platform/xilinx/chipscope/chipscope_icon.ngc
--- a/ip_cores/wrabbit/platform/xilinx/chipscope/chipscope_ila.ngc
+++ b/ip_cores/wrabbit/platform/xilinx/chipscope/chipscope_ila.ngc
--- a/ip_cores/wrabbit/platform/xilinx/wr_gtp_phy/Manifest.py
+++ b/ip_cores/wrabbit/platform/xilinx/wr_gtp_phy/Manifest.py
--- a/ip_cores/wrabbit/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd
+++ b/ip_cores/wrabbit/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd
--- a/ip_cores/wrabbit/platform/xilinx/wr_gtp_phy/gtp_phase_align.vhd
+++ b/ip_cores/wrabbit/platform/xilinx/wr_gtp_phy/gtp_phase_align.vhd
--- a/ip_cores/wrabbit/platform/xilinx/wr_gtp_phy/gtp_phase_align_virtex6.vhd
+++ b/ip_cores/wrabbit/platform/xilinx/wr_gtp_phy/gtp_phase_align_virtex6.vhd
--- a/ip_cores/wrabbit/platform/xilinx/wr_gtp_phy/gtx_reset.vhd
+++ b/ip_cores/wrabbit/platform/xilinx/wr_gtp_phy/gtx_reset.vhd
--- a/ip_cores/wrabbit/platform/xilinx/wr_gtp_phy/whiterabbitgtp_wrapper.vhd
+++ b/ip_cores/wrabbit/platform/xilinx/wr_gtp_phy/whiterabbitgtp_wrapper.vhd
--- a/ip_cores/wrabbit/platform/xilinx/wr_gtp_phy/whiterabbitgtp_wrapper_tile.vhd
+++ b/ip_cores/wrabbit/platform/xilinx/wr_gtp_phy/whiterabbitgtp_wrapper_tile.vhd
--- a/ip_cores/wrabbit/platform/xilinx/wr_gtp_phy/whiterabbitgtp_wrapper_tile_spartan6.vhd
+++ b/ip_cores/wrabbit/platform/xilinx/wr_gtp_phy/whiterabbitgtp_wrapper_tile_spartan6.vhd
--- a/ip_cores/wrabbit/platform/xilinx/wr_gtp_phy/whiterabbitgtx_wrapper_gtx.vhd
+++ b/ip_cores/wrabbit/platform/xilinx/wr_gtp_phy/whiterabbitgtx_wrapper_gtx.vhd
--- a/ip_cores/wrabbit/platform/xilinx/wr_gtp_phy/wr_gtp_phy_spartan6.vhd
+++ b/ip_cores/wrabbit/platform/xilinx/wr_gtp_phy/wr_gtp_phy_spartan6.vhd
--- a/ip_cores/wrabbit/platform/xilinx/wr_gtp_phy/wr_gtp_phy_spec.vhd
+++ b/ip_cores/wrabbit/platform/xilinx/wr_gtp_phy/wr_gtp_phy_spec.vhd
--- a/ip_cores/wrabbit/platform/xilinx/wr_gtp_phy/wr_gtx_phy_virtex6.vhd
+++ b/ip_cores/wrabbit/platform/xilinx/wr_gtp_phy/wr_gtx_phy_virtex6.vhd
--- a/ip_cores/wrabbit/platform/xilinx/wr_xilinx_pkg.vhd
+++ b/ip_cores/wrabbit/platform/xilinx/wr_xilinx_pkg.vhd
--- a/rtl/carrier_info.vhd
+++ b/rtl/carrier_info.vhd
--- a/rtl/data_engine.vhd
+++ b/rtl/data_engine.vhd
--- a/rtl/decr_counter.vhd
+++ b/rtl/decr_counter.vhd
--- a/rtl/fmc_masterFIP_core.vhd
+++ b/rtl/fmc_masterFIP_core.vhd
--- a/rtl/fmc_masterFIP_mezzanine.vhd
+++ b/rtl/fmc_masterFIP_mezzanine.vhd
--- a/rtl/free_counter.vhd
+++ b/rtl/free_counter.vhd
--- a/rtl/incr_counter.vhd
+++ b/rtl/incr_counter.vhd
--- a/rtl/irq_generator.vhd
+++ b/rtl/irq_generator.vhd
--- a/rtl/leds_manager.vhd
+++ b/rtl/leds_manager.vhd
--- a/rtl/masterFIP_pkg.vhd
+++ b/rtl/masterFIP_pkg.vhd
--- a/rtl/reg_ctrl.vhd
+++ b/rtl/reg_ctrl.vhd
--- a/rtl/tdc_eic.vhd
+++ b/rtl/tdc_eic.vhd
--- a/rtl/wbgen/tdc_eic.wb
+++ b/rtl/wbgen/tdc_eic.wb
--- a/rtl/wf_cons_bytes_processor.vhd
+++ b/rtl/wf_cons_bytes_processor.vhd
--- a/rtl/wf_cons_outcome.vhd
+++ b/rtl/wf_cons_outcome.vhd
--- a/rtl/wf_crc.vhd
+++ b/rtl/wf_crc.vhd
--- a/rtl/wf_decr_counter.vhd
+++ b/rtl/wf_decr_counter.vhd
--- a/rtl/wf_fd_receiver.vhd
+++ b/rtl/wf_fd_receiver.vhd
--- a/rtl/wf_fd_transmitter.vhd
+++ b/rtl/wf_fd_transmitter.vhd
--- a/rtl/wf_incr_counter.vhd
+++ b/rtl/wf_incr_counter.vhd
--- a/rtl/wf_prod_bytes_retriever.vhd
+++ b/rtl/wf_prod_bytes_retriever.vhd
--- a/rtl/wf_prod_data_lgth_calc.vhd
+++ b/rtl/wf_prod_data_lgth_calc.vhd
--- a/rtl/wf_rx_deglitcher.vhd
+++ b/rtl/wf_rx_deglitcher.vhd
--- a/rtl/wf_rx_deserializer.vhd
+++ b/rtl/wf_rx_deserializer.vhd
--- a/rtl/wf_rx_osc.vhd
+++ b/rtl/wf_rx_osc.vhd
--- a/rtl/wf_tx_osc.vhd
+++ b/rtl/wf_tx_osc.vhd
--- a/rtl/wf_tx_serializer.vhd
+++ b/rtl/wf_tx_serializer.vhd
--- a/sim/spec/data_vectors/masterFIP_test.vec
+++ b/sim/spec/data_vectors/masterFIP_test.vec
--- a/sim/spec/testbench/acam_data_model.vhd
+++ b/sim/spec/testbench/acam_data_model.vhd
--- a/sim/spec/testbench/acam_fifo_model.vhd
+++ b/sim/spec/testbench/acam_fifo_model.vhd
--- a/sim/spec/testbench/acam_model.vhd
+++ b/sim/spec/testbench/acam_model.vhd
--- a/sim/spec/testbench/acam_timing_model.vhd
+++ b/sim/spec/testbench/acam_timing_model.vhd
--- a/sim/spec/testbench/gnum_model/cmd_router.vhd
+++ b/sim/spec/testbench/gnum_model/cmd_router.vhd
--- a/sim/spec/testbench/gnum_model/cmd_router1.vhd
+++ b/sim/spec/testbench/gnum_model/cmd_router1.vhd
--- a/sim/spec/testbench/gnum_model/gn412x_bfm.vhd
+++ b/sim/spec/testbench/gnum_model/gn412x_bfm.vhd
--- a/sim/spec/testbench/gnum_model/mem_model.vhd
+++ b/sim/spec/testbench/gnum_model/mem_model.vhd
--- a/sim/spec/testbench/gnum_model/textutil.vhd
+++ b/sim/spec/testbench/gnum_model/textutil.vhd
--- a/sim/spec/testbench/gnum_model/util.vhd
+++ b/sim/spec/testbench/gnum_model/util.vhd
--- a/sim/spec/testbench/nanoFIP/dualram_512x8.vhd
+++ b/sim/spec/testbench/nanoFIP/dualram_512x8.vhd
--- a/sim/spec/testbench/nanoFIP/nanoFIP_cons_bytes_processor.vhd
+++ b/sim/spec/testbench/nanoFIP/nanoFIP_cons_bytes_processor.vhd
--- a/sim/spec/testbench/nanoFIP/nanoFIP_cons_outcome.vhd
+++ b/sim/spec/testbench/nanoFIP/nanoFIP_cons_outcome.vhd
--- a/sim/spec/testbench/nanoFIP/nanoFIP_consumption.vhd
+++ b/sim/spec/testbench/nanoFIP/nanoFIP_consumption.vhd
--- a/sim/spec/testbench/nanoFIP/nanoFIP_crc.vhd
+++ b/sim/spec/testbench/nanoFIP/nanoFIP_crc.vhd
--- a/sim/spec/testbench/nanoFIP/nanoFIP_dualram_512x8_clka_rd_clkb_wr.vhd
+++ b/sim/spec/testbench/nanoFIP/nanoFIP_dualram_512x8_clka_rd_clkb_wr.vhd
--- a/sim/spec/testbench/nanoFIP/nanoFIP_engine_control.vhd
+++ b/sim/spec/testbench/nanoFIP/nanoFIP_engine_control.vhd
--- a/sim/spec/testbench/nanoFIP/nanoFIP_fd_receiver.vhd
+++ b/sim/spec/testbench/nanoFIP/nanoFIP_fd_receiver.vhd
--- a/sim/spec/testbench/nanoFIP/nanoFIP_fd_transmitter.vhd
+++ b/sim/spec/testbench/nanoFIP/nanoFIP_fd_transmitter.vhd
--- a/sim/spec/testbench/nanoFIP/nanoFIP_jtag_controller.vhd
+++ b/sim/spec/testbench/nanoFIP/nanoFIP_jtag_controller.vhd
--- a/sim/spec/testbench/nanoFIP/nanoFIP_model_constr_decoder.vhd
+++ b/sim/spec/testbench/nanoFIP/nanoFIP_model_constr_decoder.vhd
--- a/sim/spec/testbench/nanoFIP/nanoFIP_prod_bytes_retriever.vhd
+++ b/sim/spec/testbench/nanoFIP/nanoFIP_prod_bytes_retriever.vhd
--- a/sim/spec/testbench/nanoFIP/nanoFIP_prod_data_lgth_calc.vhd
+++ b/sim/spec/testbench/nanoFIP/nanoFIP_prod_data_lgth_calc.vhd
--- a/sim/spec/testbench/nanoFIP/nanoFIP_prod_permit.vhd
+++ b/sim/spec/testbench/nanoFIP/nanoFIP_prod_permit.vhd
--- a/sim/spec/testbench/nanoFIP/nanoFIP_production.vhd
+++ b/sim/spec/testbench/nanoFIP/nanoFIP_production.vhd
--- a/sim/spec/testbench/nanoFIP/nanoFIP_reset_unit.vhd
+++ b/sim/spec/testbench/nanoFIP/nanoFIP_reset_unit.vhd
--- a/sim/spec/testbench/nanoFIP/nanoFIP_rx_deglitcher.vhd
+++ b/sim/spec/testbench/nanoFIP/nanoFIP_rx_deglitcher.vhd
--- a/sim/spec/testbench/nanoFIP/nanoFIP_rx_deserializer.vhd
+++ b/sim/spec/testbench/nanoFIP/nanoFIP_rx_deserializer.vhd
--- a/sim/spec/testbench/nanoFIP/nanoFIP_rx_osc.vhd
+++ b/sim/spec/testbench/nanoFIP/nanoFIP_rx_osc.vhd
--- a/sim/spec/testbench/nanoFIP/nanoFIP_status_bytes_gen.vhd
+++ b/sim/spec/testbench/nanoFIP/nanoFIP_status_bytes_gen.vhd
--- a/sim/spec/testbench/nanoFIP/nanoFIP_tx_osc.vhd
+++ b/sim/spec/testbench/nanoFIP/nanoFIP_tx_osc.vhd
--- a/sim/spec/testbench/nanoFIP/nanoFIP_tx_serializer.vhd
+++ b/sim/spec/testbench/nanoFIP/nanoFIP_tx_serializer.vhd
--- a/sim/spec/testbench/nanoFIP/nanoFIP_wb_controller.vhd
+++ b/sim/spec/testbench/nanoFIP/nanoFIP_wb_controller.vhd
--- a/sim/spec/testbench/nanoFIP/nanofip.vhd
+++ b/sim/spec/testbench/nanoFIP/nanofip.vhd
--- a/sim/spec/testbench/nanoFIP/wf_decr_counter.vhd
+++ b/sim/spec/testbench/nanoFIP/wf_decr_counter.vhd
--- a/sim/spec/testbench/nanoFIP/wf_incr_counter.vhd
+++ b/sim/spec/testbench/nanoFIP/wf_incr_counter.vhd
--- a/sim/spec/testbench/nanoFIP/wf_package.vhd
+++ b/sim/spec/testbench/nanoFIP/wf_package.vhd
--- a/sim/spec/testbench/nanoFIP/wf_tx_serializer.vhd
+++ b/sim/spec/testbench/nanoFIP/wf_tx_serializer.vhd
--- a/sim/spec/testbench/nanoFIP/wf_wb_controller.vhd
+++ b/sim/spec/testbench/nanoFIP/wf_wb_controller.vhd
--- a/sim/spec/testbench/start_stop_gen.vhd
+++ b/sim/spec/testbench/start_stop_gen.vhd
--- a/sim/spec/testbench/tb_masterFIP.vhd
+++ b/sim/spec/testbench/tb_masterFIP.vhd
--- a/syn/spec/no_wrabbit/data_vectors/masterFIP_test.vec
+++ b/syn/spec/no_wrabbit/data_vectors/masterFIP_test.vec
--- a/syn/spec/no_wrabbit/spec_masterFIP.xise
+++ b/syn/spec/no_wrabbit/spec_masterFIP.xise
--- a/syn/spec/no_wrabbit/spec_masterfip.bin
+++ b/syn/spec/no_wrabbit/spec_masterfip.bin
--- a/top/spec/no_wrabbit/spec_masterFIP.ucf
+++ b/top/spec/no_wrabbit/spec_masterFIP.ucf
--- a/top/spec/no_wrabbit/spec_masterFIP.vhd
+++ b/top/spec/no_wrabbit/spec_masterFIP.vhd
--- a/top/spec/no_wrabbit/spec_reset_gen.vhd
+++ b/top/spec/no_wrabbit/spec_reset_gen.vhd
--- a/top/spec/no_wrabbit/synthesis_descriptor.vhd
+++ b/top/spec/no_wrabbit/synthesis_descriptor.vhd