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MasterFIP - Gateware
Commit 883581d1 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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spec_masterfip_mt: updated to newer version of WRNC

parent 5ee74546
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Showing with 25 additions and 20 deletions
wr-node-core @ 57feacea
Subproject commit a59986453556b83816a653f3bfeb3a05ffdb03bb Subproject commit 57feacea81ddf573180b6694e06c428838142d6e
syn/spec_mt/spec_masterfip_mt.xise
View file @ 883581d1
...@@ -49,7 +49,7 @@ ...@@ -49,7 +49,7 @@
<property xil_pn:name="Change Device Speed To" xil_pn:value="-3" xil_pn:valueState="default"/> <property xil_pn:name="Change Device Speed To" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-3" xil_pn:valueState="default"/> <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="false" xil_pn:valueState="non-default"/> <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
......
top/spec_mt/spec_masterfip_mt.vhd
View file @ 883581d1
...@@ -6,7 +6,7 @@ ...@@ -6,7 +6,7 @@
-- Author : Tomasz Włostowski -- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT -- Company : CERN BE-CO-HT
-- Created : 2014-04-01 -- Created : 2014-04-01
-- Last update: 2015-08-14 -- Last update: 2016-02-26
-- Platform : FPGA-generic -- Platform : FPGA-generic
-- Standard : VHDL'93 -- Standard : VHDL'93
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
...@@ -199,7 +199,7 @@ constant c_hmq_config : t_wrn_mqueue_config := ...@@ -199,7 +199,7 @@ constant c_hmq_config : t_wrn_mqueue_config :=
( (
app_id => x"0f1dc03e", app_id => x"0f1dc03e",
cpu_count => 2, cpu_count => 2,
cpu_memsizes => (65536, 65536, 0, 0, 0, 0, 0, 0), cpu_memsizes => (65536+32768, 8192, 0, 0, 0, 0, 0, 0),
hmq_config => c_hmq_config, hmq_config => c_hmq_config,
rmq_config => c_rmq_config, rmq_config => c_rmq_config,
shared_mem_size => 65536 shared_mem_size => 65536
...@@ -208,8 +208,8 @@ constant c_hmq_config : t_wrn_mqueue_config := ...@@ -208,8 +208,8 @@ constant c_hmq_config : t_wrn_mqueue_config :=
signal clk_sys : std_logic; signal clk_sys : std_logic;
signal rst_n_sys : std_logic; signal rst_n_sys : std_logic;
signal fmc_dp_wb_out : t_wishbone_master_out; signal fmc_dp_wb_out : t_wishbone_master_out_array(0 to 1);
signal fmc_dp_wb_in : t_wishbone_master_in; signal fmc_dp_wb_in : t_wishbone_master_in_array(0 to 1);
signal cpu0_gpio_oen : std_logic_vector(31 downto 0); signal cpu0_gpio_oen : std_logic_vector(31 downto 0);
signal cpu0_gpio_out : std_logic_vector(31 downto 0); signal cpu0_gpio_out : std_logic_vector(31 downto 0);
...@@ -279,8 +279,8 @@ begin ...@@ -279,8 +279,8 @@ begin
carrier_onewire_b => carrier_onewire_b, carrier_onewire_b => carrier_onewire_b,
fmc_prsnt_m2c_l_i => fmc_prsnt_m2c_l_i, fmc_prsnt_m2c_l_i => fmc_prsnt_m2c_l_i,
fmc0_dp_wb_o => fmc_dp_wb_out, dp_master_o => fmc_dp_wb_out,
fmc0_dp_wb_i => fmc_dp_wb_in, dp_master_i => fmc_dp_wb_in,
fmc0_clk_aux_i => '0', fmc0_clk_aux_i => '0',
fmc0_host_irq_i => '0' fmc0_host_irq_i => '0'
...@@ -316,22 +316,27 @@ begin ...@@ -316,22 +316,27 @@ begin
adc_prim_conn_n_o => adc_prim_conn_n_o, adc_prim_conn_n_o => adc_prim_conn_n_o,
adc_sec_conn_n_o => adc_sec_conn_n_o, adc_sec_conn_n_o => adc_sec_conn_n_o,
-- WISHBONE interface with -- WISHBONE interface with
wb_adr_i => fmc_dp_wb_out.adr, wb_adr_i => fmc_dp_wb_out(0).adr,
wb_dat_i => fmc_dp_wb_out.dat, wb_dat_i => fmc_dp_wb_out(0).dat,
wb_stb_i => fmc_dp_wb_out.stb, wb_stb_i => fmc_dp_wb_out(0).stb,
wb_we_i => fmc_dp_wb_out.we, wb_we_i => fmc_dp_wb_out(0).we,
wb_cyc_i => fmc_dp_wb_out.cyc, wb_cyc_i => fmc_dp_wb_out(0).cyc,
wb_sel_i => fmc_dp_wb_out.sel, wb_sel_i => fmc_dp_wb_out(0).sel,
wb_dat_o => fmc_dp_wb_in.dat, wb_dat_o => fmc_dp_wb_in(0).dat,
wb_ack_o => fmc_dp_wb_in.ack, wb_ack_o => fmc_dp_wb_in(0).ack,
wb_stall_o => fmc_dp_wb_in.stall, wb_stall_o => fmc_dp_wb_in(0).stall,
-- Aux -- Aux
aux_o => aux); aux_o => aux);
fmc_dp_wb_in.err <= '0'; fmc_dp_wb_in(0).err <= '0';
fmc_dp_wb_in.rty <= '0'; fmc_dp_wb_in(0).rty <= '0';
fmc_dp_wb_in.int <= '0'; fmc_dp_wb_in(0).int <= '0';
fmc_dp_wb_in(1).ack <= '1';
fmc_dp_wb_in(1).stall <= '0';
fmc_dp_wb_in(1).err <= '0';
fmc_dp_wb_in(1).rty <= '0';
fmc_dp_wb_in(1).int <= '0';
fd_txena_o <= fd_txena; fd_txena_o <= fd_txena;
......
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