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MasterFIP - Gateware
Commits
7c4850a4
Commit
7c4850a4
authored
Jul 20, 2015
by
Evangelia Gousiou
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Plain Diff
simulation folder cleanup
parent
a0eea9cb
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3 changed files
with
157 additions
and
113 deletions
+157
-113
masterFIP_test.vec
sim/spec/data_vectors/masterFIP_test.vec
+67
-19
cmd_router.vhd
sim/spec/testbench/gnum_model/cmd_router.vhd
+2
-2
spec_masterFIP.xise
syn/spec/spec_masterFIP.xise
+88
-92
No files found.
sim/spec/data_vectors/masterFIP_test.vec
View file @
7c4850a4
-------------------------------------------------------------------------------
--
masterFIP
_test
.
vec
--
acam
_test
.
vec
-------------------------------------------------------------------------------
--
Select
the
GN4124
Primary
BFM
model
0
...
...
@@ -20,44 +20,92 @@ bfm_bar 0 0000000040000000 20000000
bfm_bar
1
0000000020000000
20000000
--
Drive
reset
to
the
FPGA
reset
%
d32
reset
%
d32
0
--
Wait
until
the
FPGA
is
un
-
reset
and
ready
for
traffic
on
the
local
bus
wait
%
d
5
00
wait
%
d
9
00
-------------------------------------------------------------------------------
--
Access
the
tdc
core
register
space
-------------------------------------------------------------------------------
--
writing
stuff
config
wr
000000000005
100
A
F
00000201
--
reset
inactive
wr
000000000005
0000
F
CAFE0003
wait
%
d20
wr
000000000005100
A
F
00000200
--
reset
active
wr
0000000000050000
F
CAFE0000
wait
%
d20
wr
00000000000510
C0
F
00000003
--
reset
inactive
wr
0000000000050000
F
CAFE0003
wait
%
d20
wr
00000000000510
C4
F
00000014
---------------
ID_DAT
---------------
--
control
byte
of
id_dat
wr
00000000000500
C0
F
00000003
wait
%
d20
wr
00000000000510
C8
F
00000003
--
data
bytes
varid
=
0503
for
agent
to
consume
wr
00000000000500
C4
F
00000305
wait
%
d20
wr
000000000005100
A
F
00000202
--
rx_rst
wr
0000000000050038
F
00000001
wait
%
d20
--
tx_start
wr
000000000005002
C
F
00000202
wait
%
d20000
wr
0000000000051038
F
00000
AAA
--
deactivate
tx_start
and
reset
tx
wr
000000000005002
C
F
00000001
wait
%
d20
wr
000000000005103
C
F
00000
BBB
---------------
RP_DAT
---------------
--
control
byte
of
rp_dat
wr
00000000000500
c4
F
00000002
wait
%
d20
wr
0000000000051054
F
00000005
--
data
bytes
wr
00000000000500
c8
F
02010F40
wait
%
d20
wr
00000000000500
cc
F
06050403
wait
%
d20
wr
00000000000500
d0
F
0
A090807
wait
%
d20
wr
00000000000500
D4
F
0E0
D0C0B
wait
%
d20
wr
00000000000500
D8
F
06060605
wait
%
d20
--
activate
loop
wr
000000000005100F
C
F
00000001
--
tx_start
wr
000000000005002
C
F
00001102
wait
%
d40000
--
deactivate
tx_start
and
reset
tx
wr
000000000005002
C
F
00000001
wait
%
d20
---------------
ID_DAT
---------------
--
control
byte
of
id_dat
wr
00000000000500
c4
F
00000003
wait
%
d20
--
data
bytes
varid
=
1403
for
agent
to
send
identification
wr
00000000000500
c8
F
00000314
wait
%
d20
--
deactivate
acquisition
wr
00000000000510F
C
F
00000002
\ No newline at end of file
--
tx_start
wr
000000000005002
C
F
00000202
wait
%
d20
--
release
rx_rst
wr
0000000000050038
F
00000000
wait
%
d40000
--
read
received
data
rd
0000000000050040
F
00000002
wait
%
d20
rd
0000000000050044
F
00000050
sim/spec/testbench/gnum_model/cmd_router.vhd
View file @
7c4850a4
...
...
@@ -61,14 +61,14 @@ component cmd_router1
end
component
;
-- cmd_router1
type
FILE_ARRAY
is
array
(
natural
range
<>
)
of
string
(
1
to
31
);
type
FILE_ARRAY
is
array
(
natural
range
<>
)
of
string
(
1
to
47
);
type
CMD_ARRAY
is
array
(
natural
range
<>
)
of
string
(
CMD
'range
);
type
CMD_REQ_ARRAY
is
array
(
natural
range
<>
)
of
bit_vector
(
N_BFM
-1
downto
0
);
type
integer_vector
is
array
(
natural
range
<>
)
of
integer
;
type
boolean_vector
is
array
(
natural
range
<>
)
of
boolean
;
constant
MAX_FILES
:
integer
:
=
10
;
constant
FILENAMES
:
FILE_ARRAY
(
0
to
MAX_FILES
-1
)
:
=
(
others
=>
"data_vectors/masterFIP_test.vec"
);
constant
FILENAMES
:
FILE_ARRAY
(
0
to
MAX_FILES
-1
)
:
=
(
others
=>
"
../../sim/spec/
data_vectors/masterFIP_test.vec"
);
signal
CMDo
:
CMD_ARRAY
(
N_FILES
-1
downto
0
);
signal
REQ
:
bit_vector
(
CMD_REQ
'range
);
...
...
syn/spec/spec_masterFIP.xise
View file @
7c4850a4
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