Commit a0eea9cb authored by Evangelia Gousiou's avatar Evangelia Gousiou

further cleanup

parent e33baa6a
......@@ -148,14 +148,14 @@ architecture RAM4K9 of dualram_512x8 is
---------------------------------------------------------------------------------------------------
-- Instantiation of the component VCC
component VCC
component VCCtmp
port (Y : out std_logic);
end component;
---------------------------------------------------------------------------------------------------
-- Instantiation of the component GND
component GND
component GNDtmp
port (Y : out std_logic);
end component;
......@@ -169,18 +169,18 @@ architecture RAM4K9 of dualram_512x8 is
begin
power_supply_signal : VCC port map(Y => POWER);
ground_signal : GND port map(Y => GROUND);
power_supply_signal : VCCtmp port map(Y => POWER);
ground_signal : GNDtmp port map(Y => GROUND);
---------------------------------------------------------------------------------------------------
-- Instantiation of the component RAM4K9.
-- The following configuration has been applied:
-- o aspect ratio : 9 x 512 (WIDTHA0, WIDTHA1, WIDTHB0, WIDTHB1 : VCC)
-- o word width : 8 bits (DINA8, DINB8: GND; DOUTA8, DOUTB8 : open)
-- o memory depth : 512 bytes(ADDRA11, ADDRA10, ADDRA9, ADDRB11, ADDRB10, ADDRB9: GND)
-- o BLKA, BLKB : GND (ports enabled)
-- o PIPEA, PIPEB : GND (not pipelined read)
-- o WMODEA, WMODEB: GND (in write mode the output retains the data from the previous read)
-- o aspect ratio : 9 x 512 (WIDTHA0, WIDTHA1, WIDTHB0, WIDTHB1 : VCCtmp)
-- o word width : 8 bits (DINA8, DINB8: GNDtmp; DOUTA8, DOUTB8 : open)
-- o memory depth : 512 bytes(ADDRA11, ADDRA10, ADDRA9, ADDRB11, ADDRB10, ADDRB9: GNDtmp)
-- o BLKA, BLKB : GNDtmp (ports enabled)
-- o PIPEA, PIPEB : GNDtmp (not pipelined read)
-- o WMODEA, WMODEB: GNDtmp (in write mode the output retains the data from the previous read)
A9D8DualClkRAM_R0C0 : RAM4K9
port map(
......
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
......@@ -367,7 +367,7 @@ begin
-- wf_reset_unit --
---------------------------------------------------------------------------------------------------
reset_unit : nanoFIP_reset_unit
reset_unit : wf_reset_unit
port map(
uclk_i => uclk_i,
wb_clk_i => wclk_i,
......@@ -390,7 +390,7 @@ begin
-- wf_consumption --
---------------------------------------------------------------------------------------------------
Consumption: nanoFIP_consumption
Consumption: wf_consumption
port map(
uclk_i => uclk_i,
slone_i => slone_i,
......@@ -423,7 +423,7 @@ begin
-- wf_fd_receiver --
---------------------------------------------------------------------------------------------------
FIELDRIVE_Receiver: nanoFIP_fd_receiver
FIELDRIVE_Receiver: wf_fd_receiver
port map(
uclk_i => uclk_i,
rate_i => rate_i,
......@@ -444,7 +444,7 @@ begin
-- wf_production --
---------------------------------------------------------------------------------------------------
Production: nanoFIP_production
Production: wf_production
port map(
uclk_i => uclk_i,
slone_i => slone_i,
......@@ -486,7 +486,7 @@ begin
-- wf_fd_transmitter --
---------------------------------------------------------------------------------------------------
FIELDRIVE_Transmitter: nanoFIP_fd_transmitter
FIELDRIVE_Transmitter: wf_fd_transmitter
port map(
uclk_i => uclk_i,
rate_i => rate_i,
......@@ -509,7 +509,7 @@ begin
-- wf_jtag_controller --
---------------------------------------------------------------------------------------------------
JTAG_controller: nanoFIP_jtag_controller
JTAG_controller: wf_jtag_controller
port map(
uclk_i => uclk_i,
nfip_rst_i => s_nfip_intern_rst,
......@@ -530,7 +530,7 @@ begin
-- wf_engine_control --
---------------------------------------------------------------------------------------------------
engine_control : nanoFIP_engine_control
engine_control : wf_engine_control
port map(
uclk_i => uclk_i,
nfip_rst_i => s_nfip_intern_rst,
......@@ -568,7 +568,7 @@ begin
-- wf_model_constr_decoder --
---------------------------------------------------------------------------------------------------
model_constr_decoder : nanoFIP_model_constr_decoder
model_constr_decoder : wf_model_constr_decoder
port map(
uclk_i => uclk_i,
nfip_rst_i => s_nfip_intern_rst,
......@@ -586,7 +586,7 @@ begin
-- wf_wb_controller --
---------------------------------------------------------------------------------------------------
WISHBONE_controller: nanoFIP_wb_controller
WISHBONE_controller: wf_wb_controller
port map(
wb_clk_i => wclk_i,
wb_rst_i => s_wb_rst,
......
......@@ -7,10 +7,10 @@
---------------------------------------------------------------------------------------------------
-- |
-- nanoFIP_cons_bytes_processor |
-- wf_cons_bytes_processor |
-- |
---------------------------------------------------------------------------------------------------
-- File nanoFIP_cons_bytes_processor.vhd |
-- File wf_cons_bytes_processor.vhd |
-- |
-- Description The unit is consuming the RP_DAT data bytes that are arriving from the |
-- wf_fd_receiver, according to the following: |
......@@ -64,7 +64,7 @@
-- creation for simplification; Signals renamed; |
-- CTRL, PDU_TYPE, LGTH bytes registered; |
-- Code cleaned-up & commented. |
-- 15/12/2010 v0.03 EG Unit renamed from wf_cons_bytes_from_rx to nanoFIP_cons_bytes_processor |
-- 15/12/2010 v0.03 EG Unit renamed from wf_cons_bytes_from_rx to wf_cons_bytes_processor |
-- byte_ready_p comes from the rx_deserializer (no need to pass from |
-- the engine) Code cleaned-up & commented (more!) |
---------------------------------------------------------------------------------------------------
......@@ -98,9 +98,9 @@ use work.WF_PACKAGE.all; -- definitions of types, constants, entities
--=================================================================================================
-- Entity declaration for nanoFIP_cons_bytes_processor
-- Entity declaration for wf_cons_bytes_processor
--=================================================================================================
entity nanoFIP_cons_bytes_processor is port(
entity wf_cons_bytes_processor is port(
-- INPUTS
-- nanoFIP User Interface, General signals
uclk_i : in std_logic; -- 40 MHz clock
......@@ -143,13 +143,13 @@ entity nanoFIP_cons_bytes_processor is port(
cons_var_rst_byte_1_o : out std_logic_vector (7 downto 0); -- received var_rst RP_DAT, 1st data byte
cons_var_rst_byte_2_o : out std_logic_vector (7 downto 0)); -- received var_rst RP_DAT, 2nd data byte
end entity nanoFIP_cons_bytes_processor;
end entity wf_cons_bytes_processor;
--=================================================================================================
-- architecture declaration
--=================================================================================================
architecture rtl of nanoFIP_cons_bytes_processor is
architecture rtl of wf_cons_bytes_processor is
-- addressing the memory
signal s_base_adr : unsigned (8 downto 0);
......@@ -179,7 +179,7 @@ begin
-- Port A is connected to the WISHBONE interface for the readings from the user
-- Port B is used by the nanoFIP for the writings into the memory
Consumption_RAM : nanoFIP_dualram_512x8_clka_rd_clkb_wr
Consumption_RAM : wf_dualram_512x8_clka_rd_clkb_wr
port map(
clk_porta_i => wb_clk_i, -- WISHBONE clock
addr_porta_i => wb_adr_i, -- address of byte to be read
......@@ -202,7 +202,7 @@ begin
-- consumed data and the reading of them (by the wf_jtag_controller) take place internally.
-- Note: only 127 bytes are used.
Consumption_JTAG_RAM : nanoFIP_dualram_512x8_clka_rd_clkb_wr
Consumption_JTAG_RAM : wf_dualram_512x8_clka_rd_clkb_wr
port map(
clk_porta_i => uclk_i, -- user clock
addr_porta_i => jc_mem_adr_rd_i, -- address of byte to be read
......
......@@ -7,10 +7,10 @@
---------------------------------------------------------------------------------------------------
-- |
-- nanoFIP_cons_outcome |
-- wf_cons_outcome |
-- |
---------------------------------------------------------------------------------------------------
-- File nanoFIP_cons_outcome.vhd |
-- File wf_cons_outcome.vhd |
-- |
-- Description The unit starts by validating a consumed RP_DAT frame with respect to the |
-- correctness of: |
......@@ -56,7 +56,7 @@
-- 11/2010 v0.02 EG Treatment of reset vars added to the unit |
-- Correction on var1_rdy, var2_rdy for slone |
-- 12/2010 v0.03 EG Finally no broadcast in slone, cleanning-up+commenting |
-- 01/2011 v0.04 EG Unit wf_var_rdy_generator separated in nanoFIP_cons_outcome |
-- 01/2011 v0.04 EG Unit wf_var_rdy_generator separated in wf_cons_outcome |
-- (for var1_rdy,var2_rdy+var_rst outcome) & wf_prod_permit (for var3) |
-- 02/2011 v0.05 EG Added here functionality of wf_cons_frame_validator |
-- Bug on var1_rdy, var2_rdy generation corrected (the s_varX_received |
......@@ -95,10 +95,10 @@ use work.WF_PACKAGE.all; -- definitions of types, constants, entities
--=================================================================================================
-- Entity declaration for nanoFIP_cons_outcome
-- Entity declaration for wf_cons_outcome
--=================================================================================================
entity nanoFIP_cons_outcome is port(
entity wf_cons_outcome is port(
-- INPUTS
-- nanoFIP User Interface, General signals
uclk_i : in std_logic; -- 40 MHz clock
......@@ -150,13 +150,13 @@ entity nanoFIP_cons_outcome is port(
rst_nfip_and_fd_p_o : out std_logic);-- indicates that a var_rst with its 1st data-byte
-- containing the station's address has been
-- correctly received
end entity nanoFIP_cons_outcome;
end entity wf_cons_outcome;
--=================================================================================================
-- architecture declaration
--=================================================================================================
architecture rtl of nanoFIP_cons_outcome is
architecture rtl of wf_cons_outcome is
signal s_cons_frame_ok_p : std_logic;
signal s_rst_nfip_and_fd, s_assert_rston : std_logic;
......
......@@ -7,10 +7,10 @@
---------------------------------------------------------------------------------------------------
-- |
-- nanoFIP_consumption |
-- wf_consumption |
-- |
---------------------------------------------------------------------------------------------------
-- File nanoFIP_consumption.vhd |
-- File wf_consumption.vhd |
-- |
-- Description The unit groups the main actions that regard data consumption. |
-- It instantiates the units: |
......@@ -26,7 +26,7 @@
-- CRC bytes). |
-- |
-- ___________________________________________________________ |
-- | nanoFIP_consumption | |
-- | wf_consumption | |
-- | | |
-- | _____________________________________________ | |
-- | | | | |
......@@ -95,9 +95,9 @@ use work.WF_PACKAGE.all; -- definitions of types, constants, entities
--=================================================================================================
-- Entity declaration for nanoFIP_consumption
-- Entity declaration for wf_consumption
--=================================================================================================
entity nanoFIP_consumption is port(
entity wf_consumption is port(
-- INPUTS
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
......@@ -180,14 +180,14 @@ entity nanoFIP_consumption is port(
jc_start_p_o : out std_logic;
jc_mem_data_o : out std_logic_vector (7 downto 0));
end entity nanoFIP_consumption;
end entity wf_consumption;
--=================================================================================================
-- architecture declaration
--=================================================================================================
architecture struc of nanoFIP_consumption is
architecture struc of wf_consumption is
signal s_cons_ctrl_byte, s_cons_pdu_byte, s_cons_lgth_byte : std_logic_vector (7 downto 0);
signal s_cons_var_rst_byte_1, s_cons_var_rst_byte_2 : std_logic_vector (7 downto 0);
......@@ -203,7 +203,7 @@ begin
-- Consumed Bytes Processing --
---------------------------------------------------------------------------------------------------
Consumption_Bytes_Processor : nanoFIP_cons_bytes_processor
Consumption_Bytes_Processor : wf_cons_bytes_processor
port map(
uclk_i => uclk_i,
nfip_rst_i => nfip_rst_i,
......@@ -231,7 +231,7 @@ begin
-- Consumption Outcome --
---------------------------------------------------------------------------------------------------
Consumption_Outcome : nanoFIP_cons_outcome
Consumption_Outcome : wf_cons_outcome
port map(
uclk_i => uclk_i,
slone_i => slone_i,
......
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- |
-- wf_decr_counter |
-- |
---------------------------------------------------------------------------------------------------
-- File wf_decr_counter.vhd |
-- Description Decreasing counter with synchronous reset, load enable and decrease enable |
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 10/2010 |
-- Version v0.01 |
-- Depends on - |
---------------- |
-- Last changes |
-- 10/2010 EG v0.01 first version |
-- 10/2011 EG v0.01b nfip_rst_i renamed to counter_rst_i; counter_top renamed to |
-- counter_top_i; initial value after reset is all '1'; |
-- counter_decr_p_i renamed to counter_decr_i |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
--=================================================================================================
-- Libraries & Packages
--=================================================================================================
-- Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific library
library work;
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
--=================================================================================================
-- Entity declaration for wf_decr_counter
--=================================================================================================
entity wf_decr_counter is
generic(g_counter_lgth : natural := 4); -- default length
port(
-- INPUTS
-- nanoFIP User Interface general signal
uclk_i : in std_logic; -- 40 MHz clock
-- Signal from the wf_reset_unit
counter_rst_i : in std_logic; -- resets counter to all '1'
-- Signals from any unit
counter_decr_i : in std_logic; -- decrement enable
counter_load_i : in std_logic; -- load enable; loads counter to counter_top_i
counter_top_i : in unsigned (g_counter_lgth-1 downto 0); -- load value
-- OUTPUTS
-- Signal to any unit
counter_o : out unsigned (g_counter_lgth-1 downto 0); -- counter
counter_is_zero_o : out std_logic); -- empty counter indication
end entity wf_decr_counter;
--=================================================================================================
-- architecture declaration
--=================================================================================================
architecture rtl of wf_decr_counter is
signal s_counter : unsigned (g_counter_lgth-1 downto 0);
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
---------------------------------------------------------------------------------------------------
-- Synchronous process Decr_Counter
Decr_Counter: process (uclk_i)
begin
if rising_edge (uclk_i) then
if counter_rst_i = '1' then
s_counter <= (others => '1');
else
if counter_load_i = '1' then
s_counter <= counter_top_i;
elsif counter_decr_i = '1' then
s_counter <= s_counter - 1;
end if;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
counter_o <= s_counter;
counter_is_zero_o <= '1' when s_counter = to_unsigned(0, s_counter'length) else '0';
end architecture rtl;
--=================================================================================================
-- architecture end
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
---------------------------------------------------------------------------------------------------
\ No newline at end of file
......@@ -7,35 +7,35 @@
---------------------------------------------------------------------------------------------------
-- |
-- nanoFIP_fd_transmitter |
-- wf_fd_transmitter |
-- |
---------------------------------------------------------------------------------------------------
-- File nanoFIP_fd_transmitter.vhd |
-- File wf_fd_transmitter.vhd |
-- |
-- Description The unit groups the main actions that regard FIELDRIVE data transmission. |
-- It instantiates the units: |
-- |
-- o nanoFIP_tx_serializer: that receives bytes from the nanoFIP_production, encodes them |
-- o wf_tx_serializer: that receives bytes from the wf_production, encodes them |
-- (Manchester 2), adds the FSS, FCS & FES fields and puts one |
-- by one bits to the FIELDRIVE output FD_TXD, following the |
-- synchronization signals from the nanoFIP_tx_osc unit. |
-- synchronization signals from the wf_tx_osc unit. |
-- Also generates the nanoFIP output FD_TXENA. |
-- |
-- o nanoFIP_tx_osc : that generates the nanoFIP FIELDRIVE output FD_TXCK |
-- o wf_tx_osc : that generates the nanoFIP FIELDRIVE output FD_TXCK |
-- and the array of pulses tx_sched_p_buff, used for the |
-- synchronization of the nanoFIP_tx_serializer's actions. |
-- synchronization of the wf_tx_serializer's actions. |
-- |
-- _____________________________________ |
-- | | |
-- | nanoFIP_Production | |
-- | wf_Production | |
-- |_____________________________________| |
-- \/ |
-- ___________________________________________________________ |
-- | nanoFIP_fd_transmitter | |
-- | wf_fd_transmitter | |
-- | | |
-- | _____________ __________________________________ | |
-- | | | | | | |
-- | | nanoFIP_tx_osc | > | nanoFIP_tx_serializer | | |
-- | | wf_tx_osc | > | wf_tx_serializer | | |
-- | | | | | | |
-- | |_____________| |__________________________________| | |
-- |___________________________________________________________| |
......@@ -48,9 +48,9 @@
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 11/01/2011 |
-- Version v0.01 |
-- Depends on nanoFIP_reset_unit |
-- nanoFIP_production |
-- nanoFIP_engine_control |
-- Depends on wf_reset_unit |
-- wf_production |
-- wf_engine_control |
---------------- |
-- Last changes |
-- 01/2011 EG v0.01 first version |
......@@ -81,14 +81,14 @@ use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific library
library work;
use work.wf_PACKAGE.all; -- definitions of types, constants, entities
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
--=================================================================================================
-- Entity declaration for nanoFIP_fd_transmitter
-- Entity declaration for wf_fd_transmitter
--=================================================================================================
entity nanoFIP_fd_transmitter is port(
entity wf_fd_transmitter is port(
-- INPUTS
-- nanoFIP User Interface, General signal
uclk_i : in std_logic; -- 40 MHz clock
......@@ -96,13 +96,13 @@ entity nanoFIP_fd_transmitter is port(
-- nanoFIP WorldFIP Settings
rate_i : in std_logic_vector (1 downto 0); -- WorldFIP bit rate
-- Signal from the nanoFIP_reset_unit
-- Signal from the wf_reset_unit
nfip_rst_i : in std_logic; -- nanoFIP internal reset
-- Signals from the nanoFIP_production unit
-- Signals from the wf_production unit
tx_byte_i : in std_logic_vector (7 downto 0); -- byte to be delivered
-- Signals from the nanoFIP_engine_control
-- Signals from the wf_engine_control
tx_start_p_i : in std_logic; -- indication for the start of the production
tx_byte_request_accept_p_i : in std_logic; -- indication that a byte is ready to be delivered
tx_last_data_byte_p_i : in std_logic; -- indication of he last data byte
......@@ -110,7 +110,7 @@ entity nanoFIP_fd_transmitter is port(
-- OUTPUTS
-- Signal to the nanoFIP_engine_control
-- Signal to the wf_engine_control
tx_byte_request_p_o : out std_logic; -- request for a new byte to be transmitted; pulse
-- at the end of the transmission of a previous byte
tx_completed_p_o : out std_logic; -- pulse upon termination of a transmission
......@@ -121,13 +121,13 @@ entity nanoFIP_fd_transmitter is port(
tx_enable_o : out std_logic; -- transmitter enable
tx_clk_o : out std_logic);-- line driver half bit clock
end entity nanoFIP_fd_transmitter;
end entity wf_fd_transmitter;
--=================================================================================================
-- architecture declaration
--=================================================================================================
architecture struc of nanoFIP_fd_transmitter is
architecture struc of wf_fd_transmitter is
signal s_tx_clk_p_buff : std_logic_vector (c_TX_SCHED_BUFF_LGTH-1 downto 0);
signal s_tx_osc_rst_p : std_logic;
......@@ -143,7 +143,7 @@ begin
-- Oscillator --
---------------------------------------------------------------------------------------------------
tx_oscillator: nanoFIP_tx_osc
tx_oscillator: wf_tx_osc
port map(
uclk_i => uclk_i,
rate_i => rate_i,
......@@ -160,7 +160,7 @@ begin
-- Serializer --
---------------------------------------------------------------------------------------------------
tx_serializer: nanoFIP_tx_serializer
tx_serializer: wf_tx_serializer
port map(
uclk_i => uclk_i,
nfip_rst_i => nfip_rst_i,
......
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- |
-- wf_incr_counter |
-- |
---------------------------------------------------------------------------------------------------
-- File wf_incr_counter.vhd |
-- Description Increasing counter with synchronous reinitialise and increase enable |
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 01/2011 |
-- Version v0.011 |
-- Depends on - |
---------------- |
-- Last changes |
-- 10/2010 EG v0.01 first version |
-- 01/2011 EG v0.011 counter_full became a constant |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
--=================================================================================================
-- Libraries & Packages
--=================================================================================================
-- Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific library
library work;
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
--=================================================================================================
-- Entity declaration for wf_incr_counter
--=================================================================================================
entity wf_incr_counter is
generic(g_counter_lgth : natural := 4); -- default length
port(
-- INPUTS
-- nanoFIP User Interface general signal
uclk_i : in std_logic; -- 40 MHz clock
-- Signals from any unit
counter_incr_i : in std_logic; -- increment enable
counter_reinit_i : in std_logic; -- reinitializes counter to 0
-- OUTPUT
-- Signal to any unit
counter_o : out unsigned (g_counter_lgth-1 downto 0); -- counter
counter_is_full_o : out std_logic); -- counter full indication
-- (all bits to '1')
end entity wf_incr_counter;
--=================================================================================================
-- architecture declaration
--=================================================================================================
architecture rtl of wf_incr_counter is
constant c_COUNTER_FULL : unsigned (g_counter_lgth-1 downto 0) := (others => '1');
signal s_counter : unsigned (g_counter_lgth-1 downto 0);
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
---------------------------------------------------------------------------------------------------
-- Synchronous process Incr_Counter
Incr_Counter: process (uclk_i)
begin
if rising_edge (uclk_i) then
if counter_reinit_i = '1' then
s_counter <= (others => '0');
elsif counter_incr_i = '1' then
s_counter <= s_counter + 1;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
counter_o <= s_counter;
counter_is_full_o <= '1' when s_counter = c_COUNTER_FULL else '0';
end architecture rtl;
--=================================================================================================
-- architecture end
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
---------------------------------------------------------------------------------------------------
\ No newline at end of file
......@@ -7,10 +7,10 @@
---------------------------------------------------------------------------------------------------
-- |
-- nanoFIP_model_constr_decoder |
-- wf_model_constr_decoder |
-- |
---------------------------------------------------------------------------------------------------
-- File nanoFIP_model_constr_decoder.vhd |
-- File wf_model_constr_decoder.vhd |
-- |
-- Description Generation of the nanoFIP output S_ID and decoding of the inputs C_ID and M_ID. |
-- The output S_ID0 is a clock with period the double of uclk's period and the S_ID1 |
......@@ -26,7 +26,7 @@
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 21/01/2011 |
-- Version v0.03 |
-- Depends on nanoFIP_reset_unit |
-- Depends on wf_reset_unit |
---------------- |
-- Last changes |
-- 11/09/2009 v0.01 PAS First version |
......@@ -63,18 +63,18 @@ use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific library
library work;
use work.wf_PACKAGE.all; -- definitions of types, constants, entities
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
--=================================================================================================
-- Entity declaration for nanoFIP_model_constr_decoder
-- Entity declaration for wf_model_constr_decoder
--=================================================================================================
entity nanoFIP_model_constr_decoder is port(
entity wf_model_constr_decoder is port(
-- INPUTS
-- nanoFIP User Interface general signal
uclk_i : in std_logic; -- 40 Mhz clock
-- Signal from the nanoFIP_reset_unit
-- Signal from the wf_reset_unit
nfip_rst_i : in std_logic; -- nanoFIP internal reset
-- nanoFIP WorldFIP Settings (synchronised with uclk_i)
......@@ -86,17 +86,17 @@ entity nanoFIP_model_constr_decoder is port(
-- nanoFIP WorldFIP Settings output
s_id_o : out std_logic_vector (1 downto 0); -- Identification selection
-- Signal to the nanoFIP_prod_bytes_retriever unit
-- Signal to the wf_prod_bytes_retriever unit
constr_id_dec_o : out std_logic_vector (7 downto 0); -- Constructor identification decoded
model_id_dec_o : out std_logic_vector (7 downto 0));-- Model identification decoded
end entity nanoFIP_model_constr_decoder;
end entity wf_model_constr_decoder;
--=================================================================================================
-- architecture declaration
--=================================================================================================
architecture rtl of nanoFIP_model_constr_decoder is
architecture rtl of wf_model_constr_decoder is
signal s_counter : unsigned (1 downto 0);
signal s_model_stage2, s_model_stage1 : std_logic_vector (3 downto 0);
......@@ -157,7 +157,7 @@ begin
---------------------------------------------------------------------------------------------------
-- Instantiation of a counter nanoFIP_incr_counter
-- Instantiation of a counter wf_incr_counter
Free_Counter: wf_incr_counter
generic map(g_counter_lgth => 2)
......
......@@ -7,10 +7,10 @@
---------------------------------------------------------------------------------------------------
-- |
-- nanoFIP_prod_data_lgth_calc |
-- wf_prod_data_lgth_calc |
-- |
---------------------------------------------------------------------------------------------------
-- File nanoFIP_prod_data_lgth_calc.vhd |
-- File wf_prod_data_lgth_calc.vhd |
-- |
-- Description Calculation of the number of bytes, after the FSS and before the FCS, that have to|
-- be transferred when a variable is produced (var_pres, var_identif, var_3, var_5) |
......@@ -44,7 +44,7 @@
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 09/12/2010 |
-- Version v0.02 |
-- Depends on nanoFIP_engine_control |
-- Depends on wf_engine_control |
---------------- |
-- Last changes |
-- 12/2010 v0.02 EG code cleaned-up+commented |
......@@ -75,19 +75,19 @@ use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific library
library work;
use work.wf_PACKAGE.all; -- definitions of types, constants, entities
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
--=================================================================================================
-- Entity declaration for nanoFIP_prod_data_lgth_calc
-- Entity declaration for wf_prod_data_lgth_calc
--=================================================================================================
entity nanoFIP_prod_data_lgth_calc is port(
entity wf_prod_data_lgth_calc is port(
-- INPUTS
-- nanoFIP User Interface, General signals
uclk_i : in std_logic; -- 40 MHz clock
-- Signal from the nanoFIP_reset_unit
-- Signal from the wf_reset_unit
nfip_rst_i : in std_logic; -- nanoFIP internal reset
-- nanoFIP WorldFIP Settings
......@@ -97,21 +97,21 @@ entity nanoFIP_prod_data_lgth_calc is port(
nostat_i : in std_logic; -- if negated, nFIP status is sent
slone_i : in std_logic; -- stand-alone mode
-- Signal from the nanoFIP_engine_control unit
-- Signal from the wf_engine_control unit
var_i : in t_var; -- variable type that is being treated
-- OUTPUT
-- Signal to the nanoFIP_engine_control and nanoFIP_production units
-- Signal to the wf_engine_control and wf_production units
prod_data_lgth_o : out std_logic_vector (7 downto 0));
end entity nanoFIP_prod_data_lgth_calc;
end entity wf_prod_data_lgth_calc;
--=================================================================================================
-- architecture declaration
--=================================================================================================
architecture behavior of nanoFIP_prod_data_lgth_calc is
architecture behavior of wf_prod_data_lgth_calc is
signal s_prod_data_lgth, s_p3_lgth_decoded : unsigned (7 downto 0);
......@@ -125,7 +125,7 @@ begin
-- Combinatorial process data_length_calcul: calculation of the amount of bytes, after the
-- FSS and before the FCS, that have to be transferred when a variable is produced. In the case
-- of the presence, the identification and the var5 variables, the data length is predefined in the
-- nanoFIP_PACKAGE. In the case of a var3 the inputs SLONE, NOSTAT and P3_LGTH[] are accounted for the
-- WF_PACKAGE. In the case of a var3 the inputs SLONE, NOSTAT and P3_LGTH[] are accounted for the
-- calculation.
data_length_calcul: process (var_i, s_p3_lgth_decoded, slone_i, nostat_i, p3_lgth_i)
......@@ -138,13 +138,13 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
when var_presence =>
-- data length information retrieval from the c_VARS_ARRAY matrix (nanoFIP_PACKAGE)
-- data length information retrieval from the c_VARS_ARRAY matrix (WF_PACKAGE)
s_prod_data_lgth <= c_VARS_ARRAY(c_VAR_PRESENCE_INDEX).array_lgth;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
when var_identif =>
-- data length information retrieval from the c_VARS_ARRAY matrix (nanoFIP_PACKAGE)
-- data length information retrieval from the c_VARS_ARRAY matrix (WF_PACKAGE)
s_prod_data_lgth <= c_VARS_ARRAY(c_VAR_IDENTIF_INDEX).array_lgth;
......@@ -188,7 +188,7 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
when var_5 =>
-- data length information retrieval from the c_VARS_ARRAY matrix (nanoFIP_PACKAGE)
-- data length information retrieval from the c_VARS_ARRAY matrix (WF_PACKAGE)
s_prod_data_lgth <= c_VARS_ARRAY(c_VAR_5_INDEX).array_lgth;
......
......@@ -7,10 +7,10 @@
---------------------------------------------------------------------------------------------------
-- |
-- nanoFIP_prod_permit |
-- wf_prod_permit |
-- |
---------------------------------------------------------------------------------------------------
-- File nanoFIP_prod_permit.vhd |
-- File wf_prod_permit.vhd |
-- |
-- Description Generation of the "nanoFIP User Interface, NON_WISHBONE" output signal VAR3_RDY, |
-- according to the variable (var_i) that is being treated. |
......@@ -19,8 +19,8 @@
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 14/1/2011 |
-- Version v0.01 |
-- Depends on nanoFIP_engine_control |
-- nanoFIP_reset_unit |
-- Depends on wf_engine_control |
-- wf_reset_unit |
---------------- |
-- Last changes |
-- 1/2011 v0.01 EG First version |
......@@ -51,22 +51,22 @@ use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific library
library work;
use work.wf_PACKAGE.all; -- definitions of types, constants, entities
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
--=================================================================================================
-- Entity declaration for nanoFIP_prod_permit
-- Entity declaration for wf_prod_permit
--=================================================================================================
entity nanoFIP_prod_permit is port(
entity wf_prod_permit is port(
-- INPUTS
-- nanoFIP User Interface, General signals
uclk_i : in std_logic; -- 40 MHz clock
-- Signal from the nanoFIP_reset_unit
-- Signal from the wf_reset_unit
nfip_rst_i : in std_logic; -- nanoFIP internal reset
-- Signals from the nanoFIP_engine_control
-- Signals from the wf_engine_control
var_i : in t_var; -- variable type that is being treated
......@@ -74,13 +74,13 @@ entity nanoFIP_prod_permit is port(
-- nanoFIP User Interface, NON-WISHBONE outputs
var3_rdy_o : out std_logic); -- signals the user that data can safely be written
end entity nanoFIP_prod_permit;
end entity wf_prod_permit;
--=================================================================================================
-- architecture declaration
--=================================================================================================
architecture rtl of nanoFIP_prod_permit is
architecture rtl of wf_prod_permit is
--=================================================================================================
-- architecture begin
......
......@@ -7,10 +7,10 @@
---------------------------------------------------------------------------------------------------
-- |
-- nanoFIP_reset_unit |
-- wf_reset_unit |
-- |
---------------------------------------------------------------------------------------------------
-- File nanoFIP_reset_unit.vhd |
-- File wf_reset_unit.vhd |
-- |
-- Description The unit is responsible for the generation of the: |
-- |
......@@ -86,7 +86,7 @@
-- Notes: |
-- - The input signal RSTIN is considered only if it has been active for at least |
-- 4 uclk cycles; the functional specs define 8 uclks, but in reality we check for 4.|
-- - The pulses rst_nFIP_and_FD_p and assert_RSTON_p come from the nanoFIP_cons_outcome |
-- - The pulses rst_nFIP_and_FD_p and assert_RSTON_p come from the wf_cons_outcome |
-- unit only after the sucessful validation of the frame structure and of the |
-- application-data bytes of the var_rst. |
-- - The RSTPON (Power On Reset generated with an RC circuit) removal is synchronized |
......@@ -101,14 +101,14 @@
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 11/2011 |
-- Version v0.03 |
-- Depends on nanoFIP_consumption |
-- Depends on wf_consumption |
---------------- |
-- Last changes |
-- 07/2009 v0.01 EB First version |
-- 08/2010 v0.02 EG checking of bytes1 and 2 of reset var added |
-- fd_rstn_o, nfip_rst_o enabled only if rstin has been active for>4 uclk |
-- 01/2011 v0.03 EG PoR added; signals assert_rston_p_i & rst_nfip_and_fd_p_i are inputs |
-- treated in the nanoFIP_cons_outcome; 2 state machines created; clean-up |
-- treated in the wf_cons_outcome; 2 state machines created; clean-up |
-- PoR also for internal WISHBONE resets |
-- 02/2011 v0.031 EG state nFIP_OFF_FD_OFF added |
-- 11/2011 v0.032 EG added s_rstin_c_is_full, s_var_rst_c_is_full signals that reset FSMs |
......@@ -140,13 +140,13 @@ use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific library
library work;
use work.wf_PACKAGE.all; -- definitions of types, constants, entities
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
--=================================================================================================
-- Entity declaration for nanoFIP_reset_unit
-- Entity declaration for wf_reset_unit
--=================================================================================================
entity nanoFIP_reset_unit is port(
entity wf_reset_unit is port(
-- INPUTS
-- nanoFIP User Interface General signals
uclk_i : in std_logic; -- 40 MHz clock
......@@ -158,7 +158,7 @@ entity nanoFIP_reset_unit is port(
rst_i : in std_logic; -- WISHBONE reset
wb_clk_i : in std_logic; -- WISHBONE clock
-- Signal from the nanoFIP_consumption unit
-- Signal from the wf_consumption unit
rst_nfip_and_fd_p_i : in std_logic; -- indicates that a var_rst with its 1st byte
-- containing the station's address has been
-- correctly received
......@@ -173,7 +173,7 @@ entity nanoFIP_reset_unit is port(
nfip_rst_o : out std_logic; -- nanoFIP internal reset, active high
-- resets all nanoFIP logic, apart from the WISHBONE
-- Signal to the nanoFIP_wb_controller
-- Signal to the wf_wb_controller
wb_rst_o : out std_logic; -- reset of the WISHBONE logic
-- nanoFIP User Interface General signal output
......@@ -182,13 +182,13 @@ entity nanoFIP_reset_unit is port(
-- nanoFIP FIELDRIVE output
fd_rstn_o : out std_logic); -- FIELDRIVE reset, active low
end entity nanoFIP_reset_unit;
end entity wf_reset_unit;
--=================================================================================================
-- architecture declaration
--=================================================================================================
architecture rtl of nanoFIP_reset_unit is
architecture rtl of wf_reset_unit is
-- RSTIN and RSTPON synchronizers
signal s_rsti_synch : std_logic_vector (2 downto 0);
......@@ -441,7 +441,7 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Instantiation of a nanoFIP_incr_counter: the counter counts from 0 to 4 FD_TXCK.
-- Instantiation of a wf_incr_counter: the counter counts from 0 to 4 FD_TXCK.
-- In case something goes wrong and the counter continues conting after the 4 FD_TXCK, the
-- s_rstin_c_is_full will be activated and the FSM will be reset.
......@@ -662,7 +662,7 @@ RSTIN_free_counter: wf_incr_counter
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Instantiation of a nanoFIP_incr_counter:
-- Instantiation of a wf_incr_counter:
-- the counter counts from 0 to 8, if only assert_RSTON_p has been activated, or
-- from 0 to 4 * FD_TXCK, if rst_nfip_and_fd_p_i has been activated.
-- In case something goes wrong and the counter continues conting after the 4 FD_TXCK, the
......
......@@ -7,10 +7,10 @@
---------------------------------------------------------------------------------------------------
-- |
-- nanoFIP_status_bytes_gen |
-- wf_status_bytes_gen |
-- |
---------------------------------------------------------------------------------------------------
-- File nanoFIP_status_bytes_gen.vhd |
-- File wf_status_bytes_gen.vhd |
-- |
-- Description Generation of the nanoFIP status and MPS status bytes. |
-- The unit is also responsible for outputting the "nanoFIP User Interface, |
......@@ -18,7 +18,7 @@
-- nanoFIP status bits 2 to 5. |
-- |
-- The information contained in the nanoFIP status byte is coming from : |
-- o the nanoFIP_consumption unit, for the bits 4 and 5 |
-- o the wf_consumption unit, for the bits 4 and 5 |
-- o the "nanoFIP FIELDRIVE" inputs FD_WDGN and FD_TXER, for the bits 6 and 7 |
-- o the "nanoFIP User Interface, NON_WISHBONE" inputs (VAR_ACC) and outputs |
-- (VAR_RDY), for the bits 2 and 3. |
......@@ -74,10 +74,10 @@
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 06/2011 |
-- Version v0.04 |
-- Depends on nanoFIP_reset_unit |
-- nanoFIP_consumption |
-- nanoFIP_prod_bytes_retriever |
-- nanoFIP_prod_permit |
-- Depends on wf_reset_unit |
-- wf_consumption |
-- wf_prod_bytes_retriever |
-- wf_prod_permit |
---------------- |
-- Last changes |
-- 07/07/2009 v0.01 PA First version |
......@@ -119,19 +119,19 @@ use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific library
library work;
use work.wf_PACKAGE.all; -- definitions of types, constants, entities
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
--=================================================================================================
-- Entity declaration for nanoFIP_status_bytes_gen
-- Entity declaration for wf_status_bytes_gen
--=================================================================================================
entity nanoFIP_status_bytes_gen is port(
entity wf_status_bytes_gen is port(
-- INPUTS
-- nanoFIP User Interface, General signals
uclk_i : in std_logic; -- 40 MHz Clock
slone_i : in std_logic; -- stand-alone mode
-- Signal from the nanoFIP_reset_unit
-- Signal from the wf_reset_unit
nfip_rst_i : in std_logic; -- nanaoFIP internal reset
-- nanoFIP FIELDRIVE
......@@ -143,20 +143,20 @@ entity nanoFIP_status_bytes_gen is port(
var2_acc_a_i : in std_logic; -- variable 2 access
var3_acc_a_i : in std_logic; -- variable 3 access
-- Signals from the nanoFIP_consumption unit
-- Signals from the wf_consumption unit
nfip_status_r_fcser_p_i : in std_logic; -- wrong CRC bytes received
nfip_status_r_tler_p_i : in std_logic; -- wrong PDU_TYPE, CTRL or LGTH bytes received
var1_rdy_i : in std_logic; -- variable 1 ready
var2_rdy_i : in std_logic; -- variable 2 ready
-- Signals from the nanoFIP_prod_bytes_retriever unit
-- Signals from the wf_prod_bytes_retriever unit
rst_status_bytes_p_i : in std_logic; -- reset for both status bytes;
-- they are reset right after having been delivered
-- Signals from the nanoFIP_prod_permit unit
-- Signals from the wf_prod_permit unit
var3_rdy_i : in std_logic; -- variable 3 ready
-- Signal from the nanoFIP_engine_control unit
-- Signal from the wf_engine_control unit
var_i : in t_var; -- variable type that is being treated
-- OUTPUTS
......@@ -166,16 +166,16 @@ entity nanoFIP_status_bytes_gen is port(
u_cacer_o : out std_logic; -- nanoFIP status byte, bit 2
u_pacer_o : out std_logic; -- nanoFIP status byte, bit 3
-- Signal to the nanoFIP_prod_bytes_retriever
-- Signal to the wf_prod_bytes_retriever
mps_status_byte_o : out std_logic_vector (7 downto 0); -- MPS status byte
nFIP_status_byte_o : out std_logic_vector (7 downto 0));-- nanoFIP status byte
end entity nanoFIP_status_bytes_gen;
end entity wf_status_bytes_gen;
--=================================================================================================
-- architecture declaration
--=================================================================================================
architecture rtl of nanoFIP_status_bytes_gen is
architecture rtl of wf_status_bytes_gen is
-- synchronizers
signal s_fd_txer_synch, s_fd_wdg_synch, s_var1_acc_synch : std_logic_vector (2 downto 0);
......@@ -365,7 +365,7 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Instantiation of 3 nanoFIP_incr_counters used for the internal extension of each one of the
-- Instantiation of 3 wf_incr_counters used for the internal extension of each one of the
-- signals VAR1_RDY, VAR2_RDY, VAR3_RDY for 15 uclk cycles.
-- Enabled VAR_ACC during this period will not trigger a nanoFIP status byte error.
......
This diff is collapsed.
......@@ -68,13 +68,6 @@ architecture behavioral of tb_masterFIP is
fd_txd_o : out std_logic;
fd_txena_o : out std_logic;
mezz_sys_scl_b : inout std_logic; -- Mezzanine system EEPROM I2C clock
mezz_sys_sda_b : inout std_logic;
carrier_onewire_b : inout std_logic;
carrier_scl_b : inout std_logic;
carrier_sda_b : inout std_logic;
mezz_onewire_b : inout std_logic;
pcb_ver_i : in std_logic_vector(3 downto 0);
prsnt_m2c_n_i : in std_logic;
......@@ -407,10 +400,6 @@ begin
fd_txena_o => fd_txena,
-- other signals on the spec card
carrier_onewire_b => open,
mezz_sys_scl_b => open,
mezz_sys_sda_b => open,
mezz_onewire_b => open,
pcb_ver_i => (others => '0'),
prsnt_m2c_n_i => '0',
......
This diff is collapsed.
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment