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MasterFIP - Gateware
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MasterFIP - Gateware
Commits
4c536a72
Commit
4c536a72
authored
Feb 21, 2023
by
Alén Arias Vázquez
😎
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added spi rmq bridge to the top
parent
687084a8
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2 changed files
with
6 additions
and
3 deletions
+6
-3
Manifest.py
rtl/Manifest.py
+2
-1
svec_masterfip_mt_urv.vhd
top/svec/svec_masterfip_mt_urv.vhd
+4
-2
No files found.
rtl/Manifest.py
View file @
4c536a72
...
...
@@ -9,6 +9,7 @@ files = [
"masterfip_wbgen2_pkg.vhd"
,
"wf_package.vhd"
,
"spi_slave.vhd"
,
"mt_profip_translator.vhd"
"mt_profip_translator.vhd"
,
"spi_rmq_bridge.vhd"
]
top/svec/svec_masterfip_mt_urv.vhd
View file @
4c536a72
...
...
@@ -470,11 +470,13 @@ begin
-- MASTERFIP TRANSLATOR --
---------------------------------------------------------------------------------------------------
cmp_mt_profip_translator
:
entity
work
.
mt_profip_translator
cmp_mt_profip_translator
:
entity
work
.
spi_rmq_bridge
generic
map
(
g_data_width
=>
32
,
g_cpol
=>
0
,
g_cpha
=>
1
)
g_cpha
=>
1
,
g_CDC_ENABLE
=>
0
)
port
map
(
clk_i
=>
clk_62m5_sys
,
rst_n_i
=>
local_reset_n
,
...
...
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