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MasterFIP - Gateware
Commit 4417927b authored by Evangelia Gousiou's avatar Evangelia Gousiou
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- tx, rx frame size increased to 263 bytes for messaging 

- general code cleanup
parent b6d3426e
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rtl/fmc_masterFIP_core.vhd
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rtl/fmc_masterFIP_mezz.vhd
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......@@ -104,7 +104,19 @@ entity fmc_masterFIP_mezz is
rst_sys_n_i : in std_logic; -- reset for 40 MHz logic
-- Bus Speed
speed_b0_i : in std_logic;
speed_b1_i : in std_logic;
speed_b1_i : in std_logic;
-- Bus termination
bus_term_en_n_o : out std_logic;
-- External synchronisation pulse transceiver
ext_sync_term_en_o : out std_logic;
ext_sync_dir_o : out std_logic;
ext_sync_oe_o : out std_logic;
ext_sync_tst_n_o : out std_logic;
ext_sync_i : in std_logic;
-- Power supplies for the ADC
adc_1v8_shdn_n_o : out std_logic;
adc_m5v_shdn_n_o : out std_logic;
adc_5v_en_n_o : out std_logic;
-- FielDrive
fd_rxcdn_i : in std_logic;
fd_rxd_i : in std_logic;
......@@ -114,6 +126,7 @@ entity fmc_masterFIP_mezz is
fd_txck_o : out std_logic;
fd_txd_o : out std_logic;
fd_txena_o : out std_logic;
-- WISHBONE interface with the GN4124/VME_core
-- for the core configuration | data retrieval | core interrupts | 1Wire | I2C
wb_adr_i : in std_logic_vector(31 downto 0);
......@@ -249,6 +262,18 @@ begin
-- Bus Speed
speed_b0_i => speed_b0_i,
speed_b1_i => speed_b1_i,
-- Bus termination
bus_term_en_n_o => bus_term_en_n_o,
-- External synchronisation pulse transceiver
ext_sync_term_en_o => ext_sync_term_en_o,
ext_sync_dir_o => ext_sync_dir_o,
ext_sync_oe_o => ext_sync_oe_o,
ext_sync_tst_n_o => ext_sync_tst_n_o,
ext_sync_i => ext_sync_i,
-- Power supplies for the ADC
adc_1v8_shdn_n_o => adc_1v8_shdn_n_o,
adc_m5v_shdn_n_o => adc_m5v_shdn_n_o,
adc_5v_en_n_o => adc_5v_en_n_o,
-- FielDrive
fd_rxcdn_i => fd_rxcdn_i,
fd_rxd_i => fd_rxd_i,
......@@ -258,8 +283,6 @@ begin
fd_txck_o => fd_txck_o,
fd_txd_o => fd_txd_o,
fd_txena_o => fd_txena_o,
-- Interrupts
irq_p_o => irq_p,
-- WISHBONE CSR for core configuration
wb_adr_i => wb_adr,
wb_dat_i => cnx_master_out(c_WB_SLAVE_CSR).dat,
......@@ -288,32 +311,32 @@ begin
-- WBGEN2 EMBEDDED INTERRUPTS CONTROLLER --
---------------------------------------------------------------------------------------------------
eic : fmc_masterfip_eic
port map
(clk_sys_i => clk_sys_i,
rst_n_i => rst_sys_n_i,
wb_adr_i => cnx_master_out(c_WB_SLAVE_EIC).adr(3 downto 2),
wb_dat_i => cnx_master_out(c_WB_SLAVE_EIC).dat,
wb_dat_o => cnx_master_in(c_WB_SLAVE_EIC).dat,
wb_cyc_i => cnx_master_out(c_WB_SLAVE_EIC).cyc,
wb_sel_i => cnx_master_out(c_WB_SLAVE_EIC).sel,
wb_stb_i => cnx_master_out(c_WB_SLAVE_EIC).stb,
wb_we_i => cnx_master_out(c_WB_SLAVE_EIC).we,
wb_ack_o => cnx_master_in(c_WB_SLAVE_EIC).ack,
wb_stall_o => cnx_master_in(c_WB_SLAVE_EIC).stall,
wb_int_o => wb_irq_o,
irq_macrocy_start_i => irq_p(0),
irq_silen_time_expire_i => irq_p(1),
irq_turnar_time_expire_i => irq_p(2),
irq_tx_completed_i => irq_p(3),
irq_rx_fss_ok_i => irq_p(4),
irq_rx_frame_ok_i => irq_p(5),
irq_rx_crc_wrong_i => irq_p(6));
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Unused wishbone signals
cnx_master_in(c_WB_SLAVE_EIC).err <= '0';
cnx_master_in(c_WB_SLAVE_EIC).rty <= '0';
cnx_master_in(c_WB_SLAVE_EIC).int <= '0';
-- eic : fmc_masterfip_eic
-- port map
-- (clk_sys_i => clk_sys_i,
-- rst_n_i => rst_sys_n_i,
-- wb_adr_i => cnx_master_out(c_WB_SLAVE_EIC).adr(3 downto 2),
-- wb_dat_i => cnx_master_out(c_WB_SLAVE_EIC).dat,
-- wb_dat_o => cnx_master_in(c_WB_SLAVE_EIC).dat,
-- wb_cyc_i => cnx_master_out(c_WB_SLAVE_EIC).cyc,
-- wb_sel_i => cnx_master_out(c_WB_SLAVE_EIC).sel,
-- wb_stb_i => cnx_master_out(c_WB_SLAVE_EIC).stb,
-- wb_we_i => cnx_master_out(c_WB_SLAVE_EIC).we,
-- wb_ack_o => cnx_master_in(c_WB_SLAVE_EIC).ack,
-- wb_stall_o => cnx_master_in(c_WB_SLAVE_EIC).stall,
-- wb_int_o => wb_irq_o,
-- irq_macrocy_start_i => '0',--irq_p(0),
-- irq_silen_time_expire_i => '0',--irq_p(1),
-- irq_turnar_time_expire_i => '0',--irq_p(2),
-- irq_tx_completed_i => '0',--irq_p(3),
-- irq_rx_fss_ok_i => '0',--irq_p(4),
-- irq_rx_frame_ok_i => '0',--irq_p(5),
-- irq_rx_crc_wrong_i => '0');--irq_p(6));
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- Unused wishbone signals
-- cnx_master_in(c_WB_SLAVE_EIC).err <= '0';
-- cnx_master_in(c_WB_SLAVE_EIC).rty <= '0';
-- cnx_master_in(c_WB_SLAVE_EIC).int <= '0';
......
rtl/fmc_masterfip_csr.vhd
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rtl/masterFIP_pkg.vhd
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rtl/masterfip_rx.vhd
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rtl/masterfip_tx.vhd
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rtl/wbgen/fmc_masterfip_csr.wb
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sim/spec/data_vectors/masterFIP_test.vec
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......@@ -29,120 +29,122 @@ wait %d900
-------------------------------------------------------------------------------
--------------- RESETS ---------------
-- reset inactive
wr 0000000000050000 F CAFE0003
wr 0000000000030000 F CAFE0003
wait %d20
-- reset active
wr 0000000000050000 F CAFE0000
wr 0000000000030000 F CAFE0000
wait %d20
-- reset inactive
wr 0000000000050000 F CAFE0003
wr 0000000000030000 F CAFE0003
wait %d20
----- CHECK COUNTERS FUNCTINALITY -----
-- macrocycle cnt start
wr 0000000000030018 F 80007D00
wait %d20
-- turnar counter top
wr 0000000000050014 F 000007D0
wr 000000000003001C F 000007D0
wait %d20
-- silen counter top
wr 0000000000050018 F 00000FA0
wr 0000000000030020 F 00000FA0
wait %d20
-- macrocycle cnt start
wr 0000000000050010 F 80007D00
wait %d20
--------------- ID_DAT ---------------
tx_rst
wr 000000000005002C F 00000001
wr 0000000000030034 F 00000001
wait %d10
wr 000000000005002C F 00000000
wr 0000000000030034 F 00000000
wait %d20
-- control byte of id_dat
wr 00000000000500C4 F 00000003
wr 0000000000030154 F 00000003
wait %d20
-- data bytes varid = 0503 for agent to consume
wr 00000000000500C8 F 00000305
wr 0000000000030158 F 00000305
wait %d20
-- tx_start
wr 000000000005002C F 00000202
wr 0000000000030034 F 00000202
wait %d20000
--------------- RP_DAT ---------------
tx_rst
wr 000000000005002C F 00000001
wr 0000000000030034 F 00000001
wait %d10
wr 000000000005002C F 00000000
wr 0000000000030034 F 00000000
wait %d20
-- control byte of rp_dat
wr 00000000000500c4 F 00000002
wr 0000000000030154 F 00000002
wait %d20
-- data bytes
wr 00000000000500c8 F BBAA0340
wr 0000000000030158 F BBAA0340
wait %d20
wr 00000000000500cc F EEDDCC05
wr 000000000003015c F EEDDCC05
wait %d20
wr 00000000000500d0 F 0A090807
wr 0000000000030160 F 0A090807
wait %d20
wr 00000000000500D4 F 0E0D0C0B
wr 0000000000030164 F 0E0D0C0B
wait %d20
wr 00000000000500D8 F 06060605
wr 0000000000030168 F 06060605
wait %d20
-- tx_start
wr 000000000005002C F 00000502
wr 0000000000030034 F 00000502
wait %d40000
--------------- ID_DAT ---------------
tx_rst
wr 000000000005002C F 00000001
wr 0000000000030034 F 00000001
wait %d10
wr 000000000005002C F 00000000
wr 0000000000030034 F 00000000
wait %d20
-- control byte of id_dat
wr 00000000000500c4 F 00000003
wr 0000000000030154 F 00000003
wait %d20
-- data bytes varid = 1403 for agent to send identification
wr 00000000000500c8 F 00000314
wr 0000000000030158 F 00000314
wait %d20
-- tx_start
wr 000000000005002C F 00000202
wr 0000000000030034 F 00000202
wait %d20
-- deactivate tx_start
wr 000000000005002C F 00000000
wr 0000000000030034 F 00000000
-- release rx_rst
wr 0000000000050038 F 00000000
wr 0000000000030040 F 00000000
wait %d40000
-- read received data
rd 0000000000050040 F 00000002
rd 0000000000030048 F 00000002
wait %d20
rd 0000000000050044 F 00000050
rd 000000000003004c F 00000050
--------------- RP_FIN ---------------
-- control byte of rp_fin
wr 00000000000500C4 F 00000040
wr 0000000000030154 F 00000040
wait %d20
-- rx_rst
wr 0000000000050038 F 00000001
wr 0000000000030040 F 00000001
wait %d20
-- tx_start
wr 000000000005002C F 00000002
wr 0000000000030034 F 00000002
wait %d20000
\ No newline at end of file
sim/spec/testbench/tb_masterFIP.vhd
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......@@ -59,6 +59,10 @@ architecture behavioral of tb_masterFIP is
tx_error_i : in std_logic; -- Transmit Error
irq_p_o : out std_logic; -- Interrupt request pulse to GN4124 GPIO
ext_sync_i : in std_logic;
speed_b0_i : in std_logic;
speed_b1_i : in std_logic;
fd_rxcdn_i : in std_logic;
fd_rxd_i : in std_logic;
fd_txer_i : in std_logic;
......@@ -388,7 +392,11 @@ begin
l_wr_rdy_i => l_wr_rdy,
p_rd_d_rdy_i => p_rd_d_rdy,
tx_error_i => tx_error,
irq_p_o => irq_p,
ext_sync_i => '0',
speed_b0_i => '0',
speed_b1_i => '1',
fd_rxcdn_i => fd_rxcdn,
fd_rxd_i => fd_rxd,
......
syn/spec/spec_masterFIP.xise
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top/spec/spec_masterFIP.ucf
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......@@ -67,6 +67,32 @@ NET "led_rx_err_n_o" IOSTANDARD = "LVCMOS25";
NET "led_rx_act_n_o" LOC = A20;
NET "led_rx_act_n_o" IOSTANDARD = "LVCMOS25";
NET "bus_term_en_n_o" LOC = Y13;
NET "bus_term_en_n_o" IOSTANDARD = "LVCMOS25";
NET "ext_sync_term_en_o" LOC = AB13;
NET "ext_sync_term_en_o" IOSTANDARD = "LVCMOS25";
NET "ext_sync_i" LOC = T8;
NET "ext_sync_i" IOSTANDARD = "LVCMOS25";
NET "ext_sync_tst_n_o" LOC = U8;
NET "ext_sync_tst_n_o" IOSTANDARD = "LVCMOS25";
NET "ext_sync_oe_o" LOC = W6;
NET "ext_sync_oe_o" IOSTANDARD = "LVCMOS25";
NET "ext_sync_dir_o" LOC = Y6;
NET "ext_sync_dir_o" IOSTANDARD = "LVCMOS25";
NET "adc_1v8_shdn_n_o" LOC = V17;
NET "adc_1v8_shdn_n_o" IOSTANDARD = "LVCMOS25";
NET "adc_m5v_shdn_n_o" LOC = W18;
NET "adc_m5v_shdn_n_o" IOSTANDARD = "LVCMOS25";
NET "adc_5v_en_n_o" LOC = R9;
NET "adc_5v_en_n_o" IOSTANDARD = "LVCMOS25";
#NET "mezz_onewire_b" LOC = "A19";
#NET "mezz_onewire_b" IOSTANDARD = "LVCMOS25";
......
top/spec/spec_masterFIP.vhd
View file @ 4417927b
......@@ -147,6 +147,21 @@ entity spec_masterFIP is
-- Bus Speed
speed_b0_i : in std_logic;
speed_b1_i : in std_logic;
-- Bus termination
bus_term_en_n_o : out std_logic;
-- External synchronisation pulse transceiver
ext_sync_term_en_o : out std_logic;
ext_sync_dir_o : out std_logic;
ext_sync_oe_o : out std_logic;
ext_sync_tst_n_o : out std_logic;
ext_sync_i : in std_logic;
-- Power supplies for the ADC
adc_1v8_shdn_n_o : out std_logic;
adc_m5v_shdn_n_o : out std_logic;
adc_5v_en_n_o : out std_logic;
-- FielDrive
fd_rxcdn_i : in std_logic;
......@@ -184,11 +199,10 @@ architecture rtl of spec_masterFIP is
-- Note: All address in sdb and crossbar are BYTE addresses!
-- Master ports on the wishbone crossbar
constant c_NUM_WB_MASTERS : integer := 4;
constant c_NUM_WB_MASTERS : integer := 3;
constant c_WB_SLAVE_SPEC_ONEWIRE: integer := 0; -- Carrier onewire interface
constant c_WB_SLAVE_SPEC_INFO : integer := 1; -- Info on SPEC control and status registers
constant c_WB_SLAVE_VIC : integer := 2; -- Interrupt controller
constant c_WB_SLAVE_MASTERFIP : integer := 3; -- TDC core configuration
constant c_WB_SLAVE_MASTERFIP : integer := 2; -- TDC core configuration
-- SDB header address
constant c_SDB_ADDRESS : t_wishbone_address := x"00000000";
......@@ -197,21 +211,13 @@ architecture rtl of spec_masterFIP is
constant c_NUM_WB_SLAVES : integer := 1;
constant c_MASTER_GENNUM : integer := 0;
constant c_FMC_MASTERFIP_SDB_BRIDGE : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"0001FFFF", x"00000000");
constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(5 downto 0) :=
constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(4 downto 0) :=
(0 => f_sdb_embed_device (c_ONEWIRE_SDB_DEVICE, x"00010000"),
1 => f_sdb_embed_device (c_SPEC_INFO_SDB_DEVICE, x"00020000"),
2 => f_sdb_embed_device (c_xwb_vic_sdb, x"00030000"), -- c_xwb_vic_sdb described in the wishbone_pkg
3 => f_sdb_embed_bridge (c_FMC_MASTERFIP_SDB_BRIDGE, x"00040000"),
4 => f_sdb_embed_repo_url (c_sdb_repo_url),
5 => f_sdb_embed_synthesis (c_sdb_synthesis_info));
---------------------------------------------------------------------------------------------------
-- VIC CONSTANT --
---------------------------------------------------------------------------------------------------
constant c_VIC_VECTOR_TABLE : t_wishbone_address_array(0 to 0) := (0 => x"00052000");
2 => f_sdb_embed_device (c_MASTERFIP_SDB_DEVICE, x"00030000"),
3 => f_sdb_embed_repo_url (c_SDB_REPO_URL),
4 => f_sdb_embed_synthesis (c_SDB_SYNTHESIS_INFO));
---------------------------------------------------------------------------------------------------
......@@ -403,10 +409,10 @@ begin
dma_sel_o => open,
dma_stb_o => open,
dma_we_o => open,
dma_err_i => '0',
dma_err_i => '0',
dma_ack_i => '1',
dma_rty_i => '0',
dma_int_i => '0',
dma_rty_i => '0',
dma_int_i => '0',
dma_dat_i => (others => '0'),
dma_stall_i => '0',
dma_reg_clk_i => clk_40m_sys,
......@@ -428,38 +434,50 @@ begin
---------------------------------------------------------------------------------------------------
-- masterFIP BOARD --
---------------------------------------------------------------------------------------------------
cmp_masterFIP_mezz : fmc_masterFIP_mezz
cmp_masterFIP_mezz : fmc_masterFIP_core
generic map
(g_span => g_span,
g_width => g_width,
values_for_simul => FALSE)
(g_span => 32,
g_width => 32,
values_for_simul => FALSE)
port map
(clk_sys_i => clk_40m_sys,
rst_sys_n_i => rst_sys_n,
fd_rxcdn_i => fd_rxcdn_i,
fd_rxd_i => fd_rxd_i,
fd_txer_i => fd_txer_i,
fd_wdgn_i => fd_wdgn_i,
fd_rstn_o => fd_rstn_o,
fd_txck_o => fd_txck_o,
fd_txd_o => fd_txd_o,
fd_txena_o => fd_txena,
speed_b0_i => speed_b0_i,
speed_b1_i => speed_b1_i,
(clk_i => clk_40m_sys,
rst_i => rst_sys,
-- FielDrive
fd_rxcdn_i => fd_rxcdn_i,
fd_rxd_i => fd_rxd_i,
fd_txer_i => fd_txer_i,
fd_wdgn_i => fd_wdgn_i,
fd_rstn_o => fd_rstn_o,
fd_txck_o => fd_txck_o,
fd_txd_o => fd_txd_o,
fd_txena_o => fd_txena,
-- Bus bit rate
speed_b0_i => speed_b0_i,
speed_b1_i => speed_b1_i,
-- Bus termination
bus_term_en_n_o => bus_term_en_n_o,
-- External synchronisation pulse transceiver
ext_sync_term_en_o => ext_sync_term_en_o,
ext_sync_dir_o => ext_sync_dir_o,
ext_sync_oe_o => ext_sync_oe_o,
ext_sync_tst_n_o => ext_sync_tst_n_o,
ext_sync_i => ext_sync_i,
-- Power supplies for the ADC
adc_1v8_shdn_n_o => adc_1v8_shdn_n_o,
adc_m5v_shdn_n_o => adc_m5v_shdn_n_o,
adc_5v_en_n_o => adc_5v_en_n_o,
-- WISHBONE interface with the GN4124 core
wb_adr_i => cnx_master_out(c_WB_SLAVE_MASTERFIP).adr,
wb_dat_i => cnx_master_out(c_WB_SLAVE_MASTERFIP).dat,
wb_stb_i => cnx_master_out(c_WB_SLAVE_MASTERFIP).stb,
wb_we_i => cnx_master_out(c_WB_SLAVE_MASTERFIP).we,
wb_cyc_i => cnx_master_out(c_WB_SLAVE_MASTERFIP).cyc,
wb_sel_i => cnx_master_out(c_WB_SLAVE_MASTERFIP).sel,
wb_dat_o => cnx_master_in(c_WB_SLAVE_MASTERFIP).dat,
wb_ack_o => cnx_master_in(c_WB_SLAVE_MASTERFIP).ack,
wb_stall_o => cnx_master_in(c_WB_SLAVE_MASTERFIP).stall,
-- Interrupt line from EIC
wb_irq_o => fmc_eic_irq,
wb_adr_i => "00" & cnx_master_out(c_WB_SLAVE_MASTERFIP).adr(31 downto 2),
wb_dat_i => cnx_master_out(c_WB_SLAVE_MASTERFIP).dat,
wb_stb_i => cnx_master_out(c_WB_SLAVE_MASTERFIP).stb,
wb_we_i => cnx_master_out(c_WB_SLAVE_MASTERFIP).we,
wb_cyc_i => cnx_master_out(c_WB_SLAVE_MASTERFIP).cyc,
wb_sel_i => cnx_master_out(c_WB_SLAVE_MASTERFIP).sel,
wb_dat_o => cnx_master_in(c_WB_SLAVE_MASTERFIP).dat,
wb_ack_o => cnx_master_in(c_WB_SLAVE_MASTERFIP).ack,
wb_stall_o => cnx_master_in(c_WB_SLAVE_MASTERFIP).stall,
-- Aux
aux_o => aux);
aux_o => aux);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Unused wishbone signals
cnx_master_in(c_WB_SLAVE_MASTERFIP).err <= '0';
......@@ -480,7 +498,7 @@ begin
port map (
clk_i => clk_40m_sys,
rst_n_i => rst_sys_n,
pulse_i => aux(2),
pulse_i => aux(0),
extended_o => rx_err);
cmp_rx_act_extend_p : gc_extend_pulse
......@@ -492,23 +510,6 @@ begin
pulse_i => aux(1),
extended_o => rx_act);
---------------------------------------------------------------------------------------------------
-- VIC --
---------------------------------------------------------------------------------------------------
cmp_vic : xwb_vic
generic map
(g_interface_mode => PIPELINED,
g_address_granularity => BYTE,
g_num_interrupts => 1,
g_init_vectors => c_VIC_VECTOR_TABLE)
port map
(clk_sys_i => clk_40m_sys,
rst_n_i => rst_sys_n,
slave_i => cnx_master_out(c_WB_SLAVE_VIC),
slave_o => cnx_master_in(c_WB_SLAVE_VIC),
irqs_i(0) => fmc_eic_irq,
irq_master_o => irq_to_gn4124);
---------------------------------------------------------------------------------------------------
-- Carrier 1-wire MASTER DS18B20 (thermometer + unique ID) --
......@@ -531,7 +532,7 @@ begin
owr_i => carrier_owr_i);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
carrier_onewire_b <= '0' when carrier_owr_en(0) = '1' else 'Z';
carrier_onewire_b <= '0' when carrier_owr_en(0) = '1' else 'Z';
carrier_owr_i(0) <= carrier_onewire_b;
......
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