Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
M
MasterFIP - Gateware
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
0
Issues
0
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
Wiki
Wiki
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Commits
Issue Boards
Open sidebar
Projects
MasterFIP - Gateware
Commits
21ef2622
Commit
21ef2622
authored
Feb 22, 2023
by
kblantos
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
syntax errors fix
parent
4c536a72
Hide whitespace changes
Inline
Side-by-side
Showing
1 changed file
with
18 additions
and
22 deletions
+18
-22
spi_rmq_bridge.vhd
rtl/spi_rmq_bridge.vhd
+18
-22
No files found.
rtl/spi_rmq_bridge.vhd
View file @
21ef2622
...
...
@@ -26,7 +26,7 @@ entity spi_rmq_bridge is
generic
(
g_DATA_WIDTH
:
natural
;
g_CPOL
:
natural
range
0
to
1
;
g_CP
A
:
natural
range
0
to
1
;
g_CP
HA
:
natural
range
0
to
1
;
g_CDC_ENABLE
:
natural
range
0
to
1
;
g_INPUT_FIFO_DEPTH
:
natural
:
=
512
;
g_OUTPUT_FIFO_DEPTH
:
natural
:
=
1024
...
...
@@ -63,23 +63,21 @@ architecture rtl of spi_rmq_bridge is
signal
s_spi_clk_re
:
std_logic
;
signal
s_spi_clk_fe
:
std_logic
;
attribute
fsm_encoding
:
string
;
--! SPI FSM:
--type t_SPI_STATE is (RX_SPI_HEADER, PROCESSING, WR_RMQ, RD_RMQ);
type
t_SPI_STATE
is
(
RX_SPI_HEADER
,
WR_RMQ
,
RD_RMQ
,
CS_DEASSERT
);
signal
s_spi_state
:
t_SPI_STATE
;
attribute
fsm_encoding
:
string
;
attribute
fsm_encoding
of
s_spi_state
:
signal
is
"one_hot"
;
--! WR RMQ:
type
t_WR_RMQ
is
(
IDLE
,
WR_MSB
,
WR_LSB
);
signal
s_wr_rmq_state
:
t_WR_RMQ
;
attribute
fsm_encoding
:
string
;
attribute
fsm_encoding
of
s_wr_rmq_state
:
signal
is
"one_hot"
;
--! RD RMQ:
type
t_RD_RMQ
is
(
RD_HEADER
,
RD_DATA
);
type
t_RD_RMQ
is
(
RD_HEADER
,
RD_DATA
_LSB
,
RD_DATA_MSB
);
signal
s_rd_rmq_state
:
t_RD_RMQ
;
attribute
fsm_encoding
:
string
;
attribute
fsm_encoding
of
s_rd_rmq_state
:
signal
is
"one_hot"
;
--! Signals FSM
...
...
@@ -105,7 +103,7 @@ architecture rtl of spi_rmq_bridge is
--! FIFO MOSI
signal
s_mosi_lsb
:
std_logic_vector
((
g_data_width
/
2
)
-1
downto
0
);
signal
s_mosi_msb
:
std_logic_vector
((
g_data_width
/
2
)
-1
downto
0
)
signal
s_mosi_msb
:
std_logic_vector
((
g_data_width
/
2
)
-1
downto
0
)
;
signal
s_mosi_header
:
std_logic
;
signal
s_mosi_valid
:
std_logic
;
signal
s_mosi_last
:
std_logic
;
...
...
@@ -175,13 +173,13 @@ begin
-- Define the sampling and shifting based on the CPHA
gen_pha_zero
:
if
g_cpha
=
0
generate
sample_en
<=
s
pi_clk_redg
e
;
shift_en
<=
s
pi_clk_fedg
e
;
sample_en
<=
s
_spi_clk_r
e
;
shift_en
<=
s
_spi_clk_f
e
;
end
generate
;
gen_pha_one
:
if
g_cpha
=
1
generate
sample_en
<=
s
pi_clk_fedg
e
;
shift_en
<=
s
pi_clk_redg
e
;
sample_en
<=
s
_spi_clk_f
e
;
shift_en
<=
s
_spi_clk_r
e
;
end
generate
;
----------------------------------------------------------------------------
...
...
@@ -191,7 +189,7 @@ begin
if
rising_edge
(
clk_i
)
then
if
rst_n_i
=
'0'
then
s_spi_state
<=
RX
;
s_spi_state
<=
RX
_SPI_HEADER
;
s_tx_shreg
<=
(
others
=>
'0'
);
s_rx_shreg
<=
(
others
=>
'0'
);
s_tx_bit_c
<=
(
others
=>
'0'
);
...
...
@@ -344,11 +342,11 @@ begin
----------------------------------------------------------------------------
--! RD RMQ FIFO
if
g_CDC_ENABLE
=
0
then
generate
gen_miso_fifo
:
if
g_CDC_ENABLE
=
0
generate
cmp_output_fifo
:
entity
work
.
inferred_sync_fifo
generic
map
(
g_data_width
=>
g_DATA_WIDTH
,
g_size
=>
g_FIFO_DEPTH
,
g_size
=>
g_
OUTPUT_
FIFO_DEPTH
,
g_show_ahead
=>
true
,
g_with_empty
=>
true
,
g_with_full
=>
true
,
...
...
@@ -357,8 +355,7 @@ begin
g_with_count
=>
false
,
g_almost_empty_threshold
=>
0
,
g_almost_full_threshold
=>
0
,
g_register_flag_outputs
=>
False
,
g_memory_implementation_hint
=>
"auto"
g_register_flag_outputs
=>
False
)
port
map
(
rst_n_i
=>
rst_n_i
,
...
...
@@ -373,7 +370,7 @@ begin
almost_full_o
=>
open
,
count_o
=>
open
);
end
generate
;
end
generate
gen_miso_fifo
;
s_miso_rd_en
<=
s_ready
and
not
(
s_miso_fifo_rd_empty
);
...
...
@@ -388,7 +385,7 @@ begin
case
s_rd_rmq_state
is
------------------------------------------
when
RD_HEADER
=>
if
s_miso_fifo_wr_full
=
'0'
and
rmq_snk_i
.
valid
=
'1'
and
rmq_snk_i
.
hdr
=
'1'
if
s_miso_fifo_wr_full
=
'0'
and
rmq_snk_i
.
valid
=
'1'
and
rmq_snk_i
.
hdr
=
'1'
then
s_miso_fifo_data_in
(
31
downto
0
)
<=
rmq_snk_i
.
data
;
s_miso_fifo_data_in
(
32
)
<=
'0'
;
s_miso_wr_en
<=
'1'
;
...
...
@@ -490,7 +487,7 @@ begin
end
if
;
end
process
p_wr_rmq
;
if
g_CDC_ENABLE
=
0
then
generate
gen_mosi_fifo
:
if
g_CDC_ENABLE
=
0
generate
cmp_input_fifo
:
entity
work
.
inferred_sync_fifo
generic
map
(
g_data_width
=>
g_DATA_WIDTH
+
4
,
...
...
@@ -503,8 +500,7 @@ begin
g_with_count
=>
false
,
g_almost_empty_threshold
=>
0
,
g_almost_full_threshold
=>
0
,
g_register_flag_outputs
=>
False
,
g_memory_implementation_hint
=>
"auto"
g_register_flag_outputs
=>
False
)
port
map
(
rst_n_i
=>
rst_n_i
,
...
...
@@ -519,7 +515,7 @@ begin
almost_full_o
=>
open
,
count_o
=>
open
);
end
generate
;
end
generate
gen_mosi_fifo
;
rmq_src_o
.
data
<=
s_mosi_fifo_data_out
(
31
downto
0
);
rmq_src_o
.
hdr
<=
s_mosi_fifo_data_out
(
35
);
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment