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MasterFIP - Gateware
Commit 05b8b96d authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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spec_masterfip_mt: added simulation-only virtual Wishbone/clock ports

parent 2d6f9d2e
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Showing with 35 additions and 7 deletions
top/spec/spec_masterfip_mt.vhd
View file @ 05b8b96d
......@@ -155,7 +155,8 @@ use work.masterfip_wbgen2_pkg.all; -- for the masterfip_wbgen2_csr records
entity spec_masterfip_mt is
generic (g_simul : boolean := false);
generic (g_simulation : boolean := false;
g_sim_bypass_gennum : boolean := false);
port
(-- Carrier signals
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
......@@ -245,7 +246,14 @@ entity spec_masterfip_mt is
-- To be removed on hw V3
adc_1v8_shdn_n_o : out std_logic;
adc_m5v_shdn_n_o : out std_logic;
adc_5v_en_n_o : out std_logic);
adc_5v_en_n_o : out std_logic
-- synthesis translate_off
;
sim_clk_sys_i : in std_logic;
sim_wb_i : in t_wishbone_slave_in := cc_dummy_slave_in;
sim_wb_o : out t_wishbone_slave_out
-- synthesis translate_on
);
end spec_masterfip_mt;
......@@ -344,6 +352,17 @@ architecture rtl of spec_masterfip_mt is
signal spec_led : std_logic_vector(7 downto 0);
signal fd_txd : std_logic;
function f_resize( x : string; len : integer) return string is
variable s : string(1 to len);
begin
s(1 to x'length) := x;
for i in x'length + 1 to len loop
s(i) := ' ';
end loop;
s(x'length+1) := character'val(0);
return s;
end f_resize;
--=================================================================================================
-- architecture begin
......@@ -370,12 +389,13 @@ begin
---------------------------------------------------------------------------------------------------
cmp_mock_turtle : spec_node_template
generic map
(g_simulation => g_simul,
(g_simulation => g_simulation,
g_with_wr_phy => false, -- no White Rabbit support, dah
g_with_white_rabbit => false,
g_double_wrnode_core_clock => false,
g_system_clock_freq => 100000000, -- both CPUs at 100 MHz
g_wr_node_config => C_NODE_CONFIG)
g_wr_node_config => C_NODE_CONFIG,
g_sim_bypass_gennum => g_sim_bypass_gennum)
port map
(clk_125m_pllref_p_i => clk_125m_pllref_p_i,
clk_125m_pllref_n_i => clk_125m_pllref_n_i,
......@@ -423,7 +443,15 @@ begin
-- not used
clk_20m_vcxo_i => '0',
clk_125m_gtp_n_i => '0',
clk_125m_gtp_p_i => '1');
clk_125m_gtp_p_i => '1'
-- do not wire simulation-only ports when synthesizing
-- synthesis translate_off
,
sim_clk_sys_i => sim_clk_sys_i,
sim_slave_i => sim_wb_i,
sim_slave_o => sim_wb_o
-- synthesis translate_on
);
---------------------------------------------------------------------------------------------------
......@@ -462,7 +490,7 @@ begin
generic map
(g_span => 32,
g_width => 32,
g_simul => g_simul)
g_simul => g_simulation)
port map
(clk_i => clk_100m_sys,
rst_n_i => rst_n_sys,
......@@ -548,4 +576,4 @@ end rtl;
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
--------------------------------------------------------------------------------------------------
\ No newline at end of file
--------------------------------------------------------------------------------------------------
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