Erik van der Bij · 8d2dae34
--- a/Home.md
+++ b/Home.md
+# Scalable MAROC Charge Sensitive Readout
+
+## Project description
+
+The Scalable MAROC Charge Sensitive Readout couples a MAROC ASIC (64
+channels each with a fixed threshold discriminator and a slow shaper +
+sample-and-hold + 12-bit ADC) to a FPGA. Read-out by Gigabit Ethernet
+(firmware supplied supports IPBus). Multiple boards can be plugged
+together to increase the channel count. Clocking circuitry compatible
+with the White Rabbit implementation of PTP.
+
+*TEMPLATE TO BE FILLED
+IN**
+
+[![](/project/white-rabbit/uploads/11578355de03b7cc74a366b23b508c48/svectop_s.png)](/project/white-rabbit/uploads/0eeb5b430351eca8a4e76a5af3892c2c/svectop_l.png)  
+*SVEC V1 production board** - [block
+diagram](https://www.ohwr.org/project/svec/uploads/e234fa371e49b0d8f0311cdd236df19c/Block.png)
+
+## Main Features
+
+  - VME64x interface
+  - Two Low-Pin Count FMC slots
+      - Vadj fixed to 2.5V
+      - No dedicated clock signals from Carrier to FMC (as only
+        available on HPC pins and use LPC)
+      - FMC connectivity: all 34 differential pairs connected, 1 GTP
+        transceiver with clock, 2 clock pairs, JTAG
+  - Xilinx FPGAs
+      - Application FPGA: Spartan-6 XC6SLX150T-3FGG900C
+          - Direct connection to all resources such as VME64x, memories
+            and FMC connectors
+      - System FPGA: Spartan-6 XC6SLX9-2FTG256C
+          - Provides VME bootloader, early oscillator/PLL config
+          - Configuration Flash memory for both Main FPGA and
+            Application FPGA configuration
+  - FPGA configuration
+      - From SPI flash or via VME
+  - Clocking resources
+      - 1x 10-280 MHz I2C Programmable XO Oscillator, starts up at 100
+        MHz (Silicon Labs Si570, freely usable)
+      - 1x 25 MHz TCXO controlled by a DAC with SPI interface (AD5662,
+        used by [White Rabbit PTP
+        core](https://www.ohwr.org/wr-cores/wikis/Wrpc-core))
+      - 1x 20 MHz VCXO controlled by a DAC with SPI interface (AD5662,
+        used by [White Rabbit PTP
+        core](https://www.ohwr.org/wr-cores/wikis/Wrpc-core))
+      - 2x low-jitter frequency synthesizer/fanout (TI CDCM61004, fixed
+        configuration, Fout=125 MHz, used by [White Rabbit PTP
+        core](https://www.ohwr.org/wr-cores/wikis/Wrpc-core))
+  - On-board memories
+      - 2x 256 MByte (2 Gbit) DDR3 (16-bit bus, MT41J128M16JT-125)
+      - 1x 128 Mbit SPI flash for FPGA firmware storage (M25P128-VME6GB)
+      - 64kbit EEPROM connected for storing application parameters
+        (24AA64T-I/MC)
+      - 1x I2C configuration EEPROM (24LC64)
+  - Miscellaneous
+      - On-board thermometer IC (DS18B20U+)
+      - Unique 64-bit identifier (DS18B20U+)
+  - Front panel
+      - 1x SFP port ([White
+        Rabbit](https://www.ohwr.org/project/white-rabbit/wikis/)
+        compatible)
+      - 4x LEMO/SMC programmable I/Os capable of driving 3.3V @ 50 ohm
+      - 2x mini displayPort connectors for high-speed serial GTP links
+        (not for video)
+      - 8x Programmable LED
+      - Reset push button
+  - Internal connectors
+      - VME P2 connector provides access to a Rear Transition Module
+        (compatible to
+        [VFC](https://www.ohwr.org/project/fmc-vme-carrier/wiki))
+          - 40 user defined single ended (Vcco=2.5V) signals (or 20 LVDS
+            pairs) connected to the Application FPGA
+          - 2x 125 MHz LVDS clocks provided to the RTM
+      - Xilinx-style JTAG connector
+      - Internal mini USB 2.0 High Speed connector for stand-alone
+        applications (CP2103)
+  - Optional features, check with vendor
+      - Internal 2 x SATA connector for stand-alone PCI Express
+        connectivity (clock + data)
+      - Internal 4 x UFL connectors with low-jitter clock for FMC cards
+      - Internal additional USB 2.0 on 4-pin header (FT2232HL)
+      - Battery for secure storage of FPGA configuration data
+      - Stand-alone features
+          - External supply connector (3.3V, 5V) on internal SATA
+            connector
+          - PCIe interface on internal SATA connector
+  - 10-layer PCB
+
+-----
+
+## Project information
+
+  - Official production documentation:
+    [EDA-02530](http://edms.cern.ch/nav/eda-02530)
+  - [Hardware
+    manual](http://www.janztec.com/fileadmin/downloads/manuals/manual_svec_hardware.pdf)
+    (Janz Tec)
+      - [Block diagram](https://www.ohwr.org/project/svec/uploads/e234fa371e49b0d8f0311cdd236df19c/Block.png)
+  - [CERN specific information](CERN)
+  - [Users](Users)
+  - [Software](Software)
+  - [Standard Gateware](https://www.ohwr.org/project/svec/wikis/documents) (and
+    [how to use it](https://www.ohwr.org/project/svec/wikis/Documents/SVEC-Gateware-Manual))
+  - [Frequently Asked Questions](FAQ)
+
+-----
+
+## [Releases](Releases)
+
+*Latest:**
+
+  - Hardware: v3.0 -
+    [EDA-02530-V3-0](https://edms.cern.ch/nav/EDA-02530-V3-0)
+  - Gateware: v3.0 - [Gateware release 3.0](Gateware-Release-3-0)
+  - Linux driver: see [Software support for
+    SVEC](https://www.ohwr.org/project/svec-sw/wiki) Project
+
+*All Gateware releases:** See the [Releases](Releases) page.
+
+-----
+
+## Contacts
+
+### Commercial producers
+
+  - [SVEC - BO-FVM-SVEC0](http://www.janztec.com/en/vme64xsvec.html)
+    [Janz Tec AG](http://www.janztec.com/en/), Germany
+
+### General question about project
+
+  - [Erik van der Bij](mailto:Erik.van.der.Bij@cern.ch) - CERN
+
+-----
+
+## Status
+
+<table>
+<tbody>
+<tr class="odd">
+<td><strong>Date</strong></td>
+<td><b> Event </b></td>
+</tr>
+<tr class="even">
+<td>01-07-2011</td>
+<td>First ideas for starting this simpler and cheaper version of the [FMC VME Carrier](https://www.ohwr.org/project/fmc-vme-carrier).</td>
+</tr>
+<tr class="odd">
+<td>19-07-2011</td>
+<td>Main features specification written.</td>
+</tr>
+<tr class="even">
+<td>25-10-2011</td>
+<td>Order sent out to a company for the schematics design.</td>
+</tr>
+<tr class="odd">
+<td>02-05-2012</td>
+<td>V0 files created. Ordered 4 assembled boards.</td>
+</tr>
+<tr class="even">
+<td>05-06-2012</td>
+<td>V1: replace eSATA by microHDMI, remove front USB (space reasons).</td>
+</tr>
+<tr class="odd">
+<td>15-06-2012</td>
+<td>Four V0 boards received at CERN.</td>
+</tr>
+<tr class="even">
+<td>21-06-2012</td>
+<td>V0: VME works, bootloader works, White Rabbit works, FMC slots work (two Fine Delay cards operating correctly)</td>
+</tr>
+<tr class="odd">
+<td>04-09-2012</td>
+<td>V1 of design released. Ordered 9. Price Enquiry for production of 90 will follow soon.</td>
+</tr>
+<tr class="even">
+<td>24-10-2012</td>
+<td>Four V1 boards received.</td>
+</tr>
+<tr class="odd">
+<td>01-11-2012</td>
+<td>V2 design files released. <a href="https://www.ohwr.org/project/svec/versions/12">Minor corrections</a> on mechanics and one electrical issue.</td>
+</tr>
+<tr class="even">
+<td>05-11-2012</td>
+<td>90 boards ordered. 30 for delivery end January 2013, 60 for end March 2013.</td>
+</tr>
+<tr class="odd">
+<td>08-02-2013</td>
+<td>30 V1-0 boards received at CERN.</td>
+</tr>
+<tr class="even">
+<td>17-07-2013</td>
+<td>10 V2-0 pre-series boards received.</td>
+</tr>
+<tr class="odd">
+<td>31-07-2013</td>
+<td>28 additional board ordered.</td>
+</tr>
+<tr class="even">
+<td>09-10-2013</td>
+<td>50 V2-0 series boards received.</td>
+</tr>
+<tr class="odd">
+<td>08-11-2013</td>
+<td>28 V2-0 series boards received (in total 118 received).</td>
+</tr>
+<tr class="even">
+<td>05-12-2013</td>
+<td><a href="http://www.janztec.com/fileadmin/downloads/manuals/manual_svec_hardware.pdf">Hardware manual</a> written by Janz Tec.</td>
+</tr>
+<tr class="odd">
+<td>02-04-2014</td>
+<td><a href="Gateware-Release-2-0">Release 2.0</a> of the SVEC standard gateware (bootloader &amp; golden) is available</td>
+</tr>
+<tr class="even">
+<td>20-10-2014</td>
+<td>V3-0 released. Changes can be seen in [Roadmap](https://www.ohwr.org/project/svec/roadmap?completed=1)</td>
+</tr>
+<tr class="odd">
+<td>26-11-2014</td>
+<td><a href="Gateware-Release-3-0">Release 3.0</a> of the SVEC bootloader is available</td>
+</tr>
+</tbody>
+</table>
+
+-----
+
+17 March 2015
+
+
+
+### Files
+* [Maroc_topside_s.jpg](/uploads/47d737deae7c9d6edc8b8e80d4910566/Maroc_topside_s.jpg)
+* [Maroc_topside_l.jpg](/uploads/0ddbf24ce2053f510e161890dc755e23/Maroc_topside_l.jpg)
+* [Maroc_bottomside_l.jpg](/uploads/09e95fb941d310565dd1bcbb79cc2ab1/Maroc_bottomside_l.jpg)
+* [Maroc_bottomside_s.jpg](/uploads/0bf7f3527349323fd61d0e90f4b63349/Maroc_bottomside_s.jpg)
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