hdl: reformatting

f75d5e11 · Tristan Gingold · da511871 · f75d5e11 · f75d5e11 · f75d5e11
Commit f75d5e11 authored May 12, 2022 by Tristan Gingold
12 changed files
--- a/hdl/dpram_generic.vhd
+++ b/hdl/dpram_generic.vhd
--- a/hdl/ram_voter.vhd
+++ b/hdl/ram_voter.vhd
@@ -23,52 +23,40 @@ use ieee.numeric_std.all;
 use work.voter.all;
 entity ram_voter is
-	generic (
+  generic (
-		g_addr_width : natural := 15;
+    g_addr_width : natural := 15;
-                g_data_width : natural := 38
+    g_data_width : natural := 38
+  );
-		);
+  port (
-    port (
+    da_vot_i         : in  t_voter_stdvector (open)(g_data_width-1 downto 0);
-		da_vot_i : in t_voter_stdvector (open)(g_data_width-1 downto 0);
+    aa_vot_i         : in  t_voter_stdvector (open) (g_addr_width-1 downto 0);
-		aa_vot_i : in t_voter_stdvector (open) (g_addr_width-1 downto 0);
+    wa_vot_i         : in  t_voter_stdlogic;
-		wa_vot_i : in t_voter_stdlogic;
+    ra_vot_i         : in  t_voter_stdlogic;
-		ra_vot_i : in t_voter_stdlogic;
+    lock_a_req_vot_i : in  t_voter_stdlogic;
-        lock_a_req_vot_i : in t_voter_stdlogic;
+    da_o             : out std_logic_vector (g_data_width-1 downto 0);
-		da_o :	out std_logic_vector (g_data_width-1 downto 0);
+    aa_o             : out std_logic_vector (g_addr_width-1 downto 0);
-		aa_o :	out std_logic_vector (g_addr_width-1 downto 0);
+    wa_o             : out std_logic;
-		wa_o :	out std_logic;
+    ra_o             : out std_logic;
-		ra_o : out std_logic;
+    lock_a_req_o     : out std_logic
-        lock_a_req_o : out std_logic
+  );
-      );
 end ram_voter;
 architecture rtl of ram_voter is
 begin
  da : for i in da_o'range generate
    da_o(i) <= (da_vot_i(1)(i) and da_vot_i(2)(i)) or (da_vot_i(2)(i) and da_vot_i(3)(i)) or (da_vot_i(1)(i) and da_vot_i(3)(i));
  end generate;
  aa : for i in aa_o'range generate
    aa_o(i) <= (aa_vot_i(1)(i) and aa_vot_i(2)(i)) or (aa_vot_i(2)(i) and aa_vot_i(3)(i)) or (aa_vot_i(1)(i) and aa_vot_i(3)(i));
  end generate; 
  wa_o <= (wa_vot_i(1) and wa_vot_i(2)) or (wa_vot_i(2) and wa_vot_i(3)) or (wa_vot_i(1) and wa_vot_i(3));
  ra_o <= (ra_vot_i(1) and ra_vot_i(2)) or (ra_vot_i(2) and ra_vot_i(3)) or (ra_vot_i(1) and ra_vot_i(3));
  lock_a_req_o <= (lock_a_req_vot_i(1) and lock_a_req_vot_i(2)) or (lock_a_req_vot_i(2) and lock_a_req_vot_i(3)) or (lock_a_req_vot_i(1) and lock_a_req_vot_i(3));
 end architecture;
--- a/hdl/secded_ecc.vhd
+++ b/hdl/secded_ecc.vhd
@@ -165,7 +165,6 @@ architecture rtl of secded_ecc is
  end f_ecc_errors;
  function f_ecc_one_error (syndrome : std_logic_vector (6 downto 0)) return std_logic is
-    variable syndrome_bound_check : std_logic;
  begin
        if Is_x (syndrome (0)) then
      return '0';

--- a/hdl/seu_counters.vhd
+++ b/hdl/seu_counters.vhd
@@ -13,12 +13,8 @@ use work.wishbone_pkg.all;
 --use smartfusion2.all;
 use work.voter.all;
-use work.wb_voter_pkg.all;
 entity seu_counters is
  port (
    clk_i : in std_logic;
    rst_i : in std_logic;
@@ -34,16 +30,14 @@ entity seu_counters is
    se_iram_o : out std_logic_vector (15 downto 0);
    de_iram_o : out std_logic_vector (15 downto 0)
    );
 end entity seu_counters;
 architecture rtl of seu_counters is
  signal se_iram_counter,de_iram_counter,se_dram_counter,de_dram_counter : unsigned (15 downto 0);
-    attribute syn_radhardlevel : string;
+  attribute syn_radhardlevel : string;
-attribute syn_radhardlevel of rtl : architecture is "tmr";
+  attribute syn_radhardlevel of rtl : architecture is "tmr";
 begin

--- a/hdl/urv_core_DTMR.vhd
+++ b/hdl/urv_core_DTMR.vhd
@@ -187,12 +187,12 @@ end component;
  signal im_addr, dm_addr, dram_addr          : std_logic_vector(31 downto 0);
-  signal im_data, im_data_cpu, im_data_bank1, dram_data_in, dram_data_out : std_logic_vector(31 downto 0);
+  signal im_data, dram_data_in, dram_data_out : std_logic_vector(31 downto 0);
-  signal im_valid, im_valid_cpu, im_valid_bank1                             : std_logic;
+  signal im_valid                             : std_logic;
-  signal dm_data_s, dm_data_l, dm_data_ram, dm_wb_rdata         : std_logic_vector(31 downto 0);
+  signal dm_data_s, dm_data_l, dm_wb_rdata         : std_logic_vector(31 downto 0);
  signal dm_data_select, dram_bwe                               : std_logic_vector(3 downto 0);
-  signal dm_load, dm_store, dm_done, dm_ready, dram_we, dram_re : std_logic;
+  signal dm_load, dm_store, dram_we, dram_re : std_logic;
  signal dram_done_r, dram_done_w                               : std_logic;
  signal dm_is_wishbone, dm_cycle_in_progress, dm_load_done_wb, dm_store_done_wb : std_logic;
@@ -384,11 +384,11 @@ end generate;
        dram_addr <= (others => '0');
      else
        -- signals from uRV data interface to the data-ram are sampled to improve fmax
-      if (dram_done_r or dram_done_w) then
+        if (dram_done_r or dram_done_w) then
          dram_we <= '0';
          dram_re <= '0';
-      end if;
+        end if;
        if (dm_is_wishbone = '0' and (dm_load = '1' or dm_store = '1')) then
          dram_addr    <= dm_addr;
          dram_data_in <= dm_data_s;
@@ -420,7 +420,7 @@ end generate;
            dm_load_done_wb      <= '0';
            dm_cycle_in_progress <= '0';
          end if;
        else
          if(cpu_dwb_i.stall = '0') then
            cpu_dwb_o.stb <= '0';

--- a/hdl/urv_soc.vhd
+++ b/hdl/urv_soc.vhd
--- a/hdl/urv_supervisor.vhd
+++ b/hdl/urv_supervisor.vhd
@@ -13,7 +13,6 @@ use work.wishbone_pkg.all;
 --use smartfusion2.all;
 use work.voter.all;
-use work.wb_voter_pkg.all;
@@ -48,7 +47,6 @@ architecture rtl of urv_supervisor is
  signal state_cpu_1, state_cpu_2, state_cpu_3 : std_logic;
  signal state_cpu : std_logic_vector (3 downto 1);  
-    signal release_cpu : std_logic;
  type fsm_states is (boot, boot_cnt, voting, lock_step, fatal, fatal_2);
  constant recovery_dunc                 : std_logic_vector (15 downto 0) := x"0000";

--- a/hdl/wb_envm.vhd
+++ b/hdl/wb_envm.vhd
--- a/hdl/xwb_ram_adapter.vhdl
+++ b/hdl/xwb_ram_adapter.vhdl
--- a/hdl/xwb_seu_reg.vhd
+++ b/hdl/xwb_seu_reg.vhd
@@ -83,8 +83,7 @@ begin
  slave_o.err <= '0';
  slave_o.rty <= '0';
-  slave_o.int <='0';
  desc_o <= (others => '0');

--- a/hdl/xwb_uart.vhd
+++ b/hdl/xwb_uart.vhd
@@ -78,7 +78,6 @@ begin
  slave_o.err <= '0';
  slave_o.rty <= '0';
-  slave_o.int <='0';
  desc_o <= (others => '0');

--- a/hdl/xwb_wd_reg.vhd
+++ b/hdl/xwb_wd_reg.vhd
@@ -70,7 +70,6 @@ begin
  slave_o.err <= '0';
  slave_o.rty <= '0';
-  slave_o.int <='0';
  desc_o <= (others => '0');