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Hydra - a radiation-tolerant SoC
Commit ca8231b8 authored by Mattia Rizzi's avatar Mattia Rizzi
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Files required by Libero for the MSS

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component/work/hydra/drcss.xsl 0 → 100644
View file @ ca8231b8
<?xml version="1.0" encoding="iso-8859-1" ?>
<xsl:stylesheet version="1.0" xmlns:xsl="http://www.w3.org/1999/XSL/Transform">
<xsl:template match="/">
<head>
<xsl:call-template name="css"/>
</head>
<body>
<p>
<div class="header">DRC Report: <xsl:value-of select="drcreport/header" /></div>
</p>
<table class="drctable" align="left" border="1" width="75%" cellspacing="0" cellpadding="4">
<tr>
<th>Status</th>
<th>Message</th>
<th>Details</th>
</tr>
<xsl:for-each select="drcreport/drc">
<tr>
<td style="padding-left:20px"> <img width="16" height="16">
<xsl:attribute name="src"> <xsl:value-of select="status"/> </xsl:attribute>
<xsl:attribute name="alt"> <xsl:value-of select="StatusMessage"/> </xsl:attribute>
<xsl:attribute name="title"> <xsl:value-of select="StatusMessage"/> </xsl:attribute>
</img>
</td>
<td> <a> <xsl:attribute name="href"> <xsl:value-of select="crossprobe"/> </xsl:attribute> <xsl:value-of select="message" /></a></td>
<td> <xsl:value-of select="detail" /></td>
</tr>
</xsl:for-each>
</table>
</body>
</xsl:template>
<xsl:template name="css">
<style>
body
{
font-family:arial;
font-size: 11pt;
text-align:center;
}
div.header
{
padding-top: 7px;
padding-bottom: 7px;
color:#003399;
background-color: #D0D0D0;
width=100%;
font-family:arial;
font-size:14pt;
font-weight: bold;
text-align: center;
}
table.drctable
{
border-color: #B0B0B0;
border-style:solid;
border-width:1px;
border-spacing:0px;
border-collapse:collapse;
width=75%;
font-family:couriernew;
font-size: 11pt;
}
table.drctable th
{
background-color: #F0F0F0;
border-color: #B0B0B0;
border-width:1px;
color: darkslategray;
font-weight:bold;
}
table.drctable td
{
text-align:left;
}
</style>
<!--============================= END CSS ===================================-->
</xsl:template>
</xsl:stylesheet>
component/work/hydra/hydra.cxf 0 → 100644
View file @ ca8231b8
<?xml version="1.0" encoding="UTF-8" standalone="no" ?><Component xmlns="http://actel.com/sweng/afi"><name>hydra</name><vendor/><library/><version/><fileSets><fileSet fileSetId="OTHER_FILESET"><file fileid="0"><name>./hydra.sdb</name><userFileType>SDB</userFileType></file><file fileid="1"><name>./hydra_DRC.xml</name><userFileType>log</userFileType></file><file fileid="2"><name>./hydra_manifest.txt</name><userFileType>LOG</userFileType></file></fileSet><fileSet fileSetId="ANY_SIMULATION_FILESET"><file fileid="3"><name>./subsystem.bfm</name><userFileType>unknown</userFileType></file></fileSet><fileSet fileSetId="HDL_FILESET"><file fileid="4"><name>./hydra.v</name><fileType>verilogSource</fileType></file></fileSet></fileSets><hwModel><views><view><fileSetRef>OTHER_FILESET</fileSetRef><name>OTHER</name></view><view><fileSetRef>ANY_SIMULATION_FILESET</fileSetRef><name>SIMULATION</name></view><view><fileSetRef>HDL_FILESET</fileSetRef><name>HDL</name></view></views></hwModel><category>SmartCoreDesign</category><function>SmartDesign</function><variation>SmartDesign</variation><vendor>Actel</vendor><version>1.0</version><vendorExtension><type>SmartCoreDesign</type></vendorExtension><vendorExtension><state value="GENERATED"/></vendorExtension><vendorExtensions><previousType/><preDesignInGoodState>false</preDesignInGoodState><componentRef library="" name="" vendor="" version=""/><dependentModules><module file="hdl\clock_buffer.vhd" module_class="HdlModule" name="clock_buffer" state="GOOD" type="2"/><module module_class="ComponentModule" name="hydra_MSS::work" state="GOOD" type="1"/><module file="hdl\reset_gen.vhd" module_class="HdlModule" name="reset_gen" state="GOOD" type="2"/><module file="hdl\urv_soc.vhd" id_library="Private" id_name="urv_soc" id_vendor="User" id_version="1.0" module_class="HDLSpiritModule" name="urv_soc" state="GOOD" type="4"/></dependentModules></vendorExtensions><model><signals><signal><name>DEVRST_N</name><direction>in</direction><export>true</export><vendorExtensions><pad>true</pad><padMacro>SYSRESET</padMacro><padMacroPin>DEVRST_N</padMacroPin><used>true</used></vendorExtensions></signal><signal><name>CLK_I</name><direction>in</direction><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>ETH_TX_CLK_I</name><direction>in</direction><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>ETH_TXERR_O</name><direction>out</direction><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>ETH_RX_CLK_I</name><direction>in</direction><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>ETH_RX_DV_I</name><direction>in</direction><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>ETH_MDIO</name><direction>inout</direction><export>true</export><vendorExtensions><pad>true</pad><padMacro>BIBUF</padMacro><padMacroPin>PAD</padMacroPin><used>true</used></vendorExtensions></signal><signal><name>ETH_RXERR_I</name><direction>in</direction><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>ETH_TX_EN_O</name><direction>out</direction><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>ETH_MDC_O</name><direction>out</direction><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>uart_tx_o</name><direction>out</direction><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>RST_I</name><direction>in</direction><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>GPIO_LED1</name><direction>out</direction><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>GPIO_LED2</name><direction>out</direction><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>ETH_RXD_I</name><direction>in</direction><left>3</left><right>0</right><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>ETH_TXD_O</name><direction>out</direction><left>3</left><right>0</right><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal></signals></model></Component>
\ No newline at end of file
component/work/hydra/subsystem.bfm 0 → 100644
View file @ ca8231b8
#===========================================================
# Created by Microsemi SmartDesign Tue Dec 08 14:54:39 2020
#
# Syntax:
# -------
#
# memmap resource_name base_address;
#
# write width resource_name byte_offset data;
# read width resource_name byte_offset;
# readcheck width resource_name byte_offset data;
#
#===========================================================
#-----------------------------------------------------------
# Memory Map
# Define name and base address of each resource.
#-----------------------------------------------------------
component/work/hydra_MSS/CM3_compile_bfm.tcl 0 → 100644
View file @ ca8231b8
# ===========================================================
# Created by Microsemi SmartDesign Tue Dec 08 11:16:49 2020
#
# Warning: Do not modify this file, it may lead to unexpected
# simulation failures in your design.
#
# ===========================================================
if {$tcl_platform(os) == "Linux"} {
exec "$env(ACTEL_SW_DIR)/bin/bfmtovec" -in test.bfm -out test.vec
} else {
exec "$env(ACTEL_SW_DIR)/bin/bfmtovec.exe" -in test.bfm -out test.vec
}
component/work/hydra_MSS/ENVM.cfg 0 → 100644
View file @ ca8231b8
nvm_set_data_storage_client \
-client_name {bootldr} \
-number_of_words 848 \
-word_size 8 \
-use_for_simulation {0} \
-content_type {MEMORY_FILE} \
-memory_file_format {INTELHEX} \
-memory_file {G:/Users/r/rizzi/powerlink/pl-hw-urv/SoftConsole/g4m_system_MSS_CM3_app/bootloader.hex} \
-base_address 73728 \
-reprogram 1 \
-use_as_rom 0 \
-lock_address 0
nvm_set_data_storage_client \
-client_name {app_text} \
-number_of_words 63656 \
-word_size 8 \
-use_for_simulation {0} \
-content_type {MEMORY_FILE} \
-memory_file_format {INTELHEX} \
-memory_file {G:/Users/r/rizzi/powerlink/pl-hw-urv/SoftConsole/g4m_system_MSS_CM3_app/main-text.hex} \
-base_address 0 \
-reprogram 1 \
-use_as_rom 0 \
-lock_address 0
nvm_set_data_storage_client \
-client_name {app_data} \
-number_of_words 26700 \
-word_size 8 \
-use_for_simulation {0} \
-content_type {MEMORY_FILE} \
-memory_file_format {INTELHEX} \
-memory_file {G:/Users/r/rizzi/powerlink/pl-hw-urv/SoftConsole/g4m_system_MSS_CM3_app/main-data.hex} \
-base_address 131072 \
-reprogram 1 \
-use_as_rom 0 \
-lock_address 0
component/work/hydra_MSS/drcss.xsl 0 → 100644
View file @ ca8231b8
<?xml version="1.0" encoding="iso-8859-1" ?>
<xsl:stylesheet version="1.0" xmlns:xsl="http://www.w3.org/1999/XSL/Transform">
<xsl:template match="/">
<head>
<xsl:call-template name="css"/>
</head>
<body>
<p>
<div class="header">DRC Report: <xsl:value-of select="drcreport/header" /></div>
</p>
<table class="drctable" align="left" border="1" width="75%" cellspacing="0" cellpadding="4">
<tr>
<th>Status</th>
<th>Message</th>
<th>Details</th>
</tr>
<xsl:for-each select="drcreport/drc">
<tr>
<td style="padding-left:20px"> <img width="16" height="16">
<xsl:attribute name="src"> <xsl:value-of select="status"/> </xsl:attribute>
<xsl:attribute name="alt"> <xsl:value-of select="StatusMessage"/> </xsl:attribute>
<xsl:attribute name="title"> <xsl:value-of select="StatusMessage"/> </xsl:attribute>
</img>
</td>
<td> <a> <xsl:attribute name="href"> <xsl:value-of select="crossprobe"/> </xsl:attribute> <xsl:value-of select="message" /></a></td>
<td> <xsl:value-of select="detail" /></td>
</tr>
</xsl:for-each>
</table>
</body>
</xsl:template>
<xsl:template name="css">
<style>
body
{
font-family:arial;
font-size: 11pt;
text-align:center;
}
div.header
{
padding-top: 7px;
padding-bottom: 7px;
color:#003399;
background-color: #D0D0D0;
width=100%;
font-family:arial;
font-size:14pt;
font-weight: bold;
text-align: center;
}
table.drctable
{
border-color: #B0B0B0;
border-style:solid;
border-width:1px;
border-spacing:0px;
border-collapse:collapse;
width=75%;
font-family:couriernew;
font-size: 11pt;
}
table.drctable th
{
background-color: #F0F0F0;
border-color: #B0B0B0;
border-width:1px;
color: darkslategray;
font-weight:bold;
}
table.drctable td
{
text-align:left;
}
</style>
<!--============================= END CSS ===================================-->
</xsl:template>
</xsl:stylesheet>
component/work/hydra_MSS/hydra_MSS.cxf 0 → 100644
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component/work/hydra_MSS/hydra_MSS.v 0 → 100644
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component/work/hydra_MSS/hydra_MSS_DRC.xml 0 → 100644
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<?xml version="1.0" encoding="ISO-8859-1" ?>
<?xml-stylesheet type="text/xsl" href="drcss.xsl"?>
<drcreport>
<header>hydra_MSS_tmp</header>
</drcreport>
component/work/hydra_MSS/hydra_MSS_manifest.txt 0 → 100644
View file @ ca8231b8
Microsemi Corporation - Microsemi Libero Software Release v11.8 (Version 11.8.0.26)
Date : Tue Dec 08 11:16:51 2020
Project : C:\Users\mattia\Desktop\urv-core-rad\final-design\hydra
Component : hydra_MSS
Family : SmartFusion2
HDL source files for all Synthesis and Simulation tools:
C:/Users/mattia/Desktop/urv-core-rad/final-design/hydra/component/work/hydra_MSS/hydra_MSS.v
HDL source files for Synopsys SynplifyPro Synthesis tool:
C:/Users/mattia/Desktop/urv-core-rad/final-design/hydra/component/work/hydra_MSS/hydra_MSS_syn.v
HDL source files for Mentor Precision Synthesis tool:
C:/Users/mattia/Desktop/urv-core-rad/final-design/hydra/component/work/hydra_MSS/hydra_MSS_pre.v
C:/Users/mattia/Desktop/urv-core-rad/final-design/hydra/component/work/hydra_MSS/hydra_MSS_pre.vhd
Stimulus files for all Simulation tools:
C:/Users/mattia/Desktop/urv-core-rad/final-design/hydra/component/Actel/SmartFusion2MSS/MSS/1.1.500/peripheral_init.bfm
C:/Users/mattia/Desktop/urv-core-rad/final-design/hydra/component/work/hydra_MSS/CM3_compile_bfm.tcl
C:/Users/mattia/Desktop/urv-core-rad/final-design/hydra/component/work/hydra_MSS/test.bfm
C:/Users/mattia/Desktop/urv-core-rad/final-design/hydra/component/work/hydra_MSS/user.bfm
Firmware files for all Software IDE tools:
C:/Users/mattia/Desktop/urv-core-rad/final-design/hydra/component/work/hydra_MSS/sys_config_mss_clocks.h
Configuration files to be used for Programming:
C:/Users/mattia/Desktop/urv-core-rad/final-design/hydra/component/work/hydra_MSS/ENVM.cfg
Configuration files to be used for all Simulation tools:
C:/Users/mattia/Desktop/urv-core-rad/final-design/hydra/component/work/hydra_MSS/ENVM.cfg
component/work/hydra_MSS/hydra_MSS_pre.v 0 → 100644
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This diff is collapsed.
component/work/hydra_MSS/hydra_MSS_pre.vhd 0 → 100644
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This diff is collapsed.
component/work/hydra_MSS/hydra_MSS_syn.v 0 → 100644
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component/work/hydra_MSS/sys_config_mss_clocks.h 0 → 100644
View file @ ca8231b8
/*=============================================================*/
/* Created by Microsemi SmartDesign Tue Dec 08 11:16:49 2020 */
/* */
/* Warning: Do not modify this file, it may lead to unexpected */
/* functional failures in your design. */
/* */
/*=============================================================*/
#ifndef SYS_CONFIG_MSS_CLOCKS
#define SYS_CONFIG_MSS_CLOCKS
#define MSS_SYS_M3_CLK_FREQ 100000000u
#define MSS_SYS_MDDR_CLK_FREQ 100000000u
#define MSS_SYS_APB_0_CLK_FREQ 50000000u
#define MSS_SYS_APB_1_CLK_FREQ 50000000u
#define MSS_SYS_APB_2_CLK_FREQ 25000000u
#define MSS_SYS_FIC_0_CLK_FREQ 100000000u
#define MSS_SYS_FIC_1_CLK_FREQ 100000000u
#define MSS_SYS_FIC64_CLK_FREQ 100000000u
#endif /* SYS_CONFIG_MSS_CLOCKS */
component/work/hydra_MSS/test.bfm 0 → 100644
View file @ ca8231b8
#===========================================================
# Created by Microsemi SmartDesign Tue Dec 08 11:16:49 2020
#
#
# Warning: Do not modify this file, it may lead to unexpected
# simulation failures in your Microcontroller Subsystem.
# Add your BFM commands to user.bfm
#
#
#===========================================================
#-----------------------------------------------------------
# Include User BFM
#-----------------------------------------------------------
include "user.bfm"
#-----------------------------------------------------------
# Main Function
#-----------------------------------------------------------
procedure main;
call user_main;
return
component/work/hydra_MSS/user.bfm 0 → 100644
View file @ ca8231b8
#===========================================================
# Enter your BFM commands in this file.
#
# Syntax:
# -------
#
# memmap resource_name base_address;
#
# write width resource_name byte_offset data;
# read width resource_name byte_offset;
# readcheck width resource_name byte_offset data;
#
#===========================================================
include "subsystem.bfm"
procedure user_main;
# perform subsystem initialization routine
call subsystem_init;
# add your BFM commands below:
return
\ No newline at end of file
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