Commit ad9f1ea9 authored by Mattia Rizzi's avatar Mattia Rizzi

Added local tmr and onehot encode.

this entity has never been tested in radiation
parent 16f27509
...@@ -53,6 +53,12 @@ signal envm_read_req_p, apb_read_req, apb_read_req_boot, apb_read_req_wb, apb_re ...@@ -53,6 +53,12 @@ signal envm_read_req_p, apb_read_req, apb_read_req_boot, apb_read_req_wb, apb_re
signal wb_write_req, wb_write_req_boot, wb_write_req_wb, wb_write_ack : std_logic; signal wb_write_req, wb_write_req_boot, wb_write_req_wb, wb_write_ack : std_logic;
signal wb_addr, wb_addr_boot, wb_addr_wb : std_logic_vector (16 downto 0); signal wb_addr, wb_addr_boot, wb_addr_wb : std_logic_vector (16 downto 0);
signal counter : unsigned (9 downto 0); signal counter : unsigned (9 downto 0);
attribute syn_encoding : string;
attribute syn_encoding of bootstrap_fsm, wb_fsm, apb_fsm, envm_fsm : signal is "safe,onehot";
attribute syn_radhardlevel : string;
attribute syn_radhardlevel of rtl : architecture is "tmr";
begin begin
apb_addr <= apb_addr_boot when (rst_cpu_o = '1') else apb_addr_wb; apb_addr <= apb_addr_boot when (rst_cpu_o = '1') else apb_addr_wb;
...@@ -176,7 +182,7 @@ if rising_edge(clk_i) then ...@@ -176,7 +182,7 @@ if rising_edge(clk_i) then
else else
case (apb_fsm) is case (apb_fsm) is
when idle => when idle =>
apb_read_ack <= '0'; apb_read_ack <= '0';
if (apb_read_req = '1' and apb_read_ack = '0') then if (apb_read_req = '1' and apb_read_ack = '0') then
apb_fsm <= setup; apb_fsm <= setup;
apb_psel_o <= '1'; apb_psel_o <= '1';
...@@ -283,4 +289,4 @@ end process; ...@@ -283,4 +289,4 @@ end process;
end architecture; end architecture;
\ No newline at end of file
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