Initial commit

hdl/rtl/Manifest.py

+files = ['hydra_core.vhd']

hdl/rtl/hydra_core.vhd

+--------------------------------------------------------------------------------
+-- CERN BE-CO-HT
+-- Mock Turtle
+-- https://gitlab.cern.ch/coht/mockturtle
+--------------------------------------------------------------------------------
+--
+-- unit name:   mt_urv_wrapper
+--
+-- description: A small wrapper for the URV encompassing the internal RAM and
+-- access to the RAM through CPU CSR register block.
+--
+--------------------------------------------------------------------------------
+-- Copyright CERN 2014-2018
+--------------------------------------------------------------------------------
+-- Copyright and related rights are licensed under the Solderpad Hardware
+-- License, Version 2.0 (the "License"); you may not use this file except
+-- in compliance with the License. You may obtain a copy of the License at
+-- http://solderpad.org/licenses/SHL-2.0.
+-- Unless required by applicable law or agreed to in writing, software,
+-- hardware and materials distributed under this License is distributed on an
+-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
+-- or implied. See the License for the specific language governing permissions
+-- and limitations under the License.
+--------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.genram_pkg.all;
+--use work.memory_loader_pkg.all;
+use work.wishbone_pkg.all;
+use work.urv_pkg.all;
+
+entity fip_urv is
+  generic(
+    g_IRAM_LOG_SIZE : natural := 12;
+    g_DRAM_LOG_SIZE : natural := 12);
+  port(
+    clk_sys_i : in  std_logic;
+    rst_n_i   : in  std_logic;
+    restart_i : in  std_logic;
+    dwb_o     : out t_wishbone_master_out;
+    dwb_i     : in  t_wishbone_master_in;
+
+    fic0_ready_i   : in  std_logic;
+    fic0_clk_i     : in  std_logic;
+
+    fic0_haddr_o     : out std_logic_vector(31 downto 0);
+    fic0_hburst_o    : out std_logic_vector(2 downto 0);
+    fic0_hmastlock_o : out std_logic;
+    fic0_hprot_o     : out std_logic_vector(3 downto 0);
+    fic0_hsize_o     : out std_logic_vector(2 downto 0);
+    fic0_htrans_o    : out std_logic_vector(1 downto 0);
+    fic0_hwdata_o    : out std_logic_vector(31 downto 0);
+    fic0_hwrite_o    : out std_logic;
+    fic0_hrdata_i    : in  std_logic_vector(31 downto 0);
+    fic0_hready_i    : in  std_logic;
+    fic0_hresp_i     : in  std_logic_vector(1 downto 0);
+
+    led_en_o     : out std_logic;
+    leds_o       : out std_logic_vector(4 downto 1)
+  );
+end fip_urv;
+
+architecture arch of fip_urv is
+
+  impure function f_x_to_zero (x : std_logic_vector) return std_logic_vector
+  is
+    variable tmp : std_logic_vector(x'length-1 downto 0);
+    variable found_undef : boolean := false;
+  begin
+-- synthesis translate_off
+    for i in 0 to x'length-1 loop
+      if( x(i) = 'U' or x(i) = 'Z' or x(i) = 'X' ) then
+        found_undef := true;
+      end if;
+
+      if x(i) = '1' or x(i) = 'H' then
+        tmp(i) := '1';
+      else
+        tmp(i) := '0';
+      end if;
+    end loop;
+    return tmp;
+
+    if found_undef then
+      report "Undefined data value read from memory" severity warning;
+    end if;
+
+-- synthesis translate_on
+    return x;
+  end function f_x_to_zero;
+
+  signal cpu_rst        : std_logic;
+  signal cpu_rst_d      : std_logic;
+
+  signal im_addr,  im_waddr : std_logic_vector(31 downto 0);
+  signal im_data,  im_wdata : std_logic_vector(31 downto 0);
+  signal im_valid, im_write : std_logic;
+
+  signal dm_addr, dm_data_s, dm_data_l                            : std_logic_vector(31 downto 0);
+  signal dm_data_select                                           : std_logic_vector(3 downto 0);
+  signal dm_load, dm_store, dm_load_done, dm_store_done : std_logic;
+
+  signal reg_dm_addr, reg_dm_data_s : std_logic_vector(31 downto 0);
+  signal reg_dm_data_select         : std_logic_vector(3 downto 0);
+  signal reg_dm_load, reg_dm_store  : std_logic;
+
+  signal dm_cycle_in_progress, reg_dm_is_wishbone : std_logic;
+
+  signal dm_mem_rdata, dm_wb_rdata : std_logic_vector(31 downto 0);
+  signal dm_wb_write, dm_select_wb : std_logic;
+  signal reg_dm_data_write             : std_logic;
+
+  signal dwb_out         : t_wishbone_master_out;
+begin
+
+  dwb_o <= dwb_out;
+
+  U_cpu_core : urv_cpu
+    generic map (
+      g_timer_frequency => 0,
+      g_with_hw_debug => 0,
+      g_with_hw_mul => 0,
+      g_with_hw_div => 0
+    )
+    port map (
+      clk_i            => clk_sys_i,
+      rst_i            => cpu_rst,
+      irq_i            => '0',
+      im_addr_o        => im_addr,
+      im_data_i        => im_data,
+      im_valid_i       => im_valid,
+      dm_addr_o        => dm_addr,
+      dm_data_s_o      => dm_data_s,
+      dm_data_l_i      => dm_data_l,
+      dm_data_select_o => dm_data_select,
+      dm_store_o       => dm_store,
+      dm_load_o        => dm_load,
+      dm_load_done_i   => dm_load_done,
+      dm_store_done_i  => dm_store_done,
+      dbg_force_i      => '0',
+      dbg_enabled_o    => open,
+      dbg_insn_i       => x"0000_0000",
+      dbg_insn_set_i   => '0',
+      dbg_insn_ready_o => open,
+      dbg_mbx_data_i   => x"0000_0000",
+      dbg_mbx_write_i  => '0',
+      dbg_mbx_data_o   => open);
+
+  process (clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' then
+        reg_dm_load <= '0';
+        reg_dm_store <= '0';
+      else
+        reg_dm_load <= dm_load;
+        reg_dm_store <= dm_store;
+        reg_dm_addr <= dm_addr;
+        reg_dm_data_s <= dm_data_s;
+        reg_dm_data_select <= dm_data_select;
+      end if;
+    end if;
+  end process;
+
+  p_rom: process (clk_sys_i)
+  is
+    constant IRAM_WSIZE : natural := 2 ** (g_IRAM_LOG_SIZE - 2);
+    variable iram : t_ram32_type(0 to IRAM_WSIZE - 1);
+--     := f_load_mem32_from_file ("../../../sw/fip_urv/fip_dbg.ram", IRAM_WSIZE, True);
+  begin
+    if rising_edge(clk_sys_i) then
+      if cpu_rst = '1' then
+        if im_write = '1' then
+          iram (to_integer(unsigned(im_waddr(g_IRAM_LOG_SIZE - 1 downto 2)))) := im_wdata;
+        end if;
+      else
+        im_data <= iram (to_integer(unsigned(im_addr(g_IRAM_LOG_SIZE - 1 downto 2))));
+      end if;
+    end if;
+  end process;
+
+  -- 1st MByte of the mem is the RAM
+  reg_dm_is_wishbone <= '1' when reg_dm_addr(31 downto 20) /= x"000" else '0';
+
+  reg_dm_data_write <= not reg_dm_is_wishbone and reg_dm_store;
+  dm_data_l     <= dm_wb_rdata when dm_select_wb = '1' else dm_mem_rdata;
+
+  p_ram: process (clk_sys_i)
+  is
+    variable dram : t_ram32_type (2**(g_DRAM_LOG_SIZE - 2) - 1 downto 0);
+    variable addr : natural range dram'range;
+  begin
+    if rising_edge(clk_sys_i) then
+      addr := to_integer(unsigned(reg_dm_addr(g_DRAM_LOG_SIZE - 1 downto 2)));
+      dm_mem_rdata <= dram(addr);
+      if reg_dm_data_write = '1' then
+        for i in 0 to 3 loop
+          if reg_dm_data_select (i) = '1' then
+            dram(addr)(8*i + 7 downto 8*i) := reg_dm_data_s(8*i + 7 downto 8*i);
+          end if;
+        end loop;
+      end if;
+    end if;
+  end process;
+
+  -- Wishbone bus arbitration / internal RAM access
+  p_wishbone_master : process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' then
+        dwb_out.cyc          <= '0';
+        dwb_out.stb          <= '0';
+        dwb_out.adr          <= (others => '0');
+        dwb_out.sel          <= x"0";
+        dwb_out.we           <= '0';
+        dwb_out.dat          <= (others => '0');
+        dm_cycle_in_progress <= '0';
+        dm_load_done         <= '0';
+        dm_store_done        <= '0';
+        dm_select_wb         <= '0';
+      else
+
+        if dm_cycle_in_progress = '0' then
+          if reg_dm_is_wishbone = '0' then
+            --  Internal access
+            if reg_dm_store = '1' then
+              dm_load_done  <= '0';
+              dm_store_done <= '1';
+              dm_select_wb  <= '0';
+            elsif reg_dm_load = '1' then
+              dm_load_done  <= '1';
+              dm_store_done <= '0';
+              dm_select_wb  <= '0';
+            else
+              dm_store_done <= '0';
+              dm_load_done  <= '0';
+              dm_select_wb  <= '0';
+            end if;
+          else
+            --  Wishbone access
+            if reg_dm_load = '1' or reg_dm_store = '1' then
+              dwb_out.cyc          <= '1';
+              dwb_out.stb          <= '1';
+              dwb_out.we           <= reg_dm_store;
+              dm_wb_write          <= reg_dm_store;
+              dwb_out.adr          <= reg_dm_addr;
+              dwb_out.dat          <= reg_dm_data_s;
+              dwb_out.sel          <= reg_dm_data_select;
+              dm_load_done         <= '0';
+              dm_store_done        <= '0';
+              dm_cycle_in_progress <= '1';
+            else
+              dm_store_done        <= '0';
+              dm_load_done         <= '0';
+              dm_cycle_in_progress <= '0';
+            end if;
+          end if;
+        else
+          --  Wishbone transfer in progress.
+          if dwb_i.stall = '0' then
+            dwb_out.stb <= '0';
+          end if;
+
+          if dwb_i.ack = '1' then
+            if dm_wb_write = '0' then
+              dm_wb_rdata  <= f_x_to_zero(dwb_i.dat);
+              dm_select_wb <= '1';
+              dm_load_done <= '1';
+            else
+              dm_store_done <= '1';
+              dm_select_wb  <= '0';
+            end if;
+
+            dm_cycle_in_progress <= '0';
+            dwb_out.cyc          <= '0';
+          end if;
+        end if;
+      end if;
+    end if;
+  end process p_wishbone_master;
+
+  p_im_valid : process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if cpu_rst = '1' then
+        im_valid  <= '0';
+        cpu_rst_d <= '1';
+      else
+        cpu_rst_d <= cpu_rst;
+        im_valid  <= (not cpu_rst_d);
+      end if;
+    end if;
+  end process p_im_valid;
+
+  b_init: block
+    type t_main_state is (init, envm_ready, envm_ready2, read_word, wait_word, done);
+    signal main_state : t_main_state;
+
+    type t_ahb_state is (idle, addr_phase, wait_rsp, wait_idle);
+    signal ahb_state : t_ahb_state;
+    signal htrans : std_logic_vector(1 downto 0);
+    signal haddr : std_logic_vector(31 downto 0);
+
+    signal hpms_start, hpms_done : std_logic;
+    signal fic_start, fic_done : std_logic;
+    signal hpms_data : std_logic_vector (31 downto 0);
+
+    signal envm_addr : std_logic_vector (31 downto 0);
+    signal envm_len : unsigned (31 downto 0);
+
+    signal dest_addr : std_logic_vector (31 downto 0);
+
+    signal leds : std_logic_vector(1 downto 0);
+  begin
+    fic0_hburst_o <= "000";
+    fic0_hmastlock_o <= '0';
+    fic0_hprot_o <= "0011";
+    fic0_hsize_o <= "010";
+    fic0_htrans_o <= htrans;
+    fic0_haddr_o <= haddr;
+
+    leds_o(2 downto 1) <= "11";
+    leds_o(4 downto 3) <= leds;
+
+    -- Main FSM: copy eNVM to IRAM
+    process (clk_sys_i)
+    begin
+      if rising_edge (clk_sys_i) then
+        hpms_start <= '0';
+        im_write <= '0';
+        cpu_rst <= '1';
+        led_en_o <= '1';
+        fic0_hwrite_o <= '0';
+
+        if rst_n_i = '0' then
+          main_state <= init;
+          leds <= "11";
+        else
+          case main_state is
+            when init =>
+              leds <= "11";
+              if fic0_ready_i = '1' then
+                -- poll eNVM ready bit from status register
+                haddr <= x"6008_0120";
+                fic0_hwrite_o <= '0';
+                hpms_start <= '1';
+
+                main_state <= envm_ready;
+              end if;
+
+--             main_state <= done;
+
+            when envm_ready =>
+              leds <= "10";
+              hpms_start <= '1';
+              if hpms_done = '1' then
+                hpms_start <= '0';
+                main_state <= envm_ready2;
+              end if;
+
+            when envm_ready2 =>
+              if hpms_done = '0' then
+                if hpms_data (0) = '1' then
+                  --  eNVM is ready.
+                  main_state <= read_word;
+
+                  --  Copy the whole IRAM
+                  envm_addr <= x"6000_0000";
+                  envm_len <= to_unsigned(2**g_IRAM_LOG_SIZE, 32);
+                  dest_addr <= x"0000_0000";
+                else
+                  --  eNVM not ready
+                  --  poll again.
+                  hpms_start <= '1';
+                  main_state <= envm_ready;
+                end if;
+              end if;
+
+            when read_word =>
+              leds <= "00";
+              if hpms_done = '0' then
+                haddr <= envm_addr;
+                hpms_start <= '1';
+
+                envm_addr <= std_logic_vector(unsigned(envm_addr) + 4);
+                envm_len <= envm_len - 4;
+
+                main_state <= wait_word;
+              end if;
+
+            when wait_word =>
+              leds <= "00";
+              hpms_start <= '1';
+              if hpms_done = '1' then
+                --  Write the word.
+                im_wdata <= hpms_data;
+                im_write <= '1';
+                im_waddr <= dest_addr;
+
+                dest_addr <= std_logic_vector(unsigned(dest_addr) + 4);
+
+                if envm_len = 0 then
+                  main_state <= done;
+                else
+                  main_state <= read_word;
+                end if;
+              end if;
+          
+            when done =>
+              led_en_o <= '0';
+              leds <= "00";
+              cpu_rst <= '0';
+
+              if restart_i = '1' then
+                cpu_rst <= '1';
+                main_state <= init;
+              end if;
+          end case;
+        end if;
+      end if;
+    end process;
+
+    inst_sync_start: entity work.gc_sync
+      port map (
+        clk_i => fic0_clk_i,
+        rst_n_a_i => rst_n_i,
+        d_i => hpms_start,
+        q_o => fic_start
+      );
+    inst_sync_done: entity work.gc_sync
+      port map (
+        clk_i => clk_sys_i,
+        rst_n_a_i => rst_n_i,
+        d_i => fic_done,
+        q_o => hpms_done
+      );
+
+    --  AHB FSM (in FIC clock domain)
+    process (fic0_clk_i)
+    begin
+      if rising_edge (fic0_clk_i) then
+        htrans <= "00";
+        fic_done <= '0';
+
+        if rst_n_i = '0' then
+          ahb_state <= idle;
+        else
+          case ahb_state is
+            when idle =>
+              if fic_start = '1' then
+                htrans <= "10";  --  Non seq
+                ahb_state <= addr_phase;
+              end if;
+            when addr_phase =>
+              if fic0_hready_i = '1' then
+                ahb_state <= wait_rsp;
+              else
+                --  Was not ready.
+                htrans <= "10";  --  Non seq
+              end if;
+            when wait_rsp =>
+              if fic0_hready_i = '1' then
+                ahb_state <= wait_idle;
+                fic_done <= '1';
+                hpms_data <= fic0_hrdata_i;
+              end if;
+            when wait_idle =>
+              if fic_start = '0' then
+                fic_done <= '0';
+                ahb_state <= idle;
+              else
+                fic_done <= '1';
+              end if;
+          end case;
+        end if;
+      end if;
+    end process;
+  end block;
+end arch;

hdl/syn/sf2-test/Manifest.py

+action = "synthesis"
+target="libero"
+
+syn_family = "SmartFusion2"
+syn_device = "M2S050"
+syn_grade = "STD"
+syn_package = "FG484"  # 484 FBGA
+syn_project = "sf2_test"
+
+
+top_module = "sf2_test"
+syn_tool = "liberosoc"
+
+# files = ['diot_wic_demo.pdc', 'diot_wic_demo.sdc']
+files = ['osc_comps.vhd', 'io.pdc',
+         'syn_clocks.sdc'] # , 'clocks.pdc']
+
+modules = { "local" : [ "../../top/sf2-test"] }

hdl/syn/sf2-test/exported.tcl

+# Microsemi Tcl Script
+# libero
+# Date: Fri Nov 26 11:17:26 2021
+# Directory /home/tgingold/Repositories/ohwr/diot-radtol-base/hdl/syn/sf2-test
+# File /home/tgingold/Repositories/ohwr/diot-radtol-base/hdl/syn/sf2-test/exported.tcl
+
+
+open_project -file {./sf2_test/sf2_test.prjx} -do_backup_on_convert 1 -backup_file {./sf2_test.zip} 
+run_tool -name {CONSTRAINT_MANAGEMENT} 
+organize_tool_files -tool {PLACEROUTE} -file {./io.pdc} -module {sf2_test::work} -input_type {constraint} 
+organize_tool_files -tool {VERIFYTIMING} -file {} -module {sf2_test::work} -input_type {constraint} 
+create_links \
+         -convert_EDN_to_HDL 0 \
+         -sdc {./pnr_clocks.sdc} 
+organize_tool_files -tool {PLACEROUTE} -file {./io.pdc} -file {./pnr_clocks.sdc} -module {sf2_test::work} -input_type {constraint} 
+organize_tool_files -tool {VERIFYTIMING} -file {./pnr_clocks.sdc} -module {sf2_test::work} -input_type {constraint} 
+unlink_files -file {./clocks.sdc} 
+create_links \
+         -convert_EDN_to_HDL 0 \
+         -sdc {./syn_clocks.sdc} 
+organize_tool_files -tool {SYNTHESIZE} -file {./syn_clocks.sdc} -module {sf2_test::work} -input_type {constraint} 
+delete_files -file {./sf2_test/synthesis/sf2_test.vm} -from_disk 
+clean_tool -name {SYNTHESIZE} 
+run_tool -name {SYNTHESIZE} 
+run_tool -name {PLACEROUTE} 

hdl/syn/sf2-test/io.pdc

+# Generated by Microsemi Libero SoC
+# I/O physical design constraints file created from top ports of root module
+
+# Version: v2021.2 2021.2.0.11
+# Family: SmartFusion2 Die: M2S050 Package: 484 FBGA
+# Date generated: Mon Nov 15 10:11:36 2021
+
+# 
+# I/O constraints
+# 
+
+set_io led1_o       \
+    -pinname AB18      \
+    -fixed yes         \
+    -iostd LVCMOS25    \
+    -DIRECTION OUTPUT
+
+
+set_io led2_o       \
+    -pinname P1        \
+    -fixed yes         \
+    -iostd LVCMOS25    \
+    -DIRECTION OUTPUT
+
+    
+set_io but_i          \
+    -pinname U19      \
+    -fixed yes        \
+    -RES_PULL Up      \
+    -DIRECTION INPUT

hdl/syn/sf2-test/osc_comps.vhd

+library ieee;
+use ieee.std_logic_1164.all;
+
+entity RCOSC_1MHZ is
+  port(
+         CLKOUT : out   STD_ULOGIC
+  );
+end RCOSC_1MHZ;
+
+architecture DEF_ARCH of RCOSC_1MHZ is 
+    attribute syn_black_box : boolean;
+    attribute syn_black_box of DEF_ARCH : architecture is true;
+begin
+end DEF_ARCH; 
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity RCOSC_25_50MHZ is
+
+  generic(
+    FREQUENCY:real := 20.0
+  );
+
+  port(
+    CLKOUT : out   STD_ULOGIC
+  );
+end RCOSC_25_50MHZ;
+
+architecture DEF_ARCH of RCOSC_25_50MHZ is 
+    attribute syn_black_box : boolean;
+    attribute syn_black_box of DEF_ARCH : architecture is true;
+begin
+end DEF_ARCH; 
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity XTLOSC is
+
+  generic(
+    MODE:std_logic_vector := x"3";
+    FREQUENCY:real := 20.0
+  );
+
+  port(
+    CLKOUT : out   STD_ULOGIC;
+    XTL : in    STD_ULOGIC
+  );
+end XTLOSC;
+
+architecture DEF_ARCH of XTLOSC is 
+    attribute syn_black_box : boolean;
+    attribute syn_black_box of DEF_ARCH : architecture is true;
+    attribute black_box_pad_pin : string; 
+    attribute black_box_pad_pin of DEF_ARCH: architecture is "XTL"; 
+begin
+end DEF_ARCH;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity RCOSC_1MHZ_FAB is
+  port(
+         CLKOUT : out   STD_ULOGIC;
+            A   : in    STD_ULOGIC
+  );
+end RCOSC_1MHZ_FAB;
+
+architecture DEF_ARCH of RCOSC_1MHZ_FAB is 
+    attribute syn_black_box : boolean;
+    attribute syn_black_box of DEF_ARCH : architecture is true;
+begin
+end DEF_ARCH;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity RCOSC_25_50MHZ_FAB is
+  port(
+         CLKOUT : out   STD_ULOGIC;
+            A   : in    STD_ULOGIC
+  );
+end RCOSC_25_50MHZ_FAB;
+
+architecture DEF_ARCH of RCOSC_25_50MHZ_FAB is 
+    attribute syn_black_box : boolean;
+    attribute syn_black_box of DEF_ARCH : architecture is true;
+begin
+end DEF_ARCH;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity XTLOSC_FAB is
+  port(
+         CLKOUT : out   STD_ULOGIC;
+            A   : in    STD_ULOGIC
+  );
+end XTLOSC_FAB;
+
+architecture DEF_ARCH of XTLOSC_FAB is 
+    attribute syn_black_box : boolean;
+    attribute syn_black_box of DEF_ARCH : architecture is true;
+begin
+end DEF_ARCH;

hdl/syn/sf2-test/pnr_clocks.sdc

+create_clock -name clk -period 10 -waveform {0 5 } -add  [ get_pins { inst_uart.FCCC_C0_0.FCCC_C0_0.CCC_INST/GL0 } ]

hdl/syn/sf2-test/syn_clocks.sdc

+# create_clock -period 83.3333 [ get_ports { inst_uart/OSC_C0_0:XTLOSC_O2F } ]
+# create_generated_clock -multiply_by 25 -divide_by 3 -source [ get_pins { CCC_INST/XTLOSC } ] -phase 0 [ get_pins { CCC_INST/GL0 } ]
+
+# inst_uart.FCCC_C0_0.FCCC_C0_0.GL0_INST
+
+create_clock -period 10 [ get_pins { inst_uart/FCCC_C0_0/FCCC_C0_0/CCC_INST/GL0 } ]

hdl/top/sf2-test/FCCC_C0.vhd

+----------------------------------------------------------------------
+-- Created by SmartDesign Thu Nov 18 13:58:29 2021
+-- Version: v2021.2 2021.2.0.11
+----------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- Component Description (Tcl) 
+----------------------------------------------------------------------
+--# Exporting Component Description of FCCC_C0 to TCL
+--# Family: SmartFusion2
+--# Part Number: M2S050-FG484
+--# Create and Configure the core component FCCC_C0
+--create_and_configure_core -core_vlnv {Actel:SgCore:FCCC:2.0.201} -component_name {FCCC_C0} -params {\
+--"ADVANCED_TAB_CHANGED:false"  \
+--"CLK0_IS_USED:false"  \
+--"CLK0_PAD_IS_USED:false"  \
+--"CLK1_IS_USED:false"  \
+--"CLK1_PAD_IS_USED:false"  \
+--"CLK2_IS_USED:false"  \
+--"CLK2_PAD_IS_USED:false"  \
+--"CLK3_IS_USED:false"  \
+--"CLK3_PAD_IS_USED:false"  \
+--"DYN_CONF_IS_USED:false"  \
+--"GL0_BP_IN_0_FREQ:100"  \
+--"GL0_BP_IN_0_SRC:IO_HARDWIRED_0"  \
+--"GL0_BP_IN_1_FREQ:100"  \
+--"GL0_BP_IN_1_SRC:IO_HARDWIRED_0"  \
+--"GL0_FREQUENCY_LOCKED:false"  \
+--"GL0_IN_0_SRC:PLL"  \
+--"GL0_IN_1_SRC:UNUSED"  \
+--"GL0_IS_INVERTED:false"  \
+--"GL0_IS_USED:true"  \
+--"GL0_OUT_0_FREQ:100"  \
+--"GL0_OUT_1_FREQ:50"  \
+--"GL0_OUT_IS_GATED:false"  \
+--"GL0_PLL_IN_0_PHASE:0"  \
+--"GL0_PLL_IN_1_PHASE:0"  \
+--"GL1_BP_IN_0_FREQ:100"  \
+--"GL1_BP_IN_0_SRC:IO_HARDWIRED_0"  \
+--"GL1_BP_IN_1_FREQ:100"  \
+--"GL1_BP_IN_1_SRC:IO_HARDWIRED_0"  \
+--"GL1_FREQUENCY_LOCKED:false"  \
+--"GL1_IN_0_SRC:PLL"  \
+--"GL1_IN_1_SRC:UNUSED"  \
+--"GL1_IS_INVERTED:false"  \
+--"GL1_IS_USED:false"  \
+--"GL1_OUT_0_FREQ:100"  \
+--"GL1_OUT_1_FREQ:50"  \
+--"GL1_OUT_IS_GATED:false"  \
+--"GL1_PLL_IN_0_PHASE:0"  \
+--"GL1_PLL_IN_1_PHASE:0"  \
+--"GL2_BP_IN_0_FREQ:100"  \
+--"GL2_BP_IN_0_SRC:IO_HARDWIRED_0"  \
+--"GL2_BP_IN_1_FREQ:100"  \
+--"GL2_BP_IN_1_SRC:IO_HARDWIRED_0"  \
+--"GL2_FREQUENCY_LOCKED:false"  \
+--"GL2_IN_0_SRC:PLL"  \
+--"GL2_IN_1_SRC:UNUSED"  \
+--"GL2_IS_INVERTED:false"  \
+--"GL2_IS_USED:false"  \
+--"GL2_OUT_0_FREQ:100"  \
+--"GL2_OUT_1_FREQ:50"  \
+--"GL2_OUT_IS_GATED:false"  \
+--"GL2_PLL_IN_0_PHASE:0"  \
+--"GL2_PLL_IN_1_PHASE:0"  \
+--"GL3_BP_IN_0_FREQ:100"  \
+--"GL3_BP_IN_0_SRC:IO_HARDWIRED_0"  \
+--"GL3_BP_IN_1_FREQ:100"  \
+--"GL3_BP_IN_1_SRC:IO_HARDWIRED_0"  \
+--"GL3_FREQUENCY_LOCKED:false"  \
+--"GL3_IN_0_SRC:PLL"  \
+--"GL3_IN_1_SRC:UNUSED"  \
+--"GL3_IS_INVERTED:false"  \
+--"GL3_IS_USED:false"  \
+--"GL3_OUT_0_FREQ:100"  \
+--"GL3_OUT_1_FREQ:50"  \
+--"GL3_OUT_IS_GATED:false"  \
+--"GL3_PLL_IN_0_PHASE:0"  \
+--"GL3_PLL_IN_1_PHASE:0"  \
+--"GPD0_IS_USED:false"  \
+--"GPD0_NOPIPE_RSTSYNC:true"  \
+--"GPD0_SYNC_STYLE:G3STYLE_AND_NO_LOCK_RSTSYNC"  \
+--"GPD1_IS_USED:false"  \
+--"GPD1_NOPIPE_RSTSYNC:true"  \
+--"GPD1_SYNC_STYLE:G3STYLE_AND_NO_LOCK_RSTSYNC"  \
+--"GPD2_IS_USED:false"  \
+--"GPD2_NOPIPE_RSTSYNC:true"  \
+--"GPD2_SYNC_STYLE:G3STYLE_AND_NO_LOCK_RSTSYNC"  \
+--"GPD3_IS_USED:false"  \
+--"GPD3_NOPIPE_RSTSYNC:true"  \
+--"GPD3_SYNC_STYLE:G3STYLE_AND_NO_LOCK_RSTSYNC"  \
+--"GPD_EXPOSE_RESETS:false"  \
+--"GPD_SYNC_STYLE:G3STYLE_AND_LOCK_RSTSYNC"  \
+--"INIT:0000007F98000044D74000318C6318C1F18C61E40404040401802"  \
+--"IO_HARDWIRED_0_IS_DIFF:false"  \
+--"IO_HARDWIRED_1_IS_DIFF:false"  \
+--"IO_HARDWIRED_2_IS_DIFF:false"  \
+--"IO_HARDWIRED_3_IS_DIFF:false"  \
+--"MODE_10V:false"  \
+--"NGMUX0_HOLD_IS_USED:false"  \
+--"NGMUX0_IS_USED:false"  \
+--"NGMUX1_HOLD_IS_USED:false"  \
+--"NGMUX1_IS_USED:false"  \
+--"NGMUX2_HOLD_IS_USED:false"  \
+--"NGMUX2_IS_USED:false"  \
+--"NGMUX3_HOLD_IS_USED:false"  \
+--"NGMUX3_IS_USED:false"  \
+--"NGMUX_EXPOSE_HOLD:false"  \
+--"PLL_DELAY:0"  \
+--"PLL_EXPOSE_BYPASS:false"  \
+--"PLL_EXPOSE_RESETS:false"  \
+--"PLL_EXT_FB_GL:EXT_FB_GL0"  \
+--"PLL_FB_SRC:CCC_INTERNAL"  \
+--"PLL_IN_FREQ:12"  \
+--"PLL_IN_SRC:OSC_XTAL"  \
+--"PLL_IS_USED:true"  \
+--"PLL_LOCK_IND:1024"  \
+--"PLL_LOCK_WND:32000"  \
+--"PLL_SSM_DEPTH:0.5"  \
+--"PLL_SSM_ENABLE:false"  \
+--"PLL_SSM_FREQ:40"  \
+--"PLL_SUPPLY_VOLTAGE:25_V"  \
+--"PLL_VCO_TARGET:700"  \
+--"RCOSC_1MHZ_IS_USED:false"  \
+--"RCOSC_25_50MHZ_IS_USED:false"  \
+--"VCOFREQUENCY:800.000"  \
+--"XTLOSC_IS_USED:true"  \
+--"Y0_IS_USED:false"  \
+--"Y1_IS_USED:false"  \
+--"Y2_IS_USED:false"  \
+--"Y3_IS_USED:false"   }
+--# Exporting Component Description of FCCC_C0 to TCL done
+
+----------------------------------------------------------------------
+-- Libraries
+----------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+
+library smartfusion2;
+use smartfusion2.all;
+----------------------------------------------------------------------
+-- FCCC_C0 entity declaration
+----------------------------------------------------------------------
+entity FCCC_C0 is
+    -- Port list
+    port(
+        -- Inputs
+        XTLOSC : in  std_logic;
+        -- Outputs
+        GL0    : out std_logic;
+        LOCK   : out std_logic
+        );
+end FCCC_C0;
+----------------------------------------------------------------------
+-- FCCC_C0 architecture body
+----------------------------------------------------------------------
+architecture RTL of FCCC_C0 is
+----------------------------------------------------------------------
+-- Component declarations
+----------------------------------------------------------------------
+-- FCCC_C0_FCCC_C0_0_FCCC   -   Actel:SgCore:FCCC:2.0.201
+component FCCC_C0_FCCC_C0_0_FCCC
+    -- Port list
+    port(
+        -- Inputs
+        XTLOSC : in  std_logic;
+        -- Outputs
+        GL0    : out std_logic;
+        LOCK   : out std_logic
+        );
+end component;
+----------------------------------------------------------------------
+-- Signal declarations
+----------------------------------------------------------------------
+signal GL0_net_0  : std_logic;
+signal LOCK_net_0 : std_logic;
+signal GL0_net_1  : std_logic;
+signal LOCK_net_1 : std_logic;
+----------------------------------------------------------------------
+-- TiedOff Signals
+----------------------------------------------------------------------
+signal GND_net    : std_logic;
+signal PADDR_const_net_0: std_logic_vector(7 downto 2);
+signal PWDATA_const_net_0: std_logic_vector(7 downto 0);
+
+begin
+----------------------------------------------------------------------
+-- Constant assignments
+----------------------------------------------------------------------
+ GND_net            <= '0';
+ PADDR_const_net_0  <= B"000000";
+ PWDATA_const_net_0 <= B"00000000";
+----------------------------------------------------------------------
+-- Top level output port assignments
+----------------------------------------------------------------------
+ GL0_net_1  <= GL0_net_0;
+ GL0        <= GL0_net_1;
+ LOCK_net_1 <= LOCK_net_0;
+ LOCK       <= LOCK_net_1;
+----------------------------------------------------------------------
+-- Component instances
+----------------------------------------------------------------------
+-- FCCC_C0_0   -   Actel:SgCore:FCCC:2.0.201
+FCCC_C0_0 : FCCC_C0_FCCC_C0_0_FCCC
+    port map( 
+        -- Inputs
+        XTLOSC => XTLOSC,
+        -- Outputs
+        GL0    => GL0_net_0,
+        LOCK   => LOCK_net_0 
+        );
+
+end RTL;

hdl/top/sf2-test/FCCC_C0_FCCC_C0_0_FCCC.vhd

+-- Version: v2021.2 2021.2.0.11
+
+library ieee;
+use ieee.std_logic_1164.all;
+library smartfusion2;
+use smartfusion2.all;
+
+entity FCCC_C0_FCCC_C0_0_FCCC is
+
+    port( XTLOSC : in    std_logic;
+          LOCK   : out   std_logic;
+          GL0    : out   std_logic
+        );
+
+end FCCC_C0_FCCC_C0_0_FCCC;
+
+architecture DEF_ARCH of FCCC_C0_FCCC_C0_0_FCCC is 
+
+  component VCC
+    port( Y : out   std_logic
+        );
+  end component;
+
+  component GND
+    port( Y : out   std_logic
+        );
+  end component;
+
+  component CLKINT
+    port( A : in    std_logic := 'U';
+          Y : out   std_logic
+        );
+  end component;
+
+  component CCC
+
+            generic (INIT:std_logic_vector(209 downto 0) := "00" & x"0000000000000000000000000000000000000000000000000000"; 
+        VCOFREQUENCY:real := 0.0);
+
+    port( Y0              : out   std_logic;
+          Y1              : out   std_logic;
+          Y2              : out   std_logic;
+          Y3              : out   std_logic;
+          PRDATA          : out   std_logic_vector(7 downto 0);
+          LOCK            : out   std_logic;
+          BUSY            : out   std_logic;
+          CLK0            : in    std_logic := 'U';
+          CLK1            : in    std_logic := 'U';
+          CLK2            : in    std_logic := 'U';
+          CLK3            : in    std_logic := 'U';
+          NGMUX0_SEL      : in    std_logic := 'U';
+          NGMUX1_SEL      : in    std_logic := 'U';
+          NGMUX2_SEL      : in    std_logic := 'U';
+          NGMUX3_SEL      : in    std_logic := 'U';
+          NGMUX0_HOLD_N   : in    std_logic := 'U';
+          NGMUX1_HOLD_N   : in    std_logic := 'U';
+          NGMUX2_HOLD_N   : in    std_logic := 'U';
+          NGMUX3_HOLD_N   : in    std_logic := 'U';
+          NGMUX0_ARST_N   : in    std_logic := 'U';
+          NGMUX1_ARST_N   : in    std_logic := 'U';
+          NGMUX2_ARST_N   : in    std_logic := 'U';
+          NGMUX3_ARST_N   : in    std_logic := 'U';
+          PLL_BYPASS_N    : in    std_logic := 'U';
+          PLL_ARST_N      : in    std_logic := 'U';
+          PLL_POWERDOWN_N : in    std_logic := 'U';
+          GPD0_ARST_N     : in    std_logic := 'U';
+          GPD1_ARST_N     : in    std_logic := 'U';
+          GPD2_ARST_N     : in    std_logic := 'U';
+          GPD3_ARST_N     : in    std_logic := 'U';
+          PRESET_N        : in    std_logic := 'U';
+          PCLK            : in    std_logic := 'U';
+          PSEL            : in    std_logic := 'U';
+          PENABLE         : in    std_logic := 'U';
+          PWRITE          : in    std_logic := 'U';
+          PADDR           : in    std_logic_vector(7 downto 2) := (others => 'U');
+          PWDATA          : in    std_logic_vector(7 downto 0) := (others => 'U');
+          CLK0_PAD        : in    std_logic := 'U';
+          CLK1_PAD        : in    std_logic := 'U';
+          CLK2_PAD        : in    std_logic := 'U';
+          CLK3_PAD        : in    std_logic := 'U';
+          GL0             : out   std_logic;
+          GL1             : out   std_logic;
+          GL2             : out   std_logic;
+          GL3             : out   std_logic;
+          RCOSC_25_50MHZ  : in    std_logic := 'U';
+          RCOSC_1MHZ      : in    std_logic := 'U';
+          XTLOSC          : in    std_logic := 'U'
+        );
+  end component;
+
+    signal gnd_net, vcc_net, GL0_net : std_logic;
+    signal nc8, nc7, nc6, nc2, nc5, nc4, nc3, nc1 : std_logic;
+
+begin 
+
+
+    vcc_inst : VCC
+      port map(Y => vcc_net);
+    
+    gnd_inst : GND
+      port map(Y => gnd_net);
+    
+    GL0_INST : CLKINT
+      port map(A => GL0_net, Y => GL0);
+    
+    CCC_INST : CCC
+
+              generic map(INIT => "00" & x"000007F98000044D74000318C6318C1F18C61E40404040401802",
+         VCOFREQUENCY => 800.000)
+
+      port map(Y0 => OPEN, Y1 => OPEN, Y2 => OPEN, Y3 => OPEN, 
+        PRDATA(7) => nc8, PRDATA(6) => nc7, PRDATA(5) => nc6, 
+        PRDATA(4) => nc2, PRDATA(3) => nc5, PRDATA(2) => nc4, 
+        PRDATA(1) => nc3, PRDATA(0) => nc1, LOCK => LOCK, BUSY
+         => OPEN, CLK0 => vcc_net, CLK1 => vcc_net, CLK2 => 
+        vcc_net, CLK3 => vcc_net, NGMUX0_SEL => gnd_net, 
+        NGMUX1_SEL => gnd_net, NGMUX2_SEL => gnd_net, NGMUX3_SEL
+         => gnd_net, NGMUX0_HOLD_N => vcc_net, NGMUX1_HOLD_N => 
+        vcc_net, NGMUX2_HOLD_N => vcc_net, NGMUX3_HOLD_N => 
+        vcc_net, NGMUX0_ARST_N => vcc_net, NGMUX1_ARST_N => 
+        vcc_net, NGMUX2_ARST_N => vcc_net, NGMUX3_ARST_N => 
+        vcc_net, PLL_BYPASS_N => vcc_net, PLL_ARST_N => vcc_net, 
+        PLL_POWERDOWN_N => vcc_net, GPD0_ARST_N => vcc_net, 
+        GPD1_ARST_N => vcc_net, GPD2_ARST_N => vcc_net, 
+        GPD3_ARST_N => vcc_net, PRESET_N => gnd_net, PCLK => 
+        vcc_net, PSEL => vcc_net, PENABLE => vcc_net, PWRITE => 
+        vcc_net, PADDR(7) => vcc_net, PADDR(6) => vcc_net, 
+        PADDR(5) => vcc_net, PADDR(4) => vcc_net, PADDR(3) => 
+        vcc_net, PADDR(2) => vcc_net, PWDATA(7) => vcc_net, 
+        PWDATA(6) => vcc_net, PWDATA(5) => vcc_net, PWDATA(4) => 
+        vcc_net, PWDATA(3) => vcc_net, PWDATA(2) => vcc_net, 
+        PWDATA(1) => vcc_net, PWDATA(0) => vcc_net, CLK0_PAD => 
+        gnd_net, CLK1_PAD => gnd_net, CLK2_PAD => gnd_net, 
+        CLK3_PAD => gnd_net, GL0 => GL0_net, GL1 => OPEN, GL2 => 
+        OPEN, GL3 => OPEN, RCOSC_25_50MHZ => gnd_net, RCOSC_1MHZ
+         => gnd_net, XTLOSC => XTLOSC);
+    
+
+end DEF_ARCH; 

hdl/top/sf2-test/Manifest.py

+files = ['sf2_test.vhd', 'uart.vhd',
+         'uart_MSS.vhd', 'uart_MSS_syn.vhd',
+         'OSC_C0.vhd', 'OSC_C0_OSC_C0_0_OSC.vhd',
+         'FCCC_C0.vhd', 'FCCC_C0_FCCC_C0_0_FCCC.vhd']
+
+modules = {
+    'local': ['../../rtl'],
+    "git": [
+        "git://ohwr.org/project/general-cores.git",
+        "git://ohwr.org/project/urv-core.git",
+    ],
+    "system": ['smartfusion2'],
+}
+

hdl/top/sf2-test/OSC_C0.vhd

+----------------------------------------------------------------------
+-- Created by SmartDesign Thu Nov 18 13:57:03 2021
+-- Version: v2021.2 2021.2.0.11
+----------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- Component Description (Tcl) 
+----------------------------------------------------------------------
+--# Exporting Component Description of OSC_C0 to TCL
+--# Family: SmartFusion2
+--# Part Number: M2S050-FG484
+--# Create and Configure the core component OSC_C0
+--create_and_configure_core -core_vlnv {Actel:SgCore:OSC:2.0.101} -component_name {OSC_C0} -params {\
+--"RCOSC_1MHZ_DRIVES_CCC:false"  \
+--"RCOSC_1MHZ_DRIVES_FAB:false"  \
+--"RCOSC_1MHZ_IS_USED:false"  \
+--"RCOSC_25_50MHZ_DRIVES_CCC:false"  \
+--"RCOSC_25_50MHZ_DRIVES_FAB:false"  \
+--"RCOSC_25_50MHZ_IS_USED:false"  \
+--"VOLTAGE_IS_1_2:true"  \
+--"XTLOSC_DRIVES_CCC:1"  \
+--"XTLOSC_DRIVES_FAB:1"  \
+--"XTLOSC_FREQ:12.00"  \
+--"XTLOSC_IS_USED:1"  \
+--"XTLOSC_SRC:CRYSTAL"   }
+--# Exporting Component Description of OSC_C0 to TCL done
+
+----------------------------------------------------------------------
+-- Libraries
+----------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+
+library smartfusion2;
+use smartfusion2.all;
+----------------------------------------------------------------------
+-- OSC_C0 entity declaration
+----------------------------------------------------------------------
+entity OSC_C0 is
+    -- Port list
+    port(
+        -- Inputs
+        XTL        : in  std_logic;
+        -- Outputs
+        XTLOSC_CCC : out std_logic;
+        XTLOSC_O2F : out std_logic
+        );
+end OSC_C0;
+----------------------------------------------------------------------
+-- OSC_C0 architecture body
+----------------------------------------------------------------------
+architecture RTL of OSC_C0 is
+----------------------------------------------------------------------
+-- Component declarations
+----------------------------------------------------------------------
+-- OSC_C0_OSC_C0_0_OSC   -   Actel:SgCore:OSC:2.0.101
+component OSC_C0_OSC_C0_0_OSC
+    -- Port list
+    port(
+        -- Inputs
+        XTL                : in  std_logic;
+        -- Outputs
+        RCOSC_1MHZ_CCC     : out std_logic;
+        RCOSC_1MHZ_O2F     : out std_logic;
+        RCOSC_25_50MHZ_CCC : out std_logic;
+        RCOSC_25_50MHZ_O2F : out std_logic;
+        XTLOSC_CCC         : out std_logic;
+        XTLOSC_O2F         : out std_logic
+        );
+end component;
+----------------------------------------------------------------------
+-- Signal declarations
+----------------------------------------------------------------------
+signal XTLOSC_CCC_OUT_XTLOSC_CCC       : std_logic;
+signal XTLOSC_O2F_net_0                : std_logic;
+signal XTLOSC_O2F_net_1                : std_logic;
+signal XTLOSC_CCC_OUT_XTLOSC_CCC_net_0 : std_logic;
+
+begin
+----------------------------------------------------------------------
+-- Top level output port assignments
+----------------------------------------------------------------------
+ XTLOSC_O2F_net_1                <= XTLOSC_O2F_net_0;
+ XTLOSC_O2F                      <= XTLOSC_O2F_net_1;
+ XTLOSC_CCC_OUT_XTLOSC_CCC_net_0 <= XTLOSC_CCC_OUT_XTLOSC_CCC;
+ XTLOSC_CCC                      <= XTLOSC_CCC_OUT_XTLOSC_CCC_net_0;
+----------------------------------------------------------------------
+-- Component instances
+----------------------------------------------------------------------
+-- OSC_C0_0   -   Actel:SgCore:OSC:2.0.101
+OSC_C0_0 : OSC_C0_OSC_C0_0_OSC
+    port map( 
+        -- Inputs
+        XTL                => XTL,
+        -- Outputs
+        RCOSC_25_50MHZ_CCC => OPEN,
+        RCOSC_25_50MHZ_O2F => OPEN,
+        RCOSC_1MHZ_CCC     => OPEN,
+        RCOSC_1MHZ_O2F     => OPEN,
+        XTLOSC_CCC         => XTLOSC_CCC_OUT_XTLOSC_CCC,
+        XTLOSC_O2F         => XTLOSC_O2F_net_0 
+        );
+
+end RTL;

hdl/top/sf2-test/OSC_C0_OSC_C0_0_OSC.vhd

+-- Version: v2021.2 2021.2.0.11
+
+library ieee;
+use ieee.std_logic_1164.all;
+library smartfusion2;
+use smartfusion2.all;
+
+entity OSC_C0_OSC_C0_0_OSC is
+
+    port( XTL                : in    std_logic;
+          RCOSC_25_50MHZ_CCC : out   std_logic;
+          RCOSC_25_50MHZ_O2F : out   std_logic;
+          RCOSC_1MHZ_CCC     : out   std_logic;
+          RCOSC_1MHZ_O2F     : out   std_logic;
+          XTLOSC_CCC         : out   std_logic;
+          XTLOSC_O2F         : out   std_logic
+        );
+
+end OSC_C0_OSC_C0_0_OSC;
+
+architecture DEF_ARCH of OSC_C0_OSC_C0_0_OSC is 
+
+  component XTLOSC_FAB
+    port( A      : in    std_logic := 'U';
+          CLKOUT : out   std_logic
+        );
+  end component;
+
+  component XTLOSC
+    generic (MODE:std_logic_vector(1 downto 0) := "11"; 
+        FREQUENCY:real := 20.0);
+
+    port( XTL    : in    std_logic := 'U';
+          CLKOUT : out   std_logic
+        );
+  end component;
+
+  component CLKINT
+    port( A : in    std_logic := 'U';
+          Y : out   std_logic
+        );
+  end component;
+
+    signal N_XTLOSC_CCC, N_XTLOSC_CLKINT : std_logic;
+
+begin 
+
+    XTLOSC_CCC <= N_XTLOSC_CCC;
+
+    I_XTLOSC_FAB : XTLOSC_FAB
+      port map(A => N_XTLOSC_CCC, CLKOUT => N_XTLOSC_CLKINT);
+    
+    I_XTLOSC : XTLOSC
+      generic map(MODE => "11", FREQUENCY => 12.0)
+
+      port map(XTL => XTL, CLKOUT => N_XTLOSC_CCC);
+    
+    I_XTLOSC_FAB_CLKINT : CLKINT
+      port map(A => N_XTLOSC_CLKINT, Y => XTLOSC_O2F);
+    
+
+end DEF_ARCH; 

hdl/top/sf2-test/sf2_test.vhd

+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+--library smartfusion2;
+--use smartfusion2.all;
+
+entity sf2_test is
+    port (
+    xtl   : in  std_logic;
+    devrst_n : in std_logic;
+
+    led1_o : out std_logic;
+    led2_o : out std_logic;
+    but_i : in std_logic;
+
+    rx_i : std_logic;
+    tx_o : out std_logic
+  );
+end sf2_test;
+
+architecture behav of sf2_test is
+  attribute syn_netlist_hierarchy : boolean;
+  attribute syn_netlist_hierarchy of behav: architecture is false;
+  
+  signal FIC_0_AHB_S_HADDR     : std_logic_vector(31 downto 0);
+  signal FIC_0_AHB_S_HMASTLOCK : std_logic;
+  signal FIC_0_AHB_S_HREADY    : std_logic;
+  signal FIC_0_AHB_S_HSEL      : std_logic;
+  signal FIC_0_AHB_S_HSIZE     : std_logic_vector(1 downto 0);
+  signal FIC_0_AHB_S_HTRANS    : std_logic_vector(1 downto 0);
+  signal FIC_0_AHB_S_HWDATA    : std_logic_vector(31 downto 0);
+  signal FIC_0_AHB_S_HWRITE    : std_logic;
+  signal M3_RESET_N            : std_logic;
+  signal POWER_ON_RESET_N      : std_logic;
+  signal MMUART_0_RXD          : std_logic;
+  signal FIC_0_AHB_S_HRDATA    : std_logic_vector(31 downto 0);
+  signal FIC_0_AHB_S_HREADYOUT : std_logic;
+  signal FIC_0_AHB_S_HRESP     : std_logic;
+  signal MSS_RESET_N_M2F       : std_logic;
+  signal LOCK                  : std_logic;
+  signal MMUART_0_TXD          : std_logic;
+  signal clk_100               : std_logic;
+
+  signal rst_n : std_logic;
+
+  type state_t is (INIT_DELAY,
+                   INIT_UART_RESET_R,
+                   INIT_UART_RESET_W,
+                   INIT_UART_LCR_DLAB,
+                   INIT_UART_DLR,
+                   INIT_UART_DMR,
+                   INIT_UART_DLR_2,
+                   INIT_UART_LCR,
+                   READ_NVM,
+                   WRITE_MEM,
+                   READ_STATUS,
+                   SEND_RECV,
+                   UART_RECV,
+                   UART_SEND);
+  signal state : state_t;
+  signal counter : unsigned(27 downto 0);
+
+  signal ahb_start, ahb_done, ahb_rw : std_logic;
+  signal ahb_addr, ahb_wdata, ahb_rdata : std_logic_vector(31 downto 0);
+
+  --  To send a byte: wait until uart_tx_rdy = '1', set byte and pulse cmd.
+  signal uart_tx_byte : std_logic_vector(7 downto 0);
+  signal uart_tx_rdy : std_logic;
+  signal uart_tx_cmd : std_logic;
+  signal uart_tx_creg : std_logic;
+
+  --  To recv a byte: wait until uart_rx_rdy = '1', read byte, pulse cmd.
+  signal uart_rx_byte : std_logic_vector(7 downto 0);
+  signal uart_rx_rdy : std_logic;
+  signal uart_rx_cmd : std_logic;
+
+  type ahb_state_t is (STATE_AHB_IDLE, STATE_AHB_ADDR, STATE_AHB_DATA);
+  signal ahb_state : ahb_state_t;
+
+  signal letter : std_logic_vector(7 downto 0);
+
+  constant mem_abits : natural := 11; -- 2K * 32
+
+  type mem_t is array (natural range <>) of std_logic_vector(31 downto 0);
+  signal mem : mem_t (0 to 2**mem_abits - 1);
+
+  signal mem_raddr : unsigned(mem_abits - 1 downto 0);
+  signal mem_we : std_logic;
+  signal mem_play : std_logic;
+begin
+  inst_uart: entity work.uart
+    port map (
+      FIC_0_AHB_S_HADDR     => FIC_0_AHB_S_HADDR,
+      FIC_0_AHB_S_HMASTLOCK => FIC_0_AHB_S_HMASTLOCK,
+      FIC_0_AHB_S_HREADY    => FIC_0_AHB_S_HREADY,
+      FIC_0_AHB_S_HSEL      => FIC_0_AHB_S_HSEL,
+      FIC_0_AHB_S_HSIZE     => FIC_0_AHB_S_HSIZE,
+      FIC_0_AHB_S_HTRANS    => FIC_0_AHB_S_HTRANS,
+      FIC_0_AHB_S_HWDATA    => FIC_0_AHB_S_HWDATA,
+      FIC_0_AHB_S_HWRITE    => FIC_0_AHB_S_HWRITE,
+      FIC_0_AHB_S_HRDATA    => FIC_0_AHB_S_HRDATA,
+      FIC_0_AHB_S_HREADYOUT => FIC_0_AHB_S_HREADYOUT,
+      FIC_0_AHB_S_HRESP     => FIC_0_AHB_S_HRESP,
+      M3_RESET_N            => M3_RESET_N,
+      MMUART_0_RXD          => MMUART_0_RXD,
+      XTL                   => XTL,
+      LOCK                  => LOCK,
+      MMUART_0_TXD          => MMUART_0_TXD,
+      MSS_RESET_N_M2F       => MSS_RESET_N_M2F,
+      DEVRST_N              => devrst_n,
+      POWER_ON_RESET_N      => POWER_ON_RESET_N,
+      clk_100               => clk_100);
+
+  tx_o <= MMUART_0_TXD;
+  MMUART_0_RXD <= rx_i;
+
+  M3_RESET_N <= '0';
+
+  rst_n <= POWER_ON_RESET_N and LOCK and MSS_RESET_N_M2F;
+  
+  proc_led: process (clk_100)
+  begin
+    if rising_edge(clk_100) then
+      if rst_n = '0' then
+        led1_o <= '1';
+        led2_o <= '1';
+      else
+        led1_o <= counter (25);
+        led2_o <= counter (23);
+      end if;
+    end if;
+  end process;
+
+  proc_main: process (clk_100)
+  begin
+    if rising_edge(clk_100) then
+      uart_rx_cmd <= '0';
+      uart_tx_cmd <= '0';
+      
+      if rst_n = '0' then
+        letter <= x"41";
+        mem_raddr <= (others => '0');
+        mem_play <= '1';
+      else
+        if mem_play = '1' then
+          letter <= mem (to_integer (mem_raddr))(7 downto 0);
+        end if;
+        if counter (25 downto 0) = (25 downto 0 => '1')
+          and uart_tx_rdy = '1'
+        then
+          uart_tx_cmd <= '1';
+          uart_tx_byte <= letter;
+          if mem_play = '1' then
+            if letter = (7 downto 0 => '0') then
+              mem_play <= '0';
+              letter <= x"41";
+            else
+              mem_raddr <= mem_raddr + 1;
+            end if;
+          else
+            if letter = x"5A" then
+              letter <= x"41";
+            elsif letter = x"7A" then
+              letter <= x"61";
+            elsif letter = x"7E" or letter (7) = '1' then
+              letter <= x"20";
+            else
+              letter <= std_logic_vector(unsigned(letter) + 1);
+            end if;
+          end if;
+        else
+          if uart_rx_rdy = '1' then
+            letter <= uart_rx_byte;
+            uart_rx_cmd <= '1';
+            if letter = x"0c" then
+              mem_raddr <= (others => '0');
+              mem_play <= not mem_play;
+            end if;
+          end if;
+
+          if but_i = '0' then
+            letter <= x"41";
+          end if;
+        end if;
+      end if;
+    end if;
+  end process;
+
+  proc_uart: process (clk_100)
+  begin
+    if rising_edge(clk_100) then
+      ahb_start <= '0';
+      mem_we <= '0';
+
+      if rst_n = '0' then
+        state <= INIT_DELAY;
+        counter <= (others => '0');
+        uart_rx_rdy <= '0';
+        uart_tx_rdy <= '0';
+        uart_tx_creg <= '0';
+      else
+        uart_tx_creg <= uart_tx_creg or uart_tx_cmd;
+        uart_rx_rdy <= uart_rx_rdy and not uart_rx_cmd;
+
+        case state is
+          when INIT_DELAY =>
+            if counter = x"c00_0000" then
+              state <= INIT_UART_RESET_R;
+            end if;
+            counter <= counter + 1;
+          when INIT_UART_RESET_R =>
+            --  1. Clear reset
+            ahb_addr <= x"4003_8048";
+            ahb_rw <= '1';
+            ahb_start <= '1';
+            counter <= (others => '0');
+            state <= INIT_UART_RESET_W;
+          when INIT_UART_RESET_W =>
+            if ahb_done = '1' then
+              ahb_addr <= x"4003_8048";
+              ahb_wdata <= ahb_rdata and x"ffff_ff7f";
+              ahb_rw <= '0';
+              ahb_start <= '1';
+              state <= INIT_UART_LCR_DLAB;
+            end if;
+          when INIT_UART_LCR_DLAB =>
+            if ahb_done = '1' then
+              ahb_addr <= x"4000_000C"; --  LCR
+              ahb_wdata <= x"000000_80";
+              ahb_rw <= '0';
+              ahb_start <= '1';
+              state <= INIT_UART_DLR;
+            end if;
+          when INIT_UART_DLR =>
+            if ahb_done = '1' then
+              ahb_addr <= x"4000_0000";
+              ahb_wdata <= x"000000_36";
+              ahb_rw <= '0';
+              ahb_start <= '1';
+              state <= INIT_UART_DMR;
+            end if;
+          when INIT_UART_DMR =>
+            if ahb_done = '1' then
+              ahb_addr <= x"4000_0004";
+              ahb_wdata <= x"000000_00";
+              ahb_rw <= '0';
+              ahb_start <= '1';
+              state <= INIT_UART_DLR_2;
+            end if;
+          when INIT_UART_DLR_2 =>
+            if ahb_done = '1' then
+              ahb_addr <= x"4000_000C"; --  LCR
+              ahb_wdata <= x"000000_03";
+              ahb_rw <= '0';
+              ahb_start <= '1';
+              state <= INIT_UART_LCR;
+            end if;
+          when INIT_UART_LCR =>
+            if ahb_done = '1' then
+              state <= READ_NVM;
+            end if;
+          when READ_NVM =>
+            ahb_addr <= std_logic_vector (x"6000" & counter (15 downto 0));
+            ahb_rw <= '1';
+            ahb_start <= '1';
+            state <= WRITE_MEM;
+          when WRITE_MEM =>
+            if ahb_done = '1' then
+              mem_we <= '1';
+              if counter = x"000_07fc" then
+                state <= READ_STATUS;
+              else
+                counter <= counter + 4;
+                state <= READ_NVM;
+              end if;
+            end if;
+          when READ_STATUS =>
+            counter <= counter + 1;
+
+            ahb_addr <= x"4000_0014"; --  LSR
+            ahb_rw <= '1';
+            ahb_start <= '1';
+            state <= SEND_RECV;
+          when SEND_RECV =>
+            counter <= counter + 1;
+
+            if ahb_done = '1' then
+              ahb_addr <= x"4000_0000"; --  rx/tx
+              uart_tx_rdy <= ahb_rdata(5); -- TEMT transmit empty
+              if ahb_rdata(0) = '1' then
+                --  Data ready -> read byte.
+                ahb_rw <= '1';
+                ahb_start <= '1';
+                state <= UART_RECV;
+              elsif uart_tx_creg = '1' and ahb_rdata(5) = '1' then
+                --  Byte to transmit.
+                ahb_rw <= '0';
+                ahb_start <= '1';
+                ahb_wdata (31 downto 8) <= (others => '0');
+                ahb_wdata (7 downto 0) <= uart_tx_byte;
+                uart_tx_creg <= '0';
+                state <= UART_SEND;
+              else
+                state <= READ_STATUS;
+              end if;
+            end if;
+          when UART_RECV =>
+            counter <= counter + 1;
+            if ahb_done = '1' then
+              uart_rx_byte <= ahb_rdata (7 downto 0);
+              uart_rx_rdy <= '1';
+              state <= READ_STATUS;
+            end if;
+          when UART_SEND =>
+            counter <= counter + 1;
+            if ahb_done = '1' then
+              state <= READ_STATUS;
+            end if;
+        end case;
+      end if;
+    end if;
+  end process;
+
+  proc_memw: process (clk_100)
+  begin
+    if rising_edge(clk_100) then
+      if mem_we = '1' then
+        mem(to_integer(counter (mem_abits - 1 + 2 downto 2))) <= ahb_rdata;
+      end if;
+    end if;
+  end process;
+  
+  proc_ahb: process (clk_100)
+  begin
+    if rising_edge(clk_100) then
+      FIC_0_AHB_S_HTRANS <= "00";
+      FIC_0_AHB_S_HSEL <= '0';
+      ahb_done <= '0';
+
+      if rst_n = '0' then
+        ahb_state <= STATE_AHB_IDLE;
+      else
+        case ahb_state is
+          when STATE_AHB_IDLE =>
+            if ahb_start = '1' then
+              FIC_0_AHB_S_HADDR  <= ahb_addr;
+              FIC_0_AHB_S_HTRANS <= "10";
+              FIC_0_AHB_S_HWDATA <= ahb_wdata;
+              FIC_0_AHB_S_HWRITE <= not ahb_rw;
+              FIC_0_AHB_S_HSEL <= '1';
+              ahb_state <= STATE_AHB_ADDR;
+            end if;
+          when STATE_AHB_ADDR =>
+            --  Ready is expected to be 1.
+            ahb_state <= STATE_AHB_DATA;
+          when STATE_AHB_DATA =>
+            if FIC_0_AHB_S_HREADYOUT = '1' then
+              ahb_state <= STATE_AHB_IDLE;
+              ahb_rdata <= FIC_0_AHB_S_HRDATA;
+              ahb_done <= '1';
+            end if;
+        end case;
+      end if; 
+    end if;
+  end process;
+
+  FIC_0_AHB_S_HMASTLOCK <= '0';
+  FIC_0_AHB_S_HSIZE <= "10"; --  Transfer size is always 32 bits.
+  FIC_0_AHB_S_HREADY <= FIC_0_AHB_S_HREADYOUT;
+end behav;

hdl/top/sf2-test/uart.vhd

+----------------------------------------------------------------------
+-- Created by SmartDesign Fri Nov 19 10:22:58 2021
+-- Version: v2021.2 2021.2.0.11
+----------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- Libraries
+----------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+
+library smartfusion2;
+use smartfusion2.all;
+----------------------------------------------------------------------
+-- uart entity declaration
+----------------------------------------------------------------------
+entity uart is
+    -- Port list
+    port(
+        -- Inputs
+        DEVRST_N              : in  std_logic;
+        FIC_0_AHB_S_HADDR     : in  std_logic_vector(31 downto 0);
+        FIC_0_AHB_S_HMASTLOCK : in  std_logic;
+        FIC_0_AHB_S_HREADY    : in  std_logic;
+        FIC_0_AHB_S_HSEL      : in  std_logic;
+        FIC_0_AHB_S_HSIZE     : in  std_logic_vector(1 downto 0);
+        FIC_0_AHB_S_HTRANS    : in  std_logic_vector(1 downto 0);
+        FIC_0_AHB_S_HWDATA    : in  std_logic_vector(31 downto 0);
+        FIC_0_AHB_S_HWRITE    : in  std_logic;
+        M3_RESET_N            : in  std_logic;
+        MMUART_0_RXD          : in  std_logic;
+        XTL                   : in  std_logic;
+        -- Outputs
+        FIC_0_AHB_S_HRDATA    : out std_logic_vector(31 downto 0);
+        FIC_0_AHB_S_HREADYOUT : out std_logic;
+        FIC_0_AHB_S_HRESP     : out std_logic;
+        LOCK                  : out std_logic;
+        MMUART_0_TXD          : out std_logic;
+        MSS_RESET_N_M2F       : out std_logic;
+        POWER_ON_RESET_N      : out std_logic;
+        clk_100               : out std_logic
+        );
+end uart;
+----------------------------------------------------------------------
+-- uart architecture body
+----------------------------------------------------------------------
+architecture RTL of uart is
+----------------------------------------------------------------------
+-- Component declarations
+----------------------------------------------------------------------
+-- FCCC_C0
+component FCCC_C0
+    -- Port list
+    port(
+        -- Inputs
+        XTLOSC : in  std_logic;
+        -- Outputs
+        GL0    : out std_logic;
+        LOCK   : out std_logic
+        );
+end component;
+-- OSC_C0
+component OSC_C0
+    -- Port list
+    port(
+        -- Inputs
+        XTL        : in  std_logic;
+        -- Outputs
+        XTLOSC_CCC : out std_logic;
+        XTLOSC_O2F : out std_logic
+        );
+end component;
+-- SYSRESET
+component SYSRESET
+    -- Port list
+    port(
+        -- Inputs
+        DEVRST_N         : in  std_logic;
+        -- Outputs
+        POWER_ON_RESET_N : out std_logic
+        );
+end component;
+-- uart_MSS
+component uart_MSS
+    -- Port list
+    port(
+        -- Inputs
+        FIC_0_AHB_S_HADDR     : in  std_logic_vector(31 downto 0);
+        FIC_0_AHB_S_HMASTLOCK : in  std_logic;
+        FIC_0_AHB_S_HREADY    : in  std_logic;
+        FIC_0_AHB_S_HSEL      : in  std_logic;
+        FIC_0_AHB_S_HSIZE     : in  std_logic_vector(1 downto 0);
+        FIC_0_AHB_S_HTRANS    : in  std_logic_vector(1 downto 0);
+        FIC_0_AHB_S_HWDATA    : in  std_logic_vector(31 downto 0);
+        FIC_0_AHB_S_HWRITE    : in  std_logic;
+        M3_RESET_N            : in  std_logic;
+        MCCC_CLK_BASE         : in  std_logic;
+        MMUART_0_RXD          : in  std_logic;
+        -- Outputs
+        FIC_0_AHB_S_HRDATA    : out std_logic_vector(31 downto 0);
+        FIC_0_AHB_S_HREADYOUT : out std_logic;
+        FIC_0_AHB_S_HRESP     : out std_logic;
+        MMUART_0_TXD          : out std_logic;
+        MSS_RESET_N_M2F       : out std_logic
+        );
+end component;
+----------------------------------------------------------------------
+-- Signal declarations
+----------------------------------------------------------------------
+signal clk_100_net_0                      : std_logic;
+signal FIC_0_AHB_SLAVE_HRDATA             : std_logic_vector(31 downto 0);
+signal FIC_0_AHB_SLAVE_HREADYOUT          : std_logic;
+signal FIC_0_AHB_SLAVE_HRESP              : std_logic;
+signal LOCK_net_0                         : std_logic;
+signal MMUART_0_TXD_net_0                 : std_logic;
+signal MSS_RESET_N_M2F_net_0              : std_logic;
+signal OSC_C0_0_XTLOSC_CCC_OUT_XTLOSC_CCC : std_logic;
+signal POWER_ON_RESET_N_net_0             : std_logic;
+signal MMUART_0_TXD_net_1                 : std_logic;
+signal clk_100_net_1                      : std_logic;
+signal LOCK_net_1                         : std_logic;
+signal POWER_ON_RESET_N_net_1             : std_logic;
+signal FIC_0_AHB_SLAVE_HRDATA_net_0       : std_logic_vector(31 downto 0);
+signal FIC_0_AHB_SLAVE_HREADYOUT_net_0    : std_logic;
+signal FIC_0_AHB_SLAVE_HRESP_net_0        : std_logic;
+signal MSS_RESET_N_M2F_net_1              : std_logic;
+
+begin
+----------------------------------------------------------------------
+-- Top level output port assignments
+----------------------------------------------------------------------
+ MMUART_0_TXD_net_1              <= MMUART_0_TXD_net_0;
+ MMUART_0_TXD                    <= MMUART_0_TXD_net_1;
+ clk_100_net_1                   <= clk_100_net_0;
+ clk_100                         <= clk_100_net_1;
+ LOCK_net_1                      <= LOCK_net_0;
+ LOCK                            <= LOCK_net_1;
+ POWER_ON_RESET_N_net_1          <= POWER_ON_RESET_N_net_0;
+ POWER_ON_RESET_N                <= POWER_ON_RESET_N_net_1;
+ FIC_0_AHB_SLAVE_HRDATA_net_0    <= FIC_0_AHB_SLAVE_HRDATA;
+ FIC_0_AHB_S_HRDATA(31 downto 0) <= FIC_0_AHB_SLAVE_HRDATA_net_0;
+ FIC_0_AHB_SLAVE_HREADYOUT_net_0 <= FIC_0_AHB_SLAVE_HREADYOUT;
+ FIC_0_AHB_S_HREADYOUT           <= FIC_0_AHB_SLAVE_HREADYOUT_net_0;
+ FIC_0_AHB_SLAVE_HRESP_net_0     <= FIC_0_AHB_SLAVE_HRESP;
+ FIC_0_AHB_S_HRESP               <= FIC_0_AHB_SLAVE_HRESP_net_0;
+ MSS_RESET_N_M2F_net_1           <= MSS_RESET_N_M2F_net_0;
+ MSS_RESET_N_M2F                 <= MSS_RESET_N_M2F_net_1;
+----------------------------------------------------------------------
+-- Component instances
+----------------------------------------------------------------------
+-- FCCC_C0_0
+FCCC_C0_0 : FCCC_C0
+    port map( 
+        -- Inputs
+        XTLOSC => OSC_C0_0_XTLOSC_CCC_OUT_XTLOSC_CCC,
+        -- Outputs
+        GL0    => clk_100_net_0,
+        LOCK   => LOCK_net_0 
+        );
+-- OSC_C0_0
+OSC_C0_0 : OSC_C0
+    port map( 
+        -- Inputs
+        XTL        => XTL,
+        -- Outputs
+        XTLOSC_O2F => OPEN,
+        XTLOSC_CCC => OSC_C0_0_XTLOSC_CCC_OUT_XTLOSC_CCC 
+        );
+-- SYSRESET_0
+SYSRESET_0 : SYSRESET
+    port map( 
+        -- Inputs
+        DEVRST_N         => DEVRST_N,
+        -- Outputs
+        POWER_ON_RESET_N => POWER_ON_RESET_N_net_0 
+        );
+-- uart_MSS_0
+uart_MSS_0 : uart_MSS
+    port map( 
+        -- Inputs
+        MCCC_CLK_BASE         => clk_100_net_0,
+        MMUART_0_RXD          => MMUART_0_RXD,
+        FIC_0_AHB_S_HADDR     => FIC_0_AHB_S_HADDR,
+        FIC_0_AHB_S_HREADY    => FIC_0_AHB_S_HREADY,
+        FIC_0_AHB_S_HWDATA    => FIC_0_AHB_S_HWDATA,
+        FIC_0_AHB_S_HWRITE    => FIC_0_AHB_S_HWRITE,
+        FIC_0_AHB_S_HSIZE     => FIC_0_AHB_S_HSIZE,
+        FIC_0_AHB_S_HTRANS    => FIC_0_AHB_S_HTRANS,
+        FIC_0_AHB_S_HMASTLOCK => FIC_0_AHB_S_HMASTLOCK,
+        FIC_0_AHB_S_HSEL      => FIC_0_AHB_S_HSEL,
+        M3_RESET_N            => M3_RESET_N,
+        -- Outputs
+        MMUART_0_TXD          => MMUART_0_TXD_net_0,
+        FIC_0_AHB_S_HRDATA    => FIC_0_AHB_SLAVE_HRDATA,
+        FIC_0_AHB_S_HRESP     => FIC_0_AHB_SLAVE_HRESP,
+        FIC_0_AHB_S_HREADYOUT => FIC_0_AHB_SLAVE_HREADYOUT,
+        MSS_RESET_N_M2F       => MSS_RESET_N_M2F_net_0 
+        );
+
+end RTL;