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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
package envm_sim_pkg is
type stdvector_array is array (natural range <>) of std_logic_vector (31 downto 0);
end package;
use work.envm_sim_pkg.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity envm_sim is
generic (
g_bootldr_text_offset : std_logic_vector (31 downto 0);
g_app_text_offset : std_logic_vector (31 downto 0);
g_app_data_offset : std_logic_vector (31 downto 0)
);
port (
clk_i : in std_logic;
rst_i : in std_logic;
bootldr_text_image_i : stdvector_array;
app_text_image_i : stdvector_array;
app_data_image_i : stdvector_array;
apb_psel_i : in std_logic;
apb_pwr_i : in std_logic;
apb_pen_i : in std_logic;
apb_paddr_i : in std_logic_vector(31 downto 0);
apb_pwdat_i : in std_logic_vector(31 downto 0);
apb_prdat_o : out std_logic_vector(31 downto 0);
apb_pready_o : out std_logic; --
apb_pslverr_o : out std_logic
);
end entity envm_sim;
architecture rtl of envm_sim is
begin
process (clk_i)
begin
if rising_edge (clk_i) then
apb_prdat_o <= (others => '0');
apb_pready_o <= '0';
if (apb_psel_i = '1' and apb_pen_i = '1') then
apb_pready_o <= '1';
if (apb_paddr_i (31 downto 16) = g_app_text_offset (31 downto 16)) then
apb_prdat_o <= app_text_image_i (to_integer(unsigned(apb_paddr_i(31 downto 2))) - to_integer(unsigned(g_app_text_offset(31 downto 2))));
elsif (apb_paddr_i (31 downto 16) = g_app_data_offset (31 downto 16)) then
apb_prdat_o <= app_data_image_i(to_integer(unsigned(apb_paddr_i(31 downto 2))) - to_integer(unsigned(g_app_data_offset(31 downto 2))));
elsif (apb_paddr_i (31 downto 16) = g_bootldr_text_offset (31 downto 16)) then
apb_prdat_o <= bootldr_text_image_i(to_integer(unsigned(apb_paddr_i (31 downto 2))) - to_integer(unsigned(g_bootldr_text_offset(31 downto 2))));
elsif (apb_paddr_i = x"60080120") then -- busy bit check
apb_prdat_o <= x"00000001";
-- else
-- report "invalid address" severity failure;
end if;
end if;
end if;
end process;
end architecture;