1st prototype of the HiCCE

9b6ea8ba · Kasun Sameera Mannatunga · ea0ebb4b · 9b6ea8ba · 9b6ea8ba · 9b6ea8ba
Commit 9b6ea8ba authored May 24, 2020 by Kasun Sameera Mannatunga
50 changed files
--- a/HiCCE-128-FMC version 1/Gerbers/NEURAL_FMC-12.AST
+++ b/HiCCE-128-FMC version 1/Gerbers/NEURAL_FMC-12.AST
--- a/HiCCE-128-FMC version 1/Gerbers/NEURAL_FMC-12.BOT
+++ b/HiCCE-128-FMC version 1/Gerbers/NEURAL_FMC-12.BOT
--- a/HiCCE-128-FMC version 1/Gerbers/NEURAL_FMC-12.DRD
+++ b/HiCCE-128-FMC version 1/Gerbers/NEURAL_FMC-12.DRD
--- a/HiCCE-128-FMC version 1/Gerbers/NEURAL_FMC-12.DTS
+++ b/HiCCE-128-FMC version 1/Gerbers/NEURAL_FMC-12.DTS
+*********************************************************************************************************************
+*                                                                                                                   *
+* DRILL TAPE SUMMARY REPORT                                                                                         *
+*                                                                                                                   *
+* O:\PROJECTS\MAGNASCO LAB - ROCKEFELLER U\REL442 - FPGA MEZZANINE CARD (FMC)\ORCAD\LAYOUT\BOARD\NEURAL_FMC-12.MAX  *
+* Tue Jun 26 11:16:26 2012                                                                                          *
+*                                                                                                                   *
+*********************************************************************************************************************
+
+TOOL     SIZE     QUANTITY FEED     SPEED    
+---------------------------------------------
+T1       120      526      200      100                                                                                 
+T2       150      130      200      100                                                                                 
+T3       280      4        200      100                                                                                 
+T4       380      16       200      100                                                                                 
+T5       400      4        200      100                                                                                 
+T6       420      4        200      100                                                                                 
+T7       512      2        200      100                                                                                 
+T8       750      4        200      100                                                                                 
+T9       1063     6        200      100                                                                                 
--- a/HiCCE-128-FMC version 1/Gerbers/NEURAL_FMC-12.FAB
+++ b/HiCCE-128-FMC version 1/Gerbers/NEURAL_FMC-12.FAB
--- a/HiCCE-128-FMC version 1/Gerbers/NEURAL_FMC-12.GND
+++ b/HiCCE-128-FMC version 1/Gerbers/NEURAL_FMC-12.GND
--- a/HiCCE-128-FMC version 1/Gerbers/NEURAL_FMC-12.GTD
+++ b/HiCCE-128-FMC version 1/Gerbers/NEURAL_FMC-12.GTD
+{Program	GerbTool for Layout
+	{Version	8.0}
+	{Created	Tue Jun 26 11:16:19 2012}
+}
+{Environment
+	{FilesPath  O:\PROJECTS\MAGNASCO LAB - ROCKEFELLER U\REL442 - FPGA MEZZANINE CARD (FMC)\ORCAD\LAYOUT\BOARD}
+}
+{Layers
+	{Layer  1
+		{File        NEURAL_FMC-12.TOP}
+		{LyrName     -}
+		{ApList      }
+		{Visibility  On}
+		{FlashColor  Green}
+		{DrawColor   Green}
+		{Type        Top}
+	}
+	{Layer  2
+		{File        NEURAL_FMC-12.GND}
+		{LyrName     -}
+		{ApList      }
+		{Visibility  On}
+		{FlashColor  gray50}
+		{DrawColor   gray50}
+		{Type        Plane}
+	}
+	{Layer  3
+		{File        NEURAL_FMC-12.PWR}
+		{LyrName     -}
+		{ApList      }
+		{Visibility  On}
+		{FlashColor  col8}
+		{DrawColor   col8}
+		{Type        Plane}
+	}
+	{Layer  4
+		{File        NEURAL_FMC-12.BOT}
+		{LyrName     -}
+		{ApList      }
+		{Visibility  On}
+		{FlashColor  Red}
+		{DrawColor   Red}
+		{Type        Bottom}
+	}
+	{Layer  5
+		{File        NEURAL_FMC-12.SMT}
+		{LyrName     -}
+		{ApList      }
+		{Visibility  On}
+		{FlashColor  Green}
+		{DrawColor   Green}
+		{Type        Other}
+	}
+	{Layer  6
+		{File        NEURAL_FMC-12.SMB}
+		{LyrName     -}
+		{ApList      }
+		{Visibility  On}
+		{FlashColor  vga16yellow}
+		{DrawColor   vga16yellow}
+		{Type        Other}
+	}
+	{Layer  7
+		{File        NEURAL_FMC-12.SST}
+		{LyrName     -}
+		{ApList      }
+		{Visibility  On}
+		{FlashColor  White}
+		{DrawColor   White}
+		{Type        Other}
+	}
+	{Layer  8
+		{File        NEURAL_FMC-12.AST}
+		{LyrName     -}
+		{ApList      }
+		{Visibility  On}
+		{FlashColor  Green}
+		{DrawColor   Green}
+		{Type        Other}
+	}
+	{Layer  9
+		{File        NEURAL_FMC-12.DRD}
+		{LyrName     -}
+		{ApList      }
+		{Visibility  On}
+		{FlashColor  Red}
+		{DrawColor   Red}
+		{Type        Other}
+	}
+	{Layer  10
+		{File        NEURAL_FMC-12.FAB}
+		{LyrName     -}
+		{ApList      }
+		{Visibility  On}
+		{FlashColor  Green}
+		{DrawColor   Green}
+		{Type        Other}
+	}
+}
+{Format Gerber
+	{Dialect           RS274X}
+	{m.n               3.4}
+	{Mode              Absolute}
+	{ZeroSuppression   Leading}
+	{Terminator        0x2a, 0xD, 0xA}
+	{Metric            No}
+	{Modal             No}
+	{UserData          Yes}
+	{Nets              No}
+	{Gcmds             Yes}
+	{CharSet           ASCII}
+	{Arcs360           No}
+	{ArcsModal         Yes}
+	{HonorCrLf         No}
+	{Comments          Yes}
+	{Flags             0}
+}
--- a/HiCCE-128-FMC version 1/Gerbers/NEURAL_FMC-12.LIS
+++ b/HiCCE-128-FMC version 1/Gerbers/NEURAL_FMC-12.LIS
--- a/HiCCE-128-FMC version 1/Gerbers/NEURAL_FMC-12.PWR
+++ b/HiCCE-128-FMC version 1/Gerbers/NEURAL_FMC-12.PWR
--- a/HiCCE-128-FMC version 1/Gerbers/NEURAL_FMC-12.SMB
+++ b/HiCCE-128-FMC version 1/Gerbers/NEURAL_FMC-12.SMB
--- a/HiCCE-128-FMC version 1/Gerbers/NEURAL_FMC-12.SMT
+++ b/HiCCE-128-FMC version 1/Gerbers/NEURAL_FMC-12.SMT
--- a/HiCCE-128-FMC version 1/Gerbers/NEURAL_FMC-12.SST
+++ b/HiCCE-128-FMC version 1/Gerbers/NEURAL_FMC-12.SST
--- a/HiCCE-128-FMC version 1/Gerbers/NEURAL_FMC-12.TOP
+++ b/HiCCE-128-FMC version 1/Gerbers/NEURAL_FMC-12.TOP
--- a/HiCCE-128-FMC version 1/Gerbers/NEURAL_FMC_0.DBK
+++ b/HiCCE-128-FMC version 1/Gerbers/NEURAL_FMC_0.DBK
--- a/HiCCE-128-FMC version 1/Gerbers/ROUTEBOARD.DO
+++ b/HiCCE-128-FMC version 1/Gerbers/ROUTEBOARD.DO
+select all nets
+grid wire 0.000000 (direction x) (offset 0.000000)
+grid wire 0.000000 (direction Y) (offset 0.000000)
+grid via 0.000000 (direction x) (offset 0.000000)
+grid via 0.000000 (direction Y) (offset 0.000000)
+set route_diagonal 0
+cost via -1
+limit outside -1
+
+Clean 0
+
+Clean 0
+
+Clean 0
+
+Clean 0
+
+Clean 0
+
+Clean 0
+
+Clean 0
+
+Clean 0
+
+Clean 0
+
+Clean 0
+
+write routes $/SpecctraWithinLayout.rte
+quit -c
\ No newline at end of file
--- a/HiCCE-128-FMC version 1/Layout/Allegro 17.2/24AA64TIMC.txt
+++ b/HiCCE-128-FMC version 1/Layout/Allegro 17.2/24AA64TIMC.txt
+(DEVICE DESCRIPTION FILE: 24AA64TIMC)
+PACKAGE MSOP8
+PACKAGEPROP VALUE '24AA64T-I/MC'
+PACKAGEPROP HEIGHT '1.0000000'
+CLASS IC
+PINCOUNT 8
+END
--- a/HiCCE-128-FMC version 1/Layout/Allegro 17.2/AD7982.txt
+++ b/HiCCE-128-FMC version 1/Layout/Allegro 17.2/AD7982.txt
+(DEVICE DESCRIPTION FILE: AD7982)
+PACKAGE MSOP10
+PACKAGEPROP HEIGHT '1.0000000'
+CLASS IC
+PINCOUNT 10
+END
--- a/HiCCE-128-FMC version 1/Layout/Allegro 17.2/ADP171025.txt
+++ b/HiCCE-128-FMC version 1/Layout/Allegro 17.2/ADP171025.txt
+(DEVICE DESCRIPTION FILE: ADP171025)
+PACKAGE TSOT5
+PACKAGEPROP HEIGHT '1.0000000'
+CLASS IC
+PINCOUNT 5
+END
--- a/HiCCE-128-FMC version 1/Layout/Allegro 17.2/ADR38125VREF.txt
+++ b/HiCCE-128-FMC version 1/Layout/Allegro 17.2/ADR38125VREF.txt
+(DEVICE DESCRIPTION FILE: ADR38125VREF)
+PACKAGE SOT23_123
+PACKAGEPROP HEIGHT '1.0000000'
+CLASS IC
+PINCOUNT 3
+END
--- a/HiCCE-128-FMC version 1/Layout/Allegro 17.2/CAPACITOR_-_NON_POLARIZED.txt
+++ b/HiCCE-128-FMC version 1/Layout/Allegro 17.2/CAPACITOR_-_NON_POLARIZED.txt
+(DEVICE DESCRIPTION FILE: CAPACITOR_-_NON_POLARIZED)
+PACKAGE SMC0603REV2
+PACKAGEPROP VALUE '100nF'
+PACKAGEPROP HEIGHT '1.0000000'
+CLASS IC
+PINCOUNT 2
+END
--- a/HiCCE-128-FMC version 1/Layout/Allegro 17.2/CAP_NP.txt
+++ b/HiCCE-128-FMC version 1/Layout/Allegro 17.2/CAP_NP.txt
+(DEVICE DESCRIPTION FILE: CAP_NP)
+PACKAGE SMC0603REV2
+PACKAGEPROP HEIGHT '1.0000000'
+PACKAGEPROP ALT_SYMBOLS '(SMC0603REV1)'
+CLASS IC
+PINCOUNT 2
+END
--- a/HiCCE-128-FMC version 1/Layout/Allegro 17.2/CON10_0.txt
+++ b/HiCCE-128-FMC version 1/Layout/Allegro 17.2/CON10_0.txt
+(DEVICE DESCRIPTION FILE: CON10_0)
+PACKAGE THRUHOLE100PITCH025SQRE4POSREV2
+PACKAGEPROP VALUE '4-pin con'
+PACKAGEPROP HEIGHT '1.0000000'
+CLASS IC
+PINCOUNT 4
+END
--- a/HiCCE-128-FMC version 1/Layout/Allegro 17.2/FMC_project.llb
+++ b/HiCCE-128-FMC version 1/Layout/Allegro 17.2/FMC_project.llb
--- a/HiCCE-128-FMC version 1/Layout/Allegro 17.2/JUMPER_0.txt
+++ b/HiCCE-128-FMC version 1/Layout/Allegro 17.2/JUMPER_0.txt
+(DEVICE DESCRIPTION FILE: JUMPER_0)
+PACKAGE JUMPER100
+PACKAGEPROP HEIGHT '1.0000000'
+CLASS IC
+PINCOUNT 2
+END
--- a/HiCCE-128-FMC version 1/Layout/Allegro 17.2/LED_0.txt
+++ b/HiCCE-128-FMC version 1/Layout/Allegro 17.2/LED_0.txt
+(DEVICE DESCRIPTION FILE: LED_0)
+PACKAGE MISCELLANOUSLED
+PACKAGEPROP HEIGHT '1.0000000'
+CLASS IC
+PINCOUNT 4
+END
--- a/HiCCE-128-FMC version 1/Layout/Allegro 17.2/MAX5424.txt
+++ b/HiCCE-128-FMC version 1/Layout/Allegro 17.2/MAX5424.txt
+(DEVICE DESCRIPTION FILE: MAX5424)
+PACKAGE QFN_TDFN_8
+PACKAGEPROP HEIGHT '1.0000000'
+CLASS IC
+PINCOUNT 8
+END
--- a/HiCCE-128-FMC version 1/Layout/Allegro 17.2/MAX5424_0.txt
+++ b/HiCCE-128-FMC version 1/Layout/Allegro 17.2/MAX5424_0.txt
+(DEVICE DESCRIPTION FILE: MAX5424_0)
+PACKAGE QFN_TDFN_8
+PACKAGEPROP HEIGHT '1.0000000'
+CLASS IC
+PINCOUNT 8
+END
--- a/HiCCE-128-FMC version 1/Layout/Allegro 17.2/MOUNTING_HOLE_0.txt
+++ b/HiCCE-128-FMC version 1/Layout/Allegro 17.2/MOUNTING_HOLE_0.txt
+(DEVICE DESCRIPTION FILE: MOUNTING_HOLE_0)
+PACKAGE MOUNT_HOLE_2P7_REV2
+PACKAGEPROP HEIGHT '1.0000000'
+PACKAGEPROP ALT_SYMBOLS '(MOUNT_HOLE_2P7_REV1;MOUNT_HOLE_2P7_REV3;MOUNT_HOLE_2P7_REV4;MOUNT_HOLE_2P7_REV6;MOUNT_HOLE_2P7_REV7)'
+CLASS IC
+PINCOUNT 1
+END
--- a/HiCCE-128-FMC version 1/Layout/Allegro 17.2/N-MOSFET-D_1G_2S_3D.txt
+++ b/HiCCE-128-FMC version 1/Layout/Allegro 17.2/N-MOSFET-D_1G_2S_3D.txt
+(DEVICE DESCRIPTION FILE: N-MOSFET-D_1G_2S_3D)
+PACKAGE SOT23_123
+PACKAGEPROP HEIGHT '1.0000000'
+CLASS IC
+PINCOUNT 3
+END
--- a/HiCCE-128-FMC version 1/Layout/Allegro 17.2/NEURAL_FMC-12.MAX
+++ b/HiCCE-128-FMC version 1/Layout/Allegro 17.2/NEURAL_FMC-12.MAX
--- a/HiCCE-128-FMC version 1/Layout/Allegro 17.2/NEURAL_FMC-12.brd
+++ b/HiCCE-128-FMC version 1/Layout/Allegro 17.2/NEURAL_FMC-12.brd
--- a/HiCCE-128-FMC version 1/Layout/Allegro 17.2/NEURAL_FMC-12.log
+++ b/HiCCE-128-FMC version 1/Layout/Allegro 17.2/NEURAL_FMC-12.log
--- a/HiCCE-128-FMC version 1/Layout/Allegro 17.2/NEURAL_FMC-12.txt
+++ b/HiCCE-128-FMC version 1/Layout/Allegro 17.2/NEURAL_FMC-12.txt
--- a/HiCCE-128-FMC version 1/Layout/Allegro 17.2/OMNETICS-A79023-001_1.txt
+++ b/HiCCE-128-FMC version 1/Layout/Allegro 17.2/OMNETICS-A79023-001_1.txt
+(DEVICE DESCRIPTION FILE: OMNETICS-A79023-001_1)
+PACKAGE OMNETICSBILOBE65PIN
+PACKAGEPROP HEIGHT '1.0000000'
+CLASS IC
+PINCOUNT 67
+PINORDER OMNETICS-A79023-001_1 1 2 3 4 5 6 7 8 9 10,
+	 11 12 13 14 15 16 17 18 19 20 21,
+	 22 23 24 25 26 27 28 29 30 31 32,
+	 33 34 35 36 37 38 39 40 41 42 43,
+	 44 45 46 47 48 49 50 51 52 53 54,
+	 55 56 57 58 59 60 61 62 63 64 65,
+	 HOLE1 HOLE2
+FUNCTION G1 OMNETICS-A79023-001_1 1 2 3 4 5 6 7 8 9 10,
+	 11 12 13 14 15 16 17 18 19 20 21,
+	 22 23 24 25 26 27 28 29 30 31 32,
+	 33 34 35 36 37 38 39 40 41 42 43,
+	 44 45 46 47 48 49 50 51 52 53 54,
+	 55 56 57 58 59 60 61 62 63 64 65,
+	 HOLE1 HOLE2
+END
--- a/HiCCE-128-FMC version 1/Layout/Allegro 17.2/R.txt
+++ b/HiCCE-128-FMC version 1/Layout/Allegro 17.2/R.txt
+(DEVICE DESCRIPTION FILE: R)
+PACKAGE R_0805
+PACKAGEPROP VALUE '511'
+PACKAGEPROP HEIGHT '1.0000000'
+CLASS IC
+PINCOUNT 2
+END
--- a/HiCCE-128-FMC version 1/Layout/Allegro 17.2/RHA2132_1.txt
+++ b/HiCCE-128-FMC version 1/Layout/Allegro 17.2/RHA2132_1.txt
+(DEVICE DESCRIPTION FILE: RHA2132_1)
+PACKAGE QFN_56_NOCENTER_REV1
+PACKAGEPROP HEIGHT '1.0000000'
+CLASS IC
+PINCOUNT 56
+END
--- a/HiCCE-128-FMC version 1/Layout/Allegro 17.2/RHA2132_2.txt
+++ b/HiCCE-128-FMC version 1/Layout/Allegro 17.2/RHA2132_2.txt
+(DEVICE DESCRIPTION FILE: RHA2132_2)
+PACKAGE QFN_56_NOCENTER_REV3
+PACKAGEPROP HEIGHT '1.0000000'
+CLASS IC
+PINCOUNT 56
+END
--- a/HiCCE-128-FMC version 1/Layout/Allegro 17.2/RHA2132_3.txt
+++ b/HiCCE-128-FMC version 1/Layout/Allegro 17.2/RHA2132_3.txt
+(DEVICE DESCRIPTION FILE: RHA2132_3)
+PACKAGE QFN_56_NOCENTER_REV2
+PACKAGEPROP HEIGHT '1.0000000'
+PACKAGEPROP ALT_SYMBOLS '(QFN_56_NOCENTER)'
+CLASS IC
+PINCOUNT 56
+END
--- a/HiCCE-128-FMC version 1/Layout/Allegro 17.2/VITA57_LPC.txt
+++ b/HiCCE-128-FMC version 1/Layout/Allegro 17.2/VITA57_LPC.txt
+(DEVICE DESCRIPTION FILE: VITA57_LPC)
+PACKAGE LOWPINCNT_160PINS_REV1
+PACKAGEPROP HEIGHT '1.0000000'
+CLASS IC
+PINCOUNT 162
+PINORDER VITA57_LPC H1 HOLE1 HOLE2 H2 H3 H4 H5 H6 H7 H8,
+	 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19,
+	 H20 H21 H22 H23 H24 H25 H26 H27 H28 H29 H30,
+	 H31 H32 H33 H34 H35 H36 H37 H38 H39 H40 G1,
+	 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12,
+	 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 G23,
+	 G24 G25 G26 G27 G28 G29 G30 G31 G32 G33 G34,
+	 G35 G36 G37 G38 G39 G40 D1 D2 D3 D4 D5,
+	 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16,
+	 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27,
+	 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38,
+	 D39 D40 C1 C2 C3 C4 C5 C6 C7 C8 C9,
+	 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20,
+	 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31,
+	 C32 C33 C34 C35 C36 C37 C38 C39 C40
+FUNCTION G1 VITA57_LPC H1 HOLE1 HOLE2 H2 H3 H4 H5 H6 H7 H8,
+	 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19,
+	 H20 H21 H22 H23 H24 H25 H26 H27 H28 H29 H30,
+	 H31 H32 H33 H34 H35 H36 H37 H38 H39 H40 G1,
+	 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12,
+	 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 G23,
+	 G24 G25 G26 G27 G28 G29 G30 G31 G32 G33 G34,
+	 G35 G36 G37 G38 G39 G40 D1 D2 D3 D4 D5,
+	 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16,
+	 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27,
+	 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38,
+	 D39 D40 C1 C2 C3 C4 C5 C6 C7 C8 C9,
+	 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20,
+	 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31,
+	 C32 C33 C34 C35 C36 C37 C38 C39 C40
+END
--- a/HiCCE-128-FMC version 1/Layout/Allegro 17.2/devices.map
+++ b/HiCCE-128-FMC version 1/Layout/Allegro 17.2/devices.map
+'24AA64T-I/MC' '24AA64TIMC.txt';
+'ADR381_2.5VREF' 'ADR38125VREF.txt';
+'ADP1710-2.5' 'ADP171025.txt';
--- a/HiCCE-128-FMC version 1/Layout/Allegro 17.2/netin.log
+++ b/HiCCE-128-FMC version 1/Layout/Allegro 17.2/netin.log
--- a/HiCCE-128-FMC version 1/Layout/Allegro 17.2/stderror.log
+++ b/HiCCE-128-FMC version 1/Layout/Allegro 17.2/stderror.log
--- a/HiCCE-128-FMC version 1/Layout/OrCAD 16.6/FMC_project.llb
+++ b/HiCCE-128-FMC version 1/Layout/OrCAD 16.6/FMC_project.llb
--- a/HiCCE-128-FMC version 1/Layout/OrCAD 16.6/NEURAL_FMC-12.MAX
+++ b/HiCCE-128-FMC version 1/Layout/OrCAD 16.6/NEURAL_FMC-12.MAX
--- a/HiCCE-128-FMC version 1/README.md
+++ b/HiCCE-128-FMC version 1/README.md
+# HiCCE-128-FMC version 1
+First prototype of the HiCCE project.
+
+<p align="center">
+  <img src="../Images/HiCCEv1_image.png" width="300" > <br /> <br />
+</p>
+
+
+This folder contains schematics, layout, and gerbers of the first design. the hardware project has been designed using OrCAD 16.6 PCB design software.
--- a/HiCCE-128-FMC version 1/Schematic/NEURAL_FMC.DRC
+++ b/HiCCE-128-FMC version 1/Schematic/NEURAL_FMC.DRC
+
+Checking Pins and Pin Connections
+
+--------------------------------------------------
+Checking Schematic: NeuralFMC
+--------------------------------------------------
+Checking Electrical Rules 
+
+Checking for Unconnected Nets
+
+Checking Off-Page Connections
+
+Checking for Invalid References
+
+Checking for Duplicate References
+
+Check Bus width mismatch
--- a/HiCCE-128-FMC version 1/Schematic/NEURAL_FMC.DSN
+++ b/HiCCE-128-FMC version 1/Schematic/NEURAL_FMC.DSN
--- a/HiCCE-128-FMC version 1/Schematic/NEURAL_FMC.OPJ_LOG.txt
+++ b/HiCCE-128-FMC version 1/Schematic/NEURAL_FMC.OPJ_LOG.txt
--- a/HiCCE-128-FMC version 1/Schematic/layout.log
+++ b/HiCCE-128-FMC version 1/Schematic/layout.log
--- a/HiCCE-128-FMC version 1/Schematic/neural_fmc.opj
+++ b/HiCCE-128-FMC version 1/Schematic/neural_fmc.opj