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Hdlmake
Commits
01dda1ab
Commit
01dda1ab
authored
Oct 31, 2019
by
Tristan Gingold
Browse files
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Browse Files
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Plain Diff
makefilevsim.py: remove extra blanks.
parent
ff44c62d
Show whitespace changes
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Showing
24 changed files
with
25 additions
and
218 deletions
+25
-218
makefilevsim.py
hdlmake/tools/makefilevsim.py
+2
-2
Makefile.ref
testsuite/002msim/Makefile.ref
+1
-2
Makefile.ref
testsuite/003msim/Makefile.ref
+1
-2
Makefile.ref
testsuite/004msim/Makefile.ref
+1
-2
Makefile
testsuite/011xfail/Makefile
+0
-172
Makefile.ref
testsuite/017riviera/Makefile.ref
+1
-2
Makefile.ref
testsuite/024vlog_parser/Makefile.ref
+1
-2
Makefile.ref
testsuite/025vlog_parser/Makefile.ref
+1
-2
Makefile.ref
testsuite/027vhdl_parser/Makefile.ref
+1
-2
Makefile
testsuite/032manifest_vars/Makefile
+1
-2
Makefile.ref
testsuite/043local_fetch/Makefile.ref
+1
-2
Makefile.ref
testsuite/044files_dir/Makefile.ref
+1
-2
Makefile.ref
testsuite/045incl_makefile/Makefile.ref
+1
-2
Makefile.ref
testsuite/046incl_makefiles/Makefile.ref
+1
-2
Makefile.ref
testsuite/052svlog_parser/Makefile.ref
+1
-2
Makefile.ref
testsuite/057msim_windows/Makefile.ref
+1
-2
Makefile.ref
testsuite/076extra_modules/Makefile.ref
+1
-2
Makefile.ref
testsuite/079err_vlg_macro/Makefile.ref
+1
-2
Makefile.ref
testsuite/081vlog_ifdef_elsif_else/Makefile.ref
+1
-2
Makefile.ref
testsuite/087many_modules/Makefile.ref
+1
-2
Makefile.ref
testsuite/088bad_file_abs/Makefile.ref
+1
-2
Makefile.ref
testsuite/091library/Makefile.ref
+2
-4
Makefile.ref
testsuite/093multi_sat/Makefile.ref
+1
-2
test_all.py
testsuite/test_all.py
+1
-0
No files found.
hdlmake/tools/makefilevsim.py
View file @
01dda1ab
...
...
@@ -121,9 +121,9 @@ class MakefileVsim(MakefileSim):
self
.
write
(
__create_copy_rule
(
filename
,
filesource
))
for
lib
in
libs
:
self
.
write
(
lib
+
shell
.
makefile_slash_char
()
+
"."
+
lib
+
":
\n
"
)
self
.
write
(
"
\t
(vlib {0} && vmap $(VMAP_FLAGS) {0} && {1} {0}{2}.{0}
)"
.
format
(
self
.
write
(
"
\t
(vlib {0} && vmap $(VMAP_FLAGS) {0} && {1} {0}{2}.{0})"
.
format
(
lib
,
shell
.
touch_command
(),
shell
.
makefile_slash_char
()))
self
.
write
(
"
|| {} {}
\n
\n\n
"
.
format
(
shell
.
del_command
(),
lib
))
self
.
write
(
"
|| {} {}
\n\n
"
.
format
(
shell
.
del_command
(),
lib
))
# rules for all _primary.dat files for sv
for
vlog
in
fileset
.
filter
(
VerilogFile
)
.
sort
():
self
.
write
(
"
%
s:
%
s"
%
(
os
.
path
.
join
(
...
...
testsuite/002msim/Makefile.ref
View file @
01dda1ab
...
...
@@ -31,8 +31,7 @@ $(VHDL_OBJ): $(LIB_IND) modelsim.ini
modelsim.ini
:
$(MODELSIM_INI_PATH)/modelsim.ini
cp
$<
.
2>&1
work/.work
:
(
vlib work
&&
vmap
$(VMAP_FLAGS)
work
&&
touch
work/.work
)||
rm
-rf
work
(
vlib work
&&
vmap
$(VMAP_FLAGS)
work
&&
touch
work/.work
)
||
rm
-rf
work
work/gate/.gate_vhdl
:
../files/gate.vhdl
vcom
$(VCOM_FLAGS)
-work
work
$<
...
...
testsuite/003msim/Makefile.ref
View file @
01dda1ab
...
...
@@ -31,8 +31,7 @@ $(VHDL_OBJ): $(LIB_IND) modelsim.ini
modelsim.ini
:
$(MODELSIM_INI_PATH)/modelsim.ini
cp
$<
.
2>&1
work/.work
:
(
vlib work
&&
vmap
$(VMAP_FLAGS)
work
&&
touch
work/.work
)||
rm
-rf
work
(
vlib work
&&
vmap
$(VMAP_FLAGS)
work
&&
touch
work/.work
)
||
rm
-rf
work
work/gate/.gate_vhdl
:
../files/gate.vhdl
vcom
$(VCOM_FLAGS)
-work
work
$<
...
...
testsuite/004msim/Makefile.ref
View file @
01dda1ab
...
...
@@ -31,8 +31,7 @@ $(VHDL_OBJ): $(LIB_IND) modelsim.ini
modelsim.ini
:
$(MODELSIM_INI_PATH)/modelsim.ini
cp
$<
.
2>&1
work/.work
:
(
vlib work
&&
vmap
$(VMAP_FLAGS)
work
&&
touch
work/.work
)||
rm
-rf
work
(
vlib work
&&
vmap
$(VMAP_FLAGS)
work
&&
touch
work/.work
)
||
rm
-rf
work
work/gate/.gate_vhdl
:
../files/gate.vhdl
vcom
$(VCOM_FLAGS)
-work
work
$<
...
...
testsuite/011xfail/Makefile
deleted
100644 → 0
View file @
ff44c62d
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
TOP_MODULE
:=
gate
PROJECT
:=
gate
PROJECT_FILE
:=
$(PROJECT)
.xise
TOOL_PATH
:=
TCL_INTERPRETER
:=
xtclsh
ifneq
($(strip
$(TOOL_PATH)),)
TCL_INTERPRETER
:=
$(TOOL_PATH)
/
$(TCL_INTERPRETER)
endif
SYN_FAMILY
:=
Spartan6
SYN_DEVICE
:=
xc6slx45t
SYN_PACKAGE
:=
fgg484
SYN_GRADE
:=
-3
TCL_CREATE
:=
project new
$(PROJECT_FILE)
TCL_OPEN
:=
project open
$(PROJECT_FILE)
TCL_SAVE
:=
project save
TCL_CLOSE
:=
project close
ifneq
($(wildcard
$(PROJECT_FILE)),)
TCL_CREATE
:=
$(TCL_OPEN)
endif
#target for performing local synthesis
all
:
bitstream
SOURCES_VHDLFile
:=
\
../files/gate.vhdl
files.tcl
:
@
$
(
foreach sourcefile,
$(SOURCES_VHDLFile)
,
echo
"xfile add
$(sourcefile)
"
>>
$@
&
)
SYN_PRE_PROJECT_CMD
:=
SYN_POST_PROJECT_CMD
:=
SYN_PRE_SYNTHESIZE_CMD
:=
SYN_POST_SYNTHESIZE_CMD
:=
SYN_PRE_TRANSLATE_CMD
:=
SYN_POST_TRANSLATE_CMD
:=
SYN_PRE_MAP_CMD
:=
SYN_POST_MAP_CMD
:=
SYN_PRE_PAR_CMD
:=
SYN_POST_PAR_CMD
:=
SYN_PRE_BITSTREAM_CMD
:=
SYN_POST_BITSTREAM_CMD
:=
project.tcl
:
echo
$(TCL_CREATE)
>>
$@
echo
xfile remove
[
search
\*
-type
file]
>>
$@
echo source
files.tcl
>>
$@
echo
project
set
\"
family
\"
\"
$(SYN_FAMILY)
\"
>>
$@
echo
project
set
\"
device
\"
\"
$(SYN_DEVICE)
\"
>>
$@
echo
project
set
\"
package
\"
\"
$(SYN_PACKAGE)
\"
>>
$@
echo
project
set
\"
speed
\"
\"
$(SYN_GRADE)
\"
>>
$@
echo
project
set
\"
Manual Implementation Compile Order
\"
\"
false
\"
>>
$@
echo
project
set
\"
Auto Implementation Top
\"
\"
false
\"
>>
$@
echo
project
set
\"
Create Binary Configuration File
\"
\"
true
\"
>>
$@
echo set
compile_directory
.
>>
$@
echo
project
set
top
$(TOP_MODULE)
>>
$@
echo
$(TCL_SAVE)
>>
$@
echo
$(TCL_CLOSE)
>>
$@
project
:
files.tcl project.tcl
$(SYN_PRE_PROJECT_CMD)
$(TCL_INTERPRETER)
$@
.tcl
$(SYN_POST_PROJECT_CMD)
touch
$@
synthesize.tcl
:
echo
$(TCL_OPEN)
>>
$@
echo set
process
{
Synthesize - XST
}
>>
$@
echo
process run
'$$'
process
>>
$@
echo set
result
[
process get
'$$'
process status]
>>
$@
echo
if
{
'$$'
result
==
\"
errors
\"
}
{
>>
$@
echo exit
1
>>
$@
echo
}
>>
$@
echo
$(TCL_SAVE)
>>
$@
echo
$(TCL_CLOSE)
>>
$@
synthesize
:
project synthesize.tcl
$(SYN_PRE_SYNTHESIZE_CMD)
$(TCL_INTERPRETER)
$@
.tcl
$(SYN_POST_SYNTHESIZE_CMD)
touch
$@
translate.tcl
:
echo
$(TCL_OPEN)
>>
$@
echo set
process
{
Translate
}
>>
$@
echo
process run
'$$'
process
>>
$@
echo set
result
[
process get
'$$'
process status]
>>
$@
echo
if
{
'$$'
result
==
\"
errors
\"
}
{
>>
$@
echo exit
1
>>
$@
echo
}
>>
$@
echo
$(TCL_SAVE)
>>
$@
echo
$(TCL_CLOSE)
>>
$@
translate
:
synthesize translate.tcl
$(SYN_PRE_TRANSLATE_CMD)
$(TCL_INTERPRETER)
$@
.tcl
$(SYN_POST_TRANSLATE_CMD)
touch
$@
map.tcl
:
echo
$(TCL_OPEN)
>>
$@
echo set
process
{
Map
}
>>
$@
echo
process run
'$$'
process
>>
$@
echo set
result
[
process get
'$$'
process status]
>>
$@
echo
if
{
'$$'
result
==
\"
errors
\"
}
{
>>
$@
echo exit
1
>>
$@
echo
}
>>
$@
echo
$(TCL_SAVE)
>>
$@
echo
$(TCL_CLOSE)
>>
$@
map
:
translate map.tcl
$(SYN_PRE_MAP_CMD)
$(TCL_INTERPRETER)
$@
.tcl
$(SYN_POST_MAP_CMD)
touch
$@
par.tcl
:
echo
$(TCL_OPEN)
>>
$@
echo set
process
{
Place
'&'
Route
}
>>
$@
echo
process run
'$$'
process
>>
$@
echo set
result
[
process get
'$$'
process status]
>>
$@
echo
if
{
'$$'
result
==
\"
errors
\"
}
{
>>
$@
echo exit
1
>>
$@
echo
}
>>
$@
echo
$(TCL_SAVE)
>>
$@
echo
$(TCL_CLOSE)
>>
$@
par
:
map par.tcl
$(SYN_PRE_PAR_CMD)
$(TCL_INTERPRETER)
$@
.tcl
$(SYN_POST_PAR_CMD)
touch
$@
bitstream.tcl
:
echo
$(TCL_OPEN)
>>
$@
echo set
process
{
Generate Programming File
}
>>
$@
echo
process run
'$$'
process
>>
$@
echo set
result
[
process get
'$$'
process status]
>>
$@
echo
if
{
'$$'
result
==
\"
errors
\"
}
{
>>
$@
echo exit
1
>>
$@
echo
}
>>
$@
echo
$(TCL_SAVE)
>>
$@
echo
$(TCL_CLOSE)
>>
$@
bitstream
:
par bitstream.tcl
$(SYN_PRE_BITSTREAM_CMD)
$(TCL_INTERPRETER)
$@
.tcl
$(SYN_POST_BITSTREAM_CMD)
touch
$@
CLEAN_TARGETS
:=
$(LIBS)
xst xlnx_auto_0_xdb iseconfig _xmsgs _ngo
*
.b
*
_summary.html
*
.bld
*
.cmd_log
*
.drc
*
.lso
*
.ncd
*
.ngc
*
.ngd
*
.ngr
*
.pad
*
.par
*
.pcf
*
.prj
*
.ptwx
*
.stx
*
.syr
*
.twr
*
.twx
*
.gise
*
.gise
*
.bgn
*
.unroutes
*
.ut
*
.xpi
*
.xst
*
.xise
*
.xwbt
*
_envsettings.html
*
_guide.ncd
*
_map.map
*
_map.mrp
*
_map.ncd
*
_map.ngm
*
_map.xrpt
*
_ngdbuild.xrpt
*
_pad.csv
*
_pad.txt
*
_par.xrpt
*
_summary.xml
*
_usage.xml
*
_xst.xrpt usage_statistics_webtalk.html webtalk.log par_usage_statistics.html webtalk_pn.xml
clean
:
rm
-rf
$(CLEAN_TARGETS)
rm
-rf
project synthesize translate map par bitstream
rm
-rf
project.tcl synthesize.tcl translate.tcl map.tcl par.tcl bitstream.tcl files.tcl
mrproper
:
clean
rm
-rf
*
.bit
*
.bin
*
.mcs
.PHONY
:
mrproper clean all
testsuite/017riviera/Makefile.ref
View file @
01dda1ab
...
...
@@ -28,8 +28,7 @@ $(VERILOG_OBJ) :
$(VHDL_OBJ)
:
$(LIB_IND)
work/.work
:
(
vlib work
&&
vmap
$(VMAP_FLAGS)
work
&&
touch
work/.work
)||
rm
-rf
work
(
vlib work
&&
vmap
$(VMAP_FLAGS)
work
&&
touch
work/.work
)
||
rm
-rf
work
work/gate/.gate_vhdl
:
../files/gate.vhdl
vcom
$(VCOM_FLAGS)
-work
work
$<
...
...
testsuite/024vlog_parser/Makefile.ref
View file @
01dda1ab
...
...
@@ -31,8 +31,7 @@ $(VHDL_OBJ): $(LIB_IND) modelsim.ini
modelsim.ini
:
$(MODELSIM_INI_PATH)/modelsim.ini
cp
$<
.
2>&1
work/.work
:
(
vlib work
&&
vmap
$(VMAP_FLAGS)
work
&&
touch
work/.work
)||
rm
-rf
work
(
vlib work
&&
vmap
$(VMAP_FLAGS)
work
&&
touch
work/.work
)
||
rm
-rf
work
work/vlog/.vlog_v
:
vlog.v
\
macros.v
...
...
testsuite/025vlog_parser/Makefile.ref
View file @
01dda1ab
...
...
@@ -31,8 +31,7 @@ $(VHDL_OBJ): $(LIB_IND) modelsim.ini
modelsim.ini
:
$(MODELSIM_INI_PATH)/modelsim.ini
cp
$<
.
2>&1
work/.work
:
(
vlib work
&&
vmap
$(VMAP_FLAGS)
work
&&
touch
work/.work
)||
rm
-rf
work
(
vlib work
&&
vmap
$(VMAP_FLAGS)
work
&&
touch
work/.work
)
||
rm
-rf
work
work/vlog/.vlog_v
:
vlog.v
\
inc/macros.v
...
...
testsuite/027vhdl_parser/Makefile.ref
View file @
01dda1ab
...
...
@@ -33,8 +33,7 @@ $(VHDL_OBJ): $(LIB_IND) modelsim.ini
modelsim.ini
:
$(MODELSIM_INI_PATH)/modelsim.ini
cp
$<
.
2>&1
work/.work
:
(
vlib work
&&
vmap
$(VMAP_FLAGS)
work
&&
touch
work/.work
)||
rm
-rf
work
(
vlib work
&&
vmap
$(VMAP_FLAGS)
work
&&
touch
work/.work
)
||
rm
-rf
work
work/gate/.gate_vhdl
:
gate.vhdl
\
work/pkg/.pkg_vhdl
...
...
testsuite/032manifest_vars/Makefile
View file @
01dda1ab
...
...
@@ -31,8 +31,7 @@ $(VHDL_OBJ): $(LIB_IND) modelsim.ini
modelsim.ini
:
$(MODELSIM_INI_PATH)/modelsim.ini
cp
$<
.
2>&1
work/.work
:
(
vlib work
&&
vmap
$(VMAP_FLAGS)
work
&&
touch
work/.work
)||
rm
-rf
work
(
vlib work
&&
vmap
$(VMAP_FLAGS)
work
&&
touch
work/.work
)
||
rm
-rf
work
work/gate/.gate_vhdl
:
../files/gate.vhdl
vcom
$(VCOM_FLAGS)
-work
work
$<
...
...
testsuite/043local_fetch/Makefile.ref
View file @
01dda1ab
...
...
@@ -31,8 +31,7 @@ $(VHDL_OBJ): $(LIB_IND) modelsim.ini
modelsim.ini
:
$(MODELSIM_INI_PATH)/modelsim.ini
cp
$<
.
2>&1
work/.work
:
(
vlib work
&&
vmap
$(VMAP_FLAGS)
work
&&
touch
work/.work
)||
rm
-rf
work
(
vlib work
&&
vmap
$(VMAP_FLAGS)
work
&&
touch
work/.work
)
||
rm
-rf
work
work/gate/.gate_vhdl
:
../files/gate.vhdl
vcom
$(VCOM_FLAGS)
-work
work
$<
...
...
testsuite/044files_dir/Makefile.ref
View file @
01dda1ab
...
...
@@ -31,8 +31,7 @@ $(VHDL_OBJ): $(LIB_IND) modelsim.ini
modelsim.ini
:
$(MODELSIM_INI_PATH)/modelsim.ini
cp
$<
.
2>&1
work/.work
:
(
vlib work
&&
vmap
$(VMAP_FLAGS)
work
&&
touch
work/.work
)||
rm
-rf
work
(
vlib work
&&
vmap
$(VMAP_FLAGS)
work
&&
touch
work/.work
)
||
rm
-rf
work
work/gate/.gate_vhdl
:
../files/gate.vhdl
vcom
$(VCOM_FLAGS)
-work
work
$<
...
...
testsuite/045incl_makefile/Makefile.ref
View file @
01dda1ab
...
...
@@ -33,8 +33,7 @@ $(VHDL_OBJ): $(LIB_IND) modelsim.ini
modelsim.ini
:
$(MODELSIM_INI_PATH)/modelsim.ini
cp
$<
.
2>&1
work/.work
:
(
vlib work
&&
vmap
$(VMAP_FLAGS)
work
&&
touch
work/.work
)||
rm
-rf
work
(
vlib work
&&
vmap
$(VMAP_FLAGS)
work
&&
touch
work/.work
)
||
rm
-rf
work
work/gate/.gate_vhdl
:
../files/gate.vhdl
vcom
$(VCOM_FLAGS)
-work
work
$<
...
...
testsuite/046incl_makefiles/Makefile.ref
View file @
01dda1ab
...
...
@@ -34,8 +34,7 @@ $(VHDL_OBJ): $(LIB_IND) modelsim.ini
modelsim.ini
:
$(MODELSIM_INI_PATH)/modelsim.ini
cp
$<
.
2>&1
work/.work
:
(
vlib work
&&
vmap
$(VMAP_FLAGS)
work
&&
touch
work/.work
)||
rm
-rf
work
(
vlib work
&&
vmap
$(VMAP_FLAGS)
work
&&
touch
work/.work
)
||
rm
-rf
work
work/gate/.gate_vhdl
:
../files/gate.vhdl
vcom
$(VCOM_FLAGS)
-work
work
$<
...
...
testsuite/052svlog_parser/Makefile.ref
View file @
01dda1ab
...
...
@@ -33,8 +33,7 @@ $(VHDL_OBJ): $(LIB_IND) modelsim.ini
modelsim.ini
:
$(MODELSIM_INI_PATH)/modelsim.ini
cp
$<
.
2>&1
work/.work
:
(
vlib work
&&
vmap
$(VMAP_FLAGS)
work
&&
touch
work/.work
)||
rm
-rf
work
(
vlib work
&&
vmap
$(VMAP_FLAGS)
work
&&
touch
work/.work
)
||
rm
-rf
work
work/pkg/.pkg_sv
:
pkg.sv
vlog
-work
work
$(VLOG_FLAGS)
-sv
${
INCLUDE_DIRS
}
$<
...
...
testsuite/057msim_windows/Makefile.ref
View file @
01dda1ab
...
...
@@ -31,8 +31,7 @@ $(VHDL_OBJ): $(LIB_IND) modelsim.ini
modelsim.ini
:
$(MODELSIM_INI_PATH)/modelsim.ini
copy
$<
.
2>&1
work\.work
:
(
vlib work
&&
vmap
$(VMAP_FLAGS)
work
&&
type
nul
>>
work
\.
work
)||
del /s /q /f work
(
vlib work
&&
vmap
$(VMAP_FLAGS)
work
&&
type
nul
>>
work
\.
work
)
||
del /s /q /f work
work/gate/.gate_vhdl
:
../files/gate.vhdl
vcom
$(VCOM_FLAGS)
-work
work
$<
...
...
testsuite/076extra_modules/Makefile.ref
View file @
01dda1ab
...
...
@@ -31,8 +31,7 @@ $(VHDL_OBJ): $(LIB_IND) modelsim.ini
modelsim.ini
:
$(MODELSIM_INI_PATH)/modelsim.ini
cp
$<
.
2>&1
work/.work
:
(
vlib work
&&
vmap
$(VMAP_FLAGS)
work
&&
touch
work/.work
)||
rm
-rf
work
(
vlib work
&&
vmap
$(VMAP_FLAGS)
work
&&
touch
work/.work
)
||
rm
-rf
work
work/gate_tb/.gate_tb_v
:
../files/gate_tb.v
vlog
-work
work
$(VLOG_FLAGS)
${
INCLUDE_DIRS
}
$<
...
...
testsuite/079err_vlg_macro/Makefile.ref
View file @
01dda1ab
...
...
@@ -31,8 +31,7 @@ $(VHDL_OBJ): $(LIB_IND) modelsim.ini
modelsim.ini
:
$(MODELSIM_INI_PATH)/modelsim.ini
cp
$<
.
2>&1
work/.work
:
(
vlib work
&&
vmap
$(VMAP_FLAGS)
work
&&
touch
work/.work
)||
rm
-rf
work
(
vlib work
&&
vmap
$(VMAP_FLAGS)
work
&&
touch
work/.work
)
||
rm
-rf
work
work/vlog/.vlog_v
:
vlog.v
vlog
-work
work
$(VLOG_FLAGS)
${
INCLUDE_DIRS
}
$<
...
...
testsuite/081vlog_ifdef_elsif_else/Makefile.ref
View file @
01dda1ab
...
...
@@ -33,8 +33,7 @@ $(VHDL_OBJ): $(LIB_IND) modelsim.ini
modelsim.ini
:
$(MODELSIM_INI_PATH)/modelsim.ini
cp
$<
.
2>&1
work/.work
:
(
vlib work
&&
vmap
$(VMAP_FLAGS)
work
&&
touch
work/.work
)||
rm
-rf
work
(
vlib work
&&
vmap
$(VMAP_FLAGS)
work
&&
touch
work/.work
)
||
rm
-rf
work
work/mod_a/.mod_a_v
:
mod_a.v
vlog
-work
work
$(VLOG_FLAGS)
${
INCLUDE_DIRS
}
$<
...
...
testsuite/087many_modules/Makefile.ref
View file @
01dda1ab
...
...
@@ -31,8 +31,7 @@ $(VHDL_OBJ): $(LIB_IND) modelsim.ini
modelsim.ini
:
$(MODELSIM_INI_PATH)/modelsim.ini
cp
$<
.
2>&1
work/.work
:
(
vlib work
&&
vmap
$(VMAP_FLAGS)
work
&&
touch
work/.work
)||
rm
-rf
work
(
vlib work
&&
vmap
$(VMAP_FLAGS)
work
&&
touch
work/.work
)
||
rm
-rf
work
work/gate/.gate_vhdl
:
../files/gate.vhdl
vcom
$(VCOM_FLAGS)
-work
work
$<
...
...
testsuite/088bad_file_abs/Makefile.ref
View file @
01dda1ab
...
...
@@ -31,8 +31,7 @@ $(VHDL_OBJ): $(LIB_IND) modelsim.ini
modelsim.ini
:
$(MODELSIM_INI_PATH)/modelsim.ini
cp
$<
.
2>&1
work/.work
:
(
vlib work
&&
vmap
$(VMAP_FLAGS)
work
&&
touch
work/.work
)||
rm
-rf
work
(
vlib work
&&
vmap
$(VMAP_FLAGS)
work
&&
touch
work/.work
)
||
rm
-rf
work
work/gate/.gate_vhdl
:
../files/gate.vhdl
vcom
$(VCOM_FLAGS)
-work
work
$<
...
...
testsuite/091library/Makefile.ref
View file @
01dda1ab
...
...
@@ -33,12 +33,10 @@ $(VHDL_OBJ): $(LIB_IND) modelsim.ini
modelsim.ini
:
$(MODELSIM_INI_PATH)/modelsim.ini
cp
$<
.
2>&1
sublib/.sublib
:
(
vlib sublib
&&
vmap
$(VMAP_FLAGS)
sublib
&&
touch
sublib/.sublib
)||
rm
-rf
sublib
(
vlib sublib
&&
vmap
$(VMAP_FLAGS)
sublib
&&
touch
sublib/.sublib
)
||
rm
-rf
sublib
work/.work
:
(
vlib work
&&
vmap
$(VMAP_FLAGS)
work
&&
touch
work/.work
)||
rm
-rf
work
(
vlib work
&&
vmap
$(VMAP_FLAGS)
work
&&
touch
work/.work
)
||
rm
-rf
work
work/gate3/.gate3_vhd
:
gate3.vhd
\
sublib/gate/.gate_vhdl
...
...
testsuite/093multi_sat/Makefile.ref
View file @
01dda1ab
...
...
@@ -35,8 +35,7 @@ $(VHDL_OBJ): $(LIB_IND) modelsim.ini
modelsim.ini
:
$(MODELSIM_INI_PATH)/modelsim.ini
cp
$<
.
2>&1
work/.work
:
(
vlib work
&&
vmap
$(VMAP_FLAGS)
work
&&
touch
work/.work
)||
rm
-rf
work
(
vlib work
&&
vmap
$(VMAP_FLAGS)
work
&&
touch
work/.work
)
||
rm
-rf
work
work/lgate/.lgate_vhdl
:
lgate.vhdl
\
work/gate/.gate_vhdl
...
...
testsuite/test_all.py
View file @
01dda1ab
...
...
@@ -38,6 +38,7 @@ class Config(object):
def
compare_makefile
():
ref
=
open
(
'Makefile.ref'
,
'r'
)
.
read
()
out
=
open
(
'Makefile'
,
'r'
)
.
read
()
# shutil.move('Makefile', 'Makefile.ref') # To regenerate
assert
out
==
ref
os
.
remove
(
'Makefile'
)
...
...
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