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Created with Raphaël 2.2.02Jun131May302422201918171615530Apr2926191430Mar252423201713Oct24Jun25May27Apr2428Mar27169Feb872Jan3Dec18Nov1514137510Oct963216Sep28Apr2610938Feb24Jan14Nov24Oct232221224Sep2327Aug1692131Jul201612115430Jun28272624232019181713121164224May21548Mar22Feb2123Jan31Oct30Jul274Jun26Apr1827Mar65329Feb23131024Jan23221825Oct626Aug239432126Jul151413121187429Jun2221201716151410976131May30272524201613111029Apr28272120181413121097628Mar2522171615119Refactoring in progress: no global variablesA little more of refactoring in the first stagesA little bit of comments and refactoring -- unstable: this may break some featuresFixed bug 1339. Added several new dependencies to vhdl parser.Remove old and unused dep_solver.pydisable fetch makefile section is simulation makefileMerge remote-tracking branch 'origin/feat_1337' into developPreliminary work on Feature 1326Implemented feature 1337: Ignore verilog code between "pragma protect being_protected" and "pragma protect end_protected"Update docs with info about the Xilinx ISE fine grained synthesis targetsAdd specific synthesis pre/post commands for the different stage targets at ISEfix gramatical typo on VHDL parserLook for modules and entities when trying to identify the top relationCreate the MODULE relation in Verilog and identify it with ARCHITECTURE in VHDLMove entity_name.lower() into DepRelation __init__()Fixing false positive missing relation warnings. Fix Architecture and Entity dependencies so that files listed in correct order.Merged branch master into masterAdd simulation file update.Fix typo on libero and diamond supported_files functionise: use synthesis variable syn_family if specifiedUse synthesis variable syn_family if specifiedAdd new synthesis variable syn_family (needed by some tools)Add support for .qsys (Altera's System Integration Tool) filesWrong import for fetch module at quartus.pyFix unexpected indent when importing src file types for QuartusAdd support for cyclone iv e/gx familyAdd system verilog (.sv) files to project as suchFixed doc bug regarding the recommended launch script for HDLMakeDisable the reverse option for list-files commandNow the list-files command introduces newlines if no delimiter is specifiedAdd the --reverse option to the list-files commandadd the make-remote command to the arg parserFix the file and module listing from any Manifest.pyadd more fine-grained make commandsenable parser by defaultExtend parser and specific files for all the toolsAdd vendor dependent files to the parsed synthesis fileset: WARNING, this breaks other synthesis tools but ISE!Add parser as an option for all the actionsAdd simulation file update.