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Created with Raphaël 2.2.028Jun97642131May302422201918171615530Apr2926191430Mar252423201713Oct24Jun25May27Apr2428Mar27169Feb872Jan3Dec18Nov1514137510Oct963216Sep28Apr2610938Feb24Jan14Nov24Oct232221224Sep2327Aug1692131Jul201612115430Jun28272624232019181713121164224May21548Mar22Feb2123Jan31Oct30Jul274Jun26Apr1827Mar65329Feb23131024Jan23221825Oct626Aug239432126Jul151413121187429Jun2221201716151410976131May30272524201613111029Apr2827212018Modelsim-like Makefiles use some POSIX commands: replace with Windows equivalents if available or rely on GNU Win32 Coreutils otherwiseThe 'which' command is not available at Windows command lineFix fetch for Git submodules on Windows: Normalize the paths to use the O.S. specific path separatorTree function: Solving unused package dependencies and other improvementsThe flag close_fds=True does not work on Windows: check before spawning a subprocessUse a platform independent Python function to determine if a path is absolute or relativeAdapt Modelsim-like makefiles to the new DAG solverdag-solverdag-solverFix include in Icarus Verilog and update the associated testsFixing simulation with Icarus VerilogChange the architecture ID in the DAG: this fixes JSON generationFix tree generationMayor version upgrade: hdlmake is based on Directed Acyclic Graphs nowFix the list files actionCleaning temporal debug messagesVHDL parser workaround: If we are not able to scan a package, use the full file as contentAdd support for more architecture closing schemesNew parse & solve strategy based on Directed Acyclic GraphsWARNING: Implementing a smarter parser/solver approach, this will break the system from this commit onwardsImprove parse/solve process for better performanceFix buf 1339 Added dependency check in vhdl parser for package bodyfeat_1339feat_1339Remove unused fetch_makefile.pySome improvements for the fetch mechanismDelete unused global_mod.pyRefactoring in progress: no global variablesA little more of refactoring in the first stagesA little bit of comments and refactoring -- unstable: this may break some featuresFixed bug 1339. Added several new dependencies to vhdl parser.Remove old and unused dep_solver.pydisable fetch makefile section is simulation makefileMerge remote-tracking branch 'origin/feat_1337' into developPreliminary work on Feature 1326Implemented feature 1337: Ignore verilog code between "pragma protect being_protected" and "pragma protect end_protected"Update docs with info about the Xilinx ISE fine grained synthesis targetsAdd specific synthesis pre/post commands for the different stage targets at ISEfix gramatical typo on VHDL parserLook for modules and entities when trying to identify the top relationCreate the MODULE relation in Verilog and identify it with ARCHITECTURE in VHDLMove entity_name.lower() into DepRelation __init__()Fixing false positive missing relation warnings. Fix Architecture and Entity dependencies so that files listed in correct order.