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Created with Raphaël 2.2.09Oct63216Sep28Apr2610938Feb24Jan14Nov24Oct232221224Sep2327Aug1692131Jul201612115430Jun28272624232019181713121164224May21548Mar22Feb2123Jan31Oct30Jul274Jun26Apr1827Mar65329Feb23131024Jan23221825Oct626Aug239432126Jul151413121187429Jun2221201716151410976131May30272524201613111029Apr28272120181413121097628Mar2522171615119814Jan1312Change sim_tool variable in Questa test from vsim to modelsimTest for UVM and SystemVerilog support on QuestaFix bug 1008: The vlog_parser checks if any packages are used by a source file and in case adds them to file's dependencies.Fix bug 1007: the ParserFactory checks instance of a SourceFile instead of checking file's extension.fix includes and translate source code to nametune vlog parser to include dependency chainsFiles can depend on other files that fall into two categories: included and compiled. The former don't need marker files(.name) and the dependency is directly on the included file. The latter need a marker file and the dependency is built on it. To check whether a file is compiled or included, we see if a file is in the manifests. If an included file will show up in one of the manifest, this rule will be broken and a buggy makefile will be produced.fix vlog parser to correctly build dependencies on included filesassert contructor typesMinor changes in sphinx configurationUpdated sphinx documentation & APIUpdated sphinx documentationRevert "Updated sphinx documentation"Updated sphinx documentationInitial automated API docs generationInitial new Sphinx based docsDelete obsolete docsRelocate XilinxsiminiReader ClassUpgrade to GPL v3 to match the source code licensing termsSimple 8-bit counter test for syn/sim, VHDL/VerilogInitial Altera Quartus tool moduleInitial Xilinx PlanAhead tool moduleInitial Mentor ModelSim tool moduleInitial Microsemi Libero tool moduleInitial Icarus Verilog tool moduleInitial Xilinx ISim tool moduleInitial Xilinx ISE tool moduleInitial ghdl tool moduleInitial Lattice Diamond tool moduleInitial Aldec Active-HDL tool moduleBase multi-tool support updateAdd a new test for Verilog remote synthesisAdd a new test for vhdl remote synthesisFix the include directive for vlogcomp [isim+verilog]Add some verilog tests to filterFix a problem in simulation isim testCreate a sim folder in filter testTests for simulation and synthesisCreate Binary Configuration File [issue 637]Hierachy Separator breaks ISE Synthesis