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Created with Raphaël 2.2.023Jun2019181713121164224May21548Mar22Feb2123Jan31Oct30Jul274Jun26Apr1827Mar65329Feb23131024Jan23221825Oct626Aug239432126Jul151413121187429Jun2221201716151410976131May30272524201613111029Apr28272120181413121097628Mar2522171615119814Jan1312unify simulation options:env_checker: add remote synthesis checkingreintroduce GPL noteMerge branch 'master' of ohwr.org:misc/hdl-makeadd initial enironmental checkerenv_checker: add more logicchanged copyright infoadd initial enironmental checkertest/*: no more generated filestest/*: add convinient files for running simulationtest/*: fix isim testbenchchanges made according to linter warningsRevert "corrections suggested by linter"corrections suggested by lintersrc/makefile_writer.py: fix missing dependency rulemakefile_writer.py: prettier vhdl dependency rule generation.gitattributes: fix binary filtervarious: small cleanupvarious: small fixes.gitattributes: fix binary name.gitignore: add .orig filesfix wrong commit filesadd upstream history and branchesUpdated list of supported FPGA chipsdoc/*: new documentation files.gitignore: add ignore fileshdlmake2: update binaryflow.py: fix ise standard lib typosrc/makefile_writer.py: Include placeholder file for incremental make dependencygenerate_modelsim_makefile call: fix name calling throughout the programmostly convention changesiverilog support with specific additional optionsMerge branch 'master' of ohwr.org:misc/hdl-makeAdded Verilog support for 'vm' file extension (netlis generated by Synplify).fix a bug in modelsim.ini parsingregenerate hdlmakeadd quartus project as actionfix bug preventing automatic flow from runningadd support for QIP filesfix altera megacores under modelsim