Commits · 0075884015ec89c53d52c1857cfc93970419c87e · Projects / Hdlmake · GitLab

Snippets Groups Projects

Oct 09, 2014
- fix vlog parser to correctly build dependencies on included files · 00758840
  Paweł Szostek authored 10 years ago
  
  00758840
- assert contructor types · d79227fe
  Paweł Szostek authored 10 years ago
  
  d79227fe
Oct 05, 2014
- Minor changes in sphinx configuration · 18ab5b78
  Javier D. Garcia-Lasheras authored 10 years ago
  
  18ab5b78
- Updated sphinx documentation & API · 02a454df
  Javier D. Garcia-Lasheras authored 10 years ago
  
  02a454df
- Updated sphinx documentation · e01cc160
  Javier D. Garcia-Lasheras authored 10 years ago
  
  e01cc160
- Revert "Updated sphinx documentation" · 285c5a07
  Javier D. Garcia-Lasheras authored 10 years ago
```
This reverts commit dc267836.
```
  285c5a07
- Updated sphinx documentation · dc267836
  Javier D. Garcia-Lasheras authored 10 years ago
  
  dc267836
Oct 03, 2014
- Initial automated API docs generation · d7740ae8
  Javier D. Garcia-Lasheras authored 10 years ago
  
  d7740ae8
Oct 02, 2014
- Initial new Sphinx based docs · df706b2d
  Javier D. Garcia-Lasheras authored 10 years ago
  
  df706b2d
- Delete obsolete docs · d7006a9a
  Javier D. Garcia-Lasheras authored 10 years ago
  
  d7006a9a
Sep 16, 2014
- Relocate XilinxsiminiReader Class · 0c0a06d8
  garcialasheras authored 10 years ago
  
  0c0a06d8
- Upgrade to GPL v3 to match the source code licensing terms · 8effe74c
  garcialasheras authored 10 years ago
  
  8effe74c
- Simple 8-bit counter test for syn/sim, VHDL/Verilog · cc56877a
  garcialasheras authored 10 years ago
  
  cc56877a
- Initial Altera Quartus tool module · 1d66eb8b
  garcialasheras authored 10 years ago
  
  1d66eb8b
- Initial Xilinx PlanAhead tool module · 48286ca5
  garcialasheras authored 10 years ago
  
  48286ca5
- Initial Mentor ModelSim tool module · 51e0a841
  garcialasheras authored 10 years ago
  
  51e0a841
- Initial Microsemi Libero tool module · ee1654f7
  garcialasheras authored 10 years ago
  
  ee1654f7
- Initial Icarus Verilog tool module · 2b9b0f89
  garcialasheras authored 10 years ago
  
  2b9b0f89
- Initial Xilinx ISim tool module · 23d99836
  garcialasheras authored 10 years ago
  
  23d99836
- Initial Xilinx ISE tool module · bdae4f90
  garcialasheras authored 10 years ago
  
  bdae4f90
- Initial ghdl tool module · 84ed62f9
  garcialasheras authored 10 years ago
  
  84ed62f9
- Initial Lattice Diamond tool module · d4d48136
  garcialasheras authored 10 years ago
  
  d4d48136
- Initial Aldec Active-HDL tool module · 028a63b8
  garcialasheras authored 10 years ago
  
  028a63b8
- Base multi-tool support update · cff1a962
  garcialasheras authored 10 years ago
  
  cff1a962
Apr 28, 2014
- Add a new test for Verilog remote synthesis · 9e679858
  Javier D. Garcia-Lasheras authored 10 years ago
  
  9e679858
- Add a new test for vhdl remote synthesis · 7c2e1944
  Javier D. Garcia-Lasheras authored 10 years ago
  
  7c2e1944
- Fix the include directive for vlogcomp [isim+verilog] · e90b4b32
  Javier D. Garcia-Lasheras authored 10 years ago
  
  e90b4b32
- Add some verilog tests to filter · 5e78f2a2
  Javier D. Garcia-Lasheras authored 10 years ago
  
  5e78f2a2
Apr 27, 2014
- Fix a problem in simulation isim test · 87e3bbc5
  Javier D. Garcia-Lasheras authored 10 years ago
  
  87e3bbc5
- Create a sim folder in filter test · f176dcf3
  Javier D. Garcia-Lasheras authored 10 years ago
  
  f176dcf3
Apr 26, 2014
- Tests for simulation and synthesis · 89fa25b6
  Javier D. Garcia-Lasheras authored 10 years ago
  
  89fa25b6
Apr 25, 2014
- Create Binary Configuration File [issue 637] · 77b94862
  Javier D. Garcia-Lasheras authored 10 years ago
  
  77b94862
- Hierachy Separator breaks ISE Synthesis · 4b4e621f
  Javier D. Garcia-Lasheras authored 10 years ago
  
  4b4e621f
Apr 10, 2014
- fix argument parsing · 4d5deecc
  Pawel Szostek authored 10 years ago
  
  4d5deecc
- Implement --force switch handling · ffa53083
  Pawel Szostek authored 10 years ago
  
  ffa53083
- __main__.py: better automatic flow dispatching · 1ea61641
  Pawel Szostek authored 10 years ago
  
  1ea61641
- Encode correctly (BCD) project.vhd things · 976a21c3
  Paweł Szostek authored 10 years ago
  
  976a21c3
Apr 09, 2014
- Merge branch 'master' of ohwr.org:misc/hdl-make · f2b4d907
  Pawel Szostek authored 10 years ago
```
Conflicts:
	hdlmake/action/ise_project.py
```
  f2b4d907
- minor fixes · 4a3c2dab
  Pawel Szostek authored 10 years ago
  
  4a3c2dab
- minor fix · f7092478
  Pawel Szostek authored 10 years ago
  
  f7092478