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Commit ed56092f authored by Paweł Szostek's avatar Paweł Szostek
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Do automatic fetching for simulation

parent e77df0c4
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......@@ -37,11 +37,12 @@ class HdlmakeKernel(object):
def run(self):
tm = self.top_module
if not self.modules_pool.is_everything_fetched():
self.fetch()
if tm.action == "simulation":
self.generate_modelsim_makefile()
elif tm.action == "synthesis":
if not self.modules_pool.is_everything_fetched():
self.fetch()
self.generate_ise_project()
self.generate_ise_makefile()
self.generate_remote_synthesis_makefile()
......
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