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Commit af468dec authored by Paweł Szostek's avatar Paweł Szostek
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comment out leftovers of ancient code

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hdlmake/srcfile.py
+ 156
− 156
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...@@ -46,9 +46,9 @@ class SourceFile(DepFile): ...@@ -46,9 +46,9 @@ class SourceFile(DepFile):
include_paths=module.include_dirs[:]) include_paths=module.include_dirs[:])
def gen_index(self): # def gen_index(self):
self.__class__.cur_index = self.__class__.cur_index+1 # self.__class__.cur_index = self.__class__.cur_index+1
return self.__class__.cur_index # return self.__class__.cur_index
class VHDLFile(SourceFile): class VHDLFile(SourceFile):
...@@ -68,88 +68,88 @@ class VHDLFile(SourceFile): ...@@ -68,88 +68,88 @@ class VHDLFile(SourceFile):
else: else:
return False return False
def _create_deps_provides(self): # def _create_deps_provides(self):
if self._check_encryption(): # if self._check_encryption():
self.dep_index = SourceFile.gen_index(self) # self.dep_index = SourceFile.gen_index(self)
else: # else:
self.dep_provides = list(self._search_packages()) # self.dep_provides = list(self._search_packages())
logging.debug(self.path + " provides " + str(self.dep_provides)) # logging.debug(self.path + " provides " + str(self.dep_provides))
def _create_deps_requires(self): # def _create_deps_requires(self):
if self._check_encryption(): # if self._check_encryption():
self.dep_index = SourceFile.gen_index(self) # self.dep_index = SourceFile.gen_index(self)
else: # else:
self.dep_requires = list(self._search_use_clauses()) # self.dep_requires = list(self._search_use_clauses())
logging.debug(self.path + " provides " + str(self.dep_provides)) # logging.debug(self.path + " provides " + str(self.dep_provides))
def _search_use_clauses(self): # def _search_use_clauses(self):
""" # """
Reads a file and looks for 'use' clause. For every 'use' with # Reads a file and looks for 'use' clause. For every 'use' with
non-standard library a tuple (lib, file) is returned in a list. # non-standard library a tuple (lib, file) is returned in a list.
""" # """
# Modification here! global_mod.top_module.action does not # # Modification here! global_mod.top_module.action does not
# get set for top module in time. FIX this # # get set for top module in time. FIX this
std_libs = ['std', 'ieee'] # std_libs = ['std', 'ieee']
if global_mod.top_module.action == "simulation": # if global_mod.top_module.action == "simulation":
try: # try:
if global_mod.top_module.sim_tool == "isim": # if global_mod.top_module.sim_tool == "isim":
std_libs = ise.XilinxsiminiReader().get_libraries() # std_libs = ise.XilinxsiminiReader().get_libraries()
elif global_mod.top_module.sim_tool == "vsim" or global_mod.top_module.sim_tool == "modelsim": # elif global_mod.top_module.sim_tool == "vsim" or global_mod.top_module.sim_tool == "modelsim":
std_libs = modelsim.ModelsiminiReader().get_libraries() # std_libs = modelsim.ModelsiminiReader().get_libraries()
elif global_mod.top_module.sim_tool == "iverilog": # elif global_mod.top_module.sim_tool == "iverilog":
std_libs = modelsim.MODELSIM_STANDARD_LIBS # std_libs = modelsim.MODELSIM_STANDARD_LIBS
else: # else:
logging.warning("Could not determine simulation tool. Defaulting to Modelsim") # logging.warning("Could not determine simulation tool. Defaulting to Modelsim")
std_libs = modelsim.MODELSIM_STANDARD_LIBS # std_libs = modelsim.MODELSIM_STANDARD_LIBS
except RuntimeError as e: # except RuntimeError as e:
logging.error("I/O error: ({0})".format(e.message)) # logging.error("I/O error: ({0})".format(e.message))
logging.error("Picking standard Modelsim simulation libraries. Try to fix the error.") # logging.error("Picking standard Modelsim simulation libraries. Try to fix the error.")
std_libs = modelsim.MODELSIM_STARDAND_LIBS # std_libs = modelsim.MODELSIM_STARDAND_LIBS
elif global_mod.top_module.action == "synthesis": # elif global_mod.top_module.action == "synthesis":
if global_mod.top_module.target == "xilinx": # if global_mod.top_module.target == "xilinx":
std_libs = ise.ISE_STANDARD_LIBS # std_libs = ise.ISE_STANDARD_LIBS
elif global_mod.top_module.target == "altera": # elif global_mod.top_module.target == "altera":
std_libs = quartus.QUARTUS_STANDARD_LIBS # std_libs = quartus.QUARTUS_STANDARD_LIBS
import re # import re
try: # try:
f = open(self.path, "r") # f = open(self.path, "r")
text = f.readlines() # text = f.readlines()
except UnicodeDecodeError: # except UnicodeDecodeError:
return [] # return []
use_pattern = re.compile("^[ \t]*use[ \t]+([^; ]+)[ \t]*;.*$") # use_pattern = re.compile("^[ \t]*use[ \t]+([^; ]+)[ \t]*;.*$")
lib_pattern = re.compile("([^.]+)\.([^.]+)\.all") # lib_pattern = re.compile("([^.]+)\.([^.]+)\.all")
use_lines = [] # use_lines = []
for line in text: # for line in text:
#identifiers and keywords are case-insensitive in VHDL # #identifiers and keywords are case-insensitive in VHDL
line_lower = line.lower() # line_lower = line.lower()
m = re.match(use_pattern, line_lower) # m = re.match(use_pattern, line_lower)
if m is not None: # if m is not None:
use_lines.append(m.group(1)) # use_lines.append(m.group(1))
ret = set() # ret = set()
for line in use_lines: # for line in use_lines:
m = re.match(lib_pattern, line) # m = re.match(lib_pattern, line)
if m is not None: # if m is not None:
#omit standard libraries # #omit standard libraries
if (m.group(1)).lower() in std_libs: # if (m.group(1)).lower() in std_libs:
continue # continue
if self.library != "work": # if self.library != "work":
#if a file is put in a library, `work' points this library # #if a file is put in a library, `work' points this library
new = (self.library.lower(), m.group(2).lower()) # new = (self.library.lower(), m.group(2).lower())
else: # else:
new = (m.group(1).lower(), m.group(2).lower()) # new = (m.group(1).lower(), m.group(2).lower())
#dont add if the tuple is already in the list # #dont add if the tuple is already in the list
if new in self.dep_provides: # if new in self.dep_provides:
continue # continue
ret.add(new) # ret.add(new)
f.close() # f.close()
return ret # return ret
class VerilogFile(SourceFile): class VerilogFile(SourceFile):
...@@ -166,77 +166,77 @@ class VerilogFile(SourceFile): ...@@ -166,77 +166,77 @@ class VerilogFile(SourceFile):
self.include_dirs.extend(include_dirs) self.include_dirs.extend(include_dirs)
self.include_dirs.append(path_mod.relpath(self.dirname)) self.include_dirs.append(path_mod.relpath(self.dirname))
def _create_deps_provides(self): # def _create_deps_provides(self):
# self.dep_requires = self.__search_includes() # # self.dep_requires = self.__search_includes()
# self.dep_provides = self.name # # self.dep_provides = self.name
self.dep_provides = self.name # self.dep_provides = self.name
def _create_deps_requires(self): # def _create_deps_requires(self):
# self.dep_requires = self.__search_includes() # # self.dep_requires = self.__search_includes()
# self.dep_provides = self.name # # self.dep_provides = self.name
if global_mod.top_module.sim_tool == "iverilog": # if global_mod.top_module.sim_tool == "iverilog":
deps = self._get_iverilog_dependencies() # deps = self._get_iverilog_dependencies()
self.dep_requires = deps # self.dep_requires = deps
else: # else:
self.dep_requires = self._search_includes() # self.dep_requires = self._search_includes()
def _get_iverilog_dependencies(self): # def _get_iverilog_dependencies(self):
#TODO: Check to see dependencies.list doesn't exist already # #todo: check to see dependencies.list doesn't exist already
if self.path.endswith(".vh") and global_mod.top_module.sim_tool == "iverilog": # if self.path.endswith(".vh") and global_mod.top_module.sim_tool == "iverilog":
return [] # return []
inc_dirs = [] # inc_dirs = []
#inc_dirs = global_mod.top_module.include_dirs # #inc_dirs = global_mod.top_module.include_dirs
inc_dirs = self.include_dirs # inc_dirs = self.include_dirs
if global_mod.mod_pool: # if global_mod.mod_pool:
inc_dirs.extend([os.path.relpath(m.path) for m in global_mod.mod_pool]) # inc_dirs.extend([os.path.relpath(m.path) for m in global_mod.mod_pool])
inc_dirs = list(set(inc_dirs)) # inc_dirs = list(set(inc_dirs))
vlog_opt = global_mod.top_module.vlog_opt # vlog_opt = global_mod.top_module.vlog_opt
depFileName = "dependencies.list" # depfilename = "dependencies.list"
command = "iverilog -DSIMULATE -Wno-timescale -t null -M" + depFileName # command = "iverilog -dsimulate -wno-timescale -t null -m" + depfilename
command += "".join(map(lambda x: " -y"+x, inc_dirs)) # command += "".join(map(lambda x: " -y"+x, inc_dirs))
command += "".join(map(lambda x: " -I"+x, inc_dirs)) # command += "".join(map(lambda x: " -i"+x, inc_dirs))
# TODO: Have to find a way to handle this cleanly # # todo: have to find a way to handle this cleanly
if self.rel_path().find("config_romx_llrf4") > -1: # if self.rel_path().find("config_romx_llrf4") > -1:
command += " " + vlog_opt # command += " " + vlog_opt
else: # else:
command += " " + vlog_opt + " " + self.rel_path() # command += " " + vlog_opt + " " + self.rel_path()
logging.debug("running %s" % command) # logging.debug("running %s" % command)
retcode = os.system(command) # retcode = os.system(command)
# iverilog_cmd = Popen(command, shell=True, stdin=PIPE, # # iverilog_cmd = popen(command, shell=true, stdin=pipe,
# stdout=PIPE, close_fds=True) # # stdout=pipe, close_fds=true)
# iverilog_cmd.stdout.readlines() # # iverilog_cmd.stdout.readlines()
# iverilog_cmd.wait() # # iverilog_cmd.wait()
# retcode = iverilog_cmd.returncode # # retcode = iverilog_cmd.returncode
print("retcode", retcode) # print("retcode", retcode)
if retcode and retcode != 256: # if retcode and retcode != 256:
logging.error("Dependencies not met for %s" % str(self.path)) # logging.error("dependencies not met for %s" % str(self.path))
logging.debug(command, self.include_dirs, inc_dirs, global_mod.mod_pool) # logging.debug(command, self.include_dirs, inc_dirs, global_mod.mod_pool)
quit() # quit()
elif retcode == 256: # elif retcode == 256:
#dependencies met # #dependencies met
pass # pass
depFile = open(depFileName, "r") # depfile = open(depfilename, "r")
depFiles = list(set([l.strip() for l in depFile.readlines()])) # depfiles = list(set([l.strip() for l in depfile.readlines()]))
depFile.close() # depfile.close()
return depFiles # return depfiles
def _search_includes(self): # def _search_includes(self):
import re # import re
f = open(self.path, "r") # f = open(self.path, "r")
try: # try:
text = f.readlines() # text = f.readlines()
except UnicodeDecodeError: # except unicodedecodeerror:
return [] # return []
include_pattern = re.compile("^[ \t]*`include[ \t]+\"([^ \"]+)\".*$") # include_pattern = re.compile("^[ \t]*`include[ \t]+\"([^ \"]+)\".*$")
ret = [] # ret = []
for line in text: # for line in text:
#in Verilog and SV identifiers are case-sensitive # #in verilog and sv identifiers are case-sensitive
m = re.match(include_pattern, line) # m = re.match(include_pattern, line)
if m is not None: # if m is not none:
ret.append(m.group(1)) # ret.append(m.group(1))
f.close() # f.close()
return ret # return ret
class SVFile(VerilogFile): class SVFile(VerilogFile):
......
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