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Commit a8ebe445 authored by Paweł Szostek's avatar Paweł Szostek
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do not initialize makefile when not necessary

parent 4aabbf99
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hdlmake/makefile_writer.py
+ 39
− 57
View file @ a8ebe445
......@@ -27,12 +27,13 @@ import global_mod
from string import Template
class _Box():
class _StaticClassVariable():
pass
_m = _Box()
_m = _StaticClassVariable()
_m.initialized = False
class MakefileWriter(object):
def __init__(self, filename=None):
self._file = None
......@@ -40,18 +41,17 @@ class MakefileWriter(object):
self._filename = filename
else:
self._filename = "Makefile"
self.initialize()
def __del__(self):
self._file.close()
if self._file:
self._file.close()
def initialize(self):
if not _m.initialized:
if os.path.exists(self._filename):
if os.path.isfile(self._filename):
os.remove(self._filename)
elif os.path.isdir(self._filename):
os.rmdir(self._filename)
if os.path.exists(self._filename):
if os.path.isfile(self._filename):
os.remove(self._filename)
elif os.path.isdir(self._filename):
os.rmdir(self._filename)
self._file = open(self._filename, "a+")
if not _m.initialized:
......@@ -60,9 +60,11 @@ class MakefileWriter(object):
self.writeln("# http://ohwr.org/projects/hdl-make/ #")
self.writeln("########################################")
self.writeln()
_m.initialized = True
def write(self, line=None):
if not _m.initialized:
self.initialize()
_m.initialized = True
self._file.write(line)
def writeln(self, text=None):
......@@ -307,18 +309,21 @@ mrproper:
from srcfile import VerilogFile
#open the file and write the above preambule (part 1)
self.initialize()
import global_mod
# for m in global_mod.mod_pool:
for f in global_mod.top_module.incl_makefiles:
self.writeln("include " + f)
# libs = set(f.library for f in fileset)
libs = set(f.library for f in fileset)
target_list = []
for vl in fileset.filter(VerilogFile):
rel_dir_path = os.path.dirname(vl.rel_path())
target_name = os.path.join(rel_dir_path, vl.purename)
if rel_dir_path:
rel_dir_path = rel_dir_path + '/'
target_name = os.path.join(rel_dir_path+vl.purename)
target_list.append(target_name)
# dependencies_string = ' '.join([f.rel_path() for f in vl.dep_depends_on if (f.name != vl.name) and not f.name
dependencies_string = ' '.join([f.rel_path() for f in vl.dep_depends_on if (f.name != vl.name)])
include_dirs = list(set([os.path.dirname(f.rel_path()) for f in vl.dep_depends_on if f.name.endswith("vh")]))
# dependencies_string = ' '.join([f.rel_path() for f in vl.depends_on if (f.name != vl.name) and not f.name
dependencies_string = ' '.join([f.rel_path() for f in vl.depends_on if (f.name != vl.name)])
include_dirs = list(set([os.path.dirname(f.rel_path()) for f in vl.depends_on if f.name.endswith("vh")]))
while "" in include_dirs:
include_dirs.remove("")
include_dir_string = " -I".join(include_dirs)
......@@ -340,8 +345,8 @@ mrproper:
for m in global_mod.mod_pool:
for f in m.sim_only_files:
sim_only_files.append(f.name)
# top_name = global_mod.top_module.syn_top
# top_name_syn_deps = []
top_name = global_mod.top_module.syn_top
top_name_syn_deps = []
bit_targets = []
for m in global_mod.mod_pool:
......@@ -352,16 +357,16 @@ mrproper:
# This can perhaps be done faster (?)
for vl in fileset.filter(VerilogFile):
if vl.purename == bt:
for f in vl.dep_depends_on:
for f in vl.depends_on:
if (f.name != vl.name and f.name not in sim_only_files):
bt_syn_deps.append(f)
self.writeln(bt+'syn_deps = ' + ' '.join([f.rel_path() for f in bt_syn_deps]))
self.writeln(bt+'syn_deps = '+ ' '.join([f.rel_path() for f in bt_syn_deps]))
if not os.path.exists("%s.ucf" % bt):
logging.warning("The file %s.ucf doesn't exist!" % bt)
self.writeln(bt+".bit:\t"+bt+".v $("+bt+"syn_deps) "+bt+".ucf")
part = (global_mod.top_module.syn_device + '-' +
global_mod.top_module.syn_package +
global_mod.top_module.syn_grade)
part=(global_mod.top_module.syn_device+'-'+
global_mod.top_module.syn_package+
global_mod.top_module.syn_grade)
self.writeln("\tPART="+part+" $(SYNTH) "+bt+" $^")
self.writeln("\tmv _xilinx/"+bt+".bit $@")
......@@ -370,18 +375,17 @@ mrproper:
def generate_vsim_makefile(self, fileset, top_module):
from srcfile import VerilogFile, VHDLFile, SVFile
from tools.modelsim import ModelsiminiReader
make_preambule_p1 = """## variables #############################
PWD := $(shell pwd)
MODELSIM_INI_PATH := """ + ModelsiminiReader.modelsim_ini_dir() + """
MODELSIM_INI_PATH := $(HDLMAKE_MODELSIM_PATH)"../"
VCOM_FLAGS := -quiet -modelsimini modelsim.ini
VSIM_FLAGS :=
VLOG_FLAGS := -quiet -modelsimini modelsim.ini """ + self.__get_rid_of_incdirs(top_module.vlog_opt) + """
"""
make_preambule_p2 = Template("""## rules #################################
sim: check_tool sim_pre_cmd modelsim.ini $$(LIB_IND) $$(VERILOG_OBJ) $$(VHDL_OBJ)
sim: sim_pre_cmd modelsim.ini $$(LIB_IND) $$(VERILOG_OBJ) $$(VHDL_OBJ)
$$(VERILOG_OBJ): $$(VHDL_OBJ)
$$(VHDL_OBJ): $$(LIB_IND) modelsim.ini
......@@ -391,13 +395,11 @@ sim_pre_cmd:
sim_post_cmd: sim
\t\t${sim_post_cmd}
check_tool:
\t\t${check_tool}
modelsim.ini: $$(MODELSIM_INI_PATH)/modelsim.ini
\t\tcp $$< .
clean:
\t\trm -rf ./modelsim.ini $$(LIBS)
.PHONY: clean sim_pre_cmd sim_post_cmd check_tool
.PHONY: clean sim_pre_cmd sim_post_cmd
""")
#open the file and write the above preambule (part 1)
......@@ -449,17 +451,8 @@ clean:
sim_post_cmd = top_module.sim_post_cmd
else:
sim_post_cmd = ''
if top_module.force_tool:
ft = top_module.force_tool
check_tool = """python $(HDLMAKE_HDLMAKE_PATH)/hdlmake _conditioncheck --tool {tool} --reference {reference} --condition "{condition}"\\
|| (echo "{tool} version does not meet condition: {condition} {reference}" && false)
""".format(tool=ft[0],
condition=ft[1],
reference=ft[2])
make_preambule_p2 = make_preambule_p2.substitute(sim_pre_cmd=sim_pre_cmd,
sim_post_cmd=sim_post_cmd,
check_tool=check_tool)
sim_post_cmd=sim_post_cmd)
self.write(make_preambule_p2)
for lib in libs:
......@@ -518,13 +511,10 @@ ISIM_FLAGS :=
VLOGCOMP_FLAGS := -intstyle default -incremental -initfile xilinxsim.ini """ + self.__get_rid_of_incdirs(top_module.vlog_opt) + """
"""
make_preambule_p2 = """## rules #################################
sim: xilinxsim.ini check_tool $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
sim: xilinxsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
$(VERILOG_OBJ): $(LIB_IND) xilinxsim.ini
$(VHDL_OBJ): $(LIB_IND) xilinxsim.ini
check_tool:
\t\t{check_tool}
xilinxsim.ini: $(XILINX_INI_PATH)/xilinxsim.ini
\t\tcp $< .
fuse:
......@@ -532,11 +522,12 @@ fuse:
clean:
\t\trm -rf ./xilinxsim.ini $(LIBS) fuse.xmsgs fuse.log fuseRelaunch.cmd isim isim.log \
isim.wdb
.PHONY: clean check_tool
.PHONY: clean
"""
#open the file and write the above preambule (part 1)
self.initialize()
self.write(make_preambule_p1)
self.write("VERILOG_SRC := ")
for vl in fileset.filter(VerilogFile):
......@@ -573,15 +564,6 @@ isim.wdb
self.write('LIB_IND := ')
self.write(' '.join([lib+"/."+lib for lib in libs]))
self.write('\n')
if top_module.force_tool:
ft = top_module.force_tool
check_tool = """python $(HDLMAKE_HDLMAKE_PATH)/hdlmake _conditioncheck --tool {tool} --reference {reference} --condition "{condition}"\\
|| (echo "{tool} version does not meet condition: {condition} {reference}" && false)
""".format(tool=ft[0],
condition=ft[1],
reference=ft[2])
self.write(make_preambule_p2.format(check_tool=check_tool))
self.write(make_preambule_p2)
# ISim does not have a vmap command to insert additional libraries in
......@@ -607,7 +589,7 @@ isim.wdb
#self.writeln(".PHONY: " + os.path.join(comp_obj, '.'+vl.purename+"_"+vl.extension()))
self.write(os.path.join(comp_obj, '.'+vl.purename+"_"+vl.extension())+': ')
self.write(vl.rel_path() + ' ')
self.writeln(' '.join([fname.rel_path() for fname in vl.dep_depends_on]))
self.writeln(' '.join([fname.rel_path() for fname in vl.depends_on]))
self.write("\t\tvlogcomp -work "+vl.library+"=./"+vl.library)
self.write(" $(VLOGCOMP_FLAGS) ")
#if isinstance(vl, SVFile):
......@@ -635,12 +617,12 @@ isim.wdb
self.writeln("\t\t@mkdir -p $(dir $@) && touch $@\n")
self.writeln()
# dependency meta-target. This rule just list the dependencies of the above file
#if len(vhdl.dep_depends_on) != 0:
#if len(vhdl.depends_on) != 0:
#self.writeln(".PHONY: " + os.path.join(lib, purename, "."+purename))
# Touch the dependency file as well. In this way, "make" will recompile only what is needed (out of date)
#if len(vhdl.dep_depends_on) != 0:
#if len(vhdl.depends_on) != 0:
self.write(os.path.join(lib, purename, "."+purename) + ":")
for dep_file in vhdl.dep_depends_on:
for dep_file in vhdl.depends_on:
name = dep_file.purename
self.write(" \\\n" + os.path.join(dep_file.library, name, "."+name + "_" + vhdl.extension()))
self.write('\n')
......
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