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Hdlmake
Commits
8d3eacaa
Commit
8d3eacaa
authored
13 years ago
by
Paweł Szostek
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Fix fetch-makefile generation
Now modules to be fetched are recognized properly
parent
a7fcbdb3
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Changes
4
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4 changed files
synthesis/fetch.py
+3
-0
3 additions, 0 deletions
synthesis/fetch.py
synthesis/hdlmake_kernel.py
+0
-3
0 additions, 3 deletions
synthesis/hdlmake_kernel.py
synthesis/makefile_writer.py
+2
-2
2 additions, 2 deletions
synthesis/makefile_writer.py
synthesis/module.py
+3
-0
3 additions, 0 deletions
synthesis/module.py
with
8 additions
and
5 deletions
synthesis/fetch.py
+
3
−
0
View file @
8d3eacaa
...
@@ -270,6 +270,9 @@ class ModulePool(list):
...
@@ -270,6 +270,9 @@ class ModulePool(list):
raise
RuntimeError
(
"
Expecting a Module instance
"
)
raise
RuntimeError
(
"
Expecting a Module instance
"
)
if
self
.
__contains
(
new_module
):
if
self
.
__contains
(
new_module
):
return
return
for
mod
in
new_module
.
submodules
():
self
.
add
(
mod
)
if
new_module
.
isfetched
:
if
new_module
.
isfetched
:
self
.
modules
.
append
(
new_module
)
self
.
modules
.
append
(
new_module
)
return
True
return
True
...
...
This diff is collapsed.
Click to expand it.
synthesis/hdlmake_kernel.py
+
0
−
3
View file @
8d3eacaa
...
@@ -208,9 +208,6 @@ class HdlmakeKernel(object):
...
@@ -208,9 +208,6 @@ class HdlmakeKernel(object):
os
.
chdir
(
"
..
"
)
os
.
chdir
(
"
..
"
)
ssh
.
transfer_files_back
(
what
=
dest_folder
+
cwd
,
where
=
"
.
"
)
ssh
.
transfer_files_back
(
what
=
dest_folder
+
cwd
,
where
=
"
.
"
)
os
.
chdir
(
cur_dir
)
os
.
chdir
(
cur_dir
)
# if global_mod.options.del == True:
# p.echo("Deleting synthesis folder")
# ssh.system('rm -rf ' + dest_folder)
def
__search_tcl_file
(
self
,
directory
=
None
):
def
__search_tcl_file
(
self
,
directory
=
None
):
import
re
import
re
...
...
This diff is collapsed.
Click to expand it.
synthesis/makefile_writer.py
+
2
−
2
View file @
8d3eacaa
...
@@ -152,9 +152,9 @@ mrproper:
...
@@ -152,9 +152,9 @@ mrproper:
file
.
write
(
"
cd
"
+
rp
(
module
.
fetchto
)
+
'
;
'
)
file
.
write
(
"
cd
"
+
rp
(
module
.
fetchto
)
+
'
;
'
)
c
=
"
svn checkout {0} {1};
"
c
=
"
svn checkout {0} {1};
"
if
module
.
revision
:
if
module
.
revision
:
c
.
format
(
module
.
url
,
module
.
revision
)
c
=
c
.
format
(
module
.
url
,
module
.
revision
)
else
:
else
:
c
.
format
(
module
.
url
,
""
)
c
=
c
.
format
(
module
.
url
,
""
)
file
.
write
(
c
)
file
.
write
(
c
)
file
.
write
(
"
cd $(PWD)
\n\n
"
)
file
.
write
(
"
cd $(PWD)
\n\n
"
)
...
...
This diff is collapsed.
Click to expand it.
synthesis/module.py
+
3
−
0
View file @
8d3eacaa
...
@@ -123,6 +123,9 @@ class Module(object):
...
@@ -123,6 +123,9 @@ class Module(object):
def
__str__
(
self
):
def
__str__
(
self
):
return
self
.
url
return
self
.
url
def
submodules
(
self
):
return
self
.
local
+
self
.
git
+
self
.
svn
def
basename
(
self
):
def
basename
(
self
):
import
path
import
path
return
path
.
url_basename
(
self
.
url
)
return
path
.
url_basename
(
self
.
url
)
...
...
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