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Commit 617cd7b4 authored by Paweł Szostek's avatar Paweł Szostek
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Case insensitivity for id's and keywords applied

parent 3e0c51df
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......@@ -166,6 +166,7 @@ class VHDLFile(SourceFile):
ret = []
for line in text:
line = line.lower()
m = re.match(package_pattern, line)
if m != None:
ret.append(self.library.lower()+"::"+m.group(1).lower())
......@@ -195,6 +196,7 @@ class VerilogFile(SourceFile):
include_pattern = re.compile("^[ \t]*`include[ \t]+\"([^ \"]+)\".*$")
ret = []
for line in text:
line = line.lower()
m = re.match(include_pattern, line)
if m != None:
ret.append(m.group(1))
......
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