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Commit 5c8e8bb7 authored by Paweł Szostek's avatar Paweł Szostek
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CDC file feature

parent f49c7774
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hdlmake
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src/dep_solver.py
+ 6
− 3
View file @ 5c8e8bb7
......@@ -95,7 +95,7 @@ class DependencySolver:
max_iter = 100
import copy
fset = fileset.files;
fset = fileset.filter(IDependable);
f_nondep = []
......@@ -131,7 +131,7 @@ class DependencySolver:
p.vprint(f.path)
if f.dep_requires:
for req in f.dep_requires:
pf = self._find_provider_vhdl_file(fset, req)
pf = self._find_provider_vhdl_file([file for file in fset if isinstance(file, VHDLFile)], req)
if not pf:
p.rawprint("Missing dependency in file "+str(f)+": " + req)
quit()
......@@ -155,7 +155,10 @@ class DependencySolver:
newobj = sf.SourceFileSet();
newobj.add(f_nondep);
for f in fset:
if not f.dep_fixed:
try:
if not f.dep_fixed:
newobj.add(f)
except:
newobj.add(f)
for k in newobj.files:
......
src/flow.py
+ 37
− 13
View file @ 5c8e8bb7
......@@ -108,43 +108,65 @@ class ISEProject:
where = self.xml_doc.documentElement
self.xml_files = self.__purge_dom_node(name="files", where=where)
node = where.getElementsByTagName("version")[0]
where.removeChild(node)
self.xml_bindings = self.__purge_dom_node(name="bindings", where=where)
try:
node = where.getElementsByTagName("version")[0]
where.removeChild(node)
except:
pass
f.close()
def __purge_dom_node(self, name, where):
node = where.getElementsByTagName(name)[0]
where.removeChild(node)
try:
node = where.getElementsByTagName(name)[0]
where.removeChild(node)
except:
pass
new = self.xml_doc.createElement(name)
where.appendChild(new)
return new
def __output_files(self, node):
for f in self.files:
import os
from srcfile import UCFFile, VHDLFile, VerilogFile
from srcfile import UCFFile, VHDLFile, VerilogFile, CDCFile
fp = self.xml_doc.createElement("file")
fp.setAttribute("xil_pn:name", os.path.relpath(f.path))
if (isinstance(f, VHDLFile)):
if isinstance(f, VHDLFile):
fp.setAttribute("xil_pn:type", "FILE_VHDL")
elif (isinstance(f, VerilogFile)):
elif isinstance(f, VerilogFile):
fp.setAttribute("xil_pn:type", "FILE_VERILOG")
elif (isinstance(f, UCFFile)):
elif isinstance(f, UCFFile):
fp.setAttribute("xil_pn:type", "FILE_UCF")
elif isinstance(f, CDCFile):
fp.setAttribute("xil_pn:type", "FILE_CDC")
else:
continue
assoc = self.xml_doc.createElement("association");
assoc.setAttribute("xil_pn:name", "Implementation");
assoc.setAttribute("xil_pn:seqID", str(self.files.index(f)+1));
if(f.library != "work"):
try:
if(f.library != "work"):
lib = self.xml_doc.createElement("library");
lib.setAttribute("xil_pn:name", f.library);
fp.appendChild(lib)
except:
pass
fp.appendChild(assoc)
node.appendChild(fp);
def __output_bindings(self, node):
from srcfile import CDCFile
for b in [f for f in self.files if isinstance(f, CDCFile)]:
print b.path
bp = self.xml_doc.createElement("binding")
bp.setAttribute("xil_pn:location", self.top_mod.syn_top)
bp.setAttribute("xil_pn:name",b.rel_path())
node.appendChild(bp)
def __output_props(self, node):
for p in self.props:
node.appendChild(p.emit_xml(self.xml_doc))
......@@ -167,12 +189,12 @@ class ISEProject:
self.create_empty_project()
else:
self.__output_ise(self.xml_doc.documentElement)
self.__output_bindings(self.xml_bindings)
self.__output_files(self.xml_files)
self.__output_props(self.xml_props)
self.__output_libs(self.xml_libs)
self.xml_doc.writexml(open(filename,"w"), newl="\n", addindent="\t")
def create_empty_project(self):
self.xml_doc = xmlimpl.createDocument("http://www.xilinx.com/XMLSchema", "project", None)
top_element = self.xml_doc.documentElement
......@@ -189,9 +211,11 @@ class ISEProject:
self.xml_files = self.xml_doc.createElement("files")
self.xml_props = self.xml_doc.createElement("properties")
self.xml_libs = self.xml_doc.createElement("libraries")
self.xml_bindings = self.xml_doc.createElement("bindings")
top_element.appendChild(header)
top_element.appendChild(version)
top_element.appendChild(self.xml_files)
top_element.appendChild(self.xml_props)
top_element.appendChild(self.xml_libs)
top_element.appendChild(self.xml_bindings)
src/hdlmake_kernel.py
+ 8
− 2
View file @ 5c8e8bb7
......@@ -137,13 +137,16 @@ class HdlmakeKernel(object):
def __update_existing_ise_project(self, ise):
from dep_solver import DependencySolver
from srcfile import IDependable
from flow import ISEProject
top_mod = self.modules_pool.get_top_module()
fileset = self.modules_pool.build_global_file_list()
solver = DependencySolver()
non_dependable = fileset.inversed_filter(IDependable)
fileset = solver.solve(fileset)
fileset.add(non_dependable)
prj = ISEProject(ise=ise)
prj = ISEProject(ise=ise, top_mod=self.modules_pool.get_top_module())
prj.add_files(fileset)
prj.add_libs(fileset.get_libs())
prj.load_xml(top_mod.syn_project)
......@@ -151,13 +154,16 @@ class HdlmakeKernel(object):
def __create_new_ise_project(self, ise):
from dep_solver import DependencySolver
from srcfile import IDependable
from flow import ISEProject, ISEProjectProperty
top_mod = self.modules_pool.get_top_module()
fileset = self.modules_pool.build_global_file_list()
solver = DependencySolver()
non_dependable = fileset.inversed_filter(IDependable)
fileset = solver.solve(fileset)
fileset.add(non_dependable)
prj = ISEProject(ise=ise)
prj = ISEProject(ise=ise, top_mod=self.modules_pool.get_top_module())
prj.add_files(fileset)
prj.add_libs(fileset.get_libs())
......
src/srcfile.py
+ 28
− 9
View file @ 5c8e8bb7
......@@ -201,9 +201,9 @@ class VerilogFile(SourceFile):
f.close()
return ret
class UCFFile(SourceFile):
class UCFFile(File):
def __init__(self, path):
SourceFile.__init__(self, path);
File.__init__(self, path);
class TCLFile(File):
def __init__(self, path):
......@@ -212,14 +212,18 @@ class TCLFile(File):
class XISEFile(File):
def __init__(self, path):
File.__init__(self, path)
class CDCFile(File):
def __init__(self, path):
File.__init__(self, path)
class NGCFile(SourceFile):
class NGCFile(File):
def __init__(self, path):
SourceFile.__init__(self, path);
File.__init__(self, path);
class WBGenFile(SourceFile):
class WBGenFile(File):
def __init__(self, path):
SourceFile.__init__(self, path);
File.__init__(self, path);
class SourceFileSet(object):
def __init__(self):
......@@ -260,9 +264,22 @@ class SourceFileSet(object):
if isinstance(f, type):
out.append(f)
return out
def inversed_filter(self, type):
out = []
for f in self.files:
if not isinstance(f,type):
out.append(f)
return out
def get_libs(self):
return set(file.library for file in self.files)
ret = set()
for file in self.files:
try:
ret.add(file.library)
except:
pass
return ret
class SourceFileFactory:
def new (self, path, library = None):
......@@ -280,9 +297,11 @@ class SourceFileFactory:
elif extension == 'v' or extension == 'sv':
nf = VerilogFile(path, library);
elif extension == 'ngc':
nf = NGCFile(path);
nf = NGCFile(path)
elif extension == 'ucf':
nf = UCFFile(path);
nf = UCFFile(path)
elif extension == 'cdc':
nf = CDCFile(path)
elif extension == 'wb':
nf = WBGenFile(path);
elif extension == 'tcl':
......
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