index.rst

Welcome to hdlmake's documentation!

Warning

The full project documentation is under development. Check this space as new content will be added in the coming days.

• :ref:`genindex`
• :ref:`modindex`
• :ref:`search`

Introduction

Contribute

• Issue Tracker: http://www.ohwr.org/projects/hdl-make/issues
• Source Code: http://www.ohwr.org/projects/hdl-make/repository

Support

If you are having issues, please let us know. We have a mailing list located at: http://www.ohwr.org/mailing_list/show?project_id=hdl-make

License

This document is licensed under the Creative Commons Attribution-ShareAlike 4.0 International License. To view a copy of this license, visit: http://creativecommons.org/licenses/by-sa/4.0/deed.en_US

The source code for the hdlmake project is licensed under the GPL license version 3 or later. To get more info about this license, visit the following link: http://www.gnu.org/copyleft/gpl.html

Copyright notice

CERN, the European Organization for Nuclear Research, is the first and sole owner of all copyright of both this document and the associated source code deliverables.

Features

• Synthesis
• Simulation
• GIT/SVN Support
• Multi Language
• Multi Tools
• Multiple Operating System Support

Supported Tools

Tool	Synthesis	Simulation
Xilinx ISE	Yes	n.a.
Xilinx PlanAhead	Yes	No
Altera Quartus	Yes	n.a.
Microsemi (Actel) Libero	Yes	n.a.
Lattice Semi. Diamond	Yes	n.a.
Xilinx ISim	Yes	n.a.
Mentor Graphics Modelsim	n.a.	Yes
Aldec Active-HDL	n.a.	Yes
Icarus Verilog	n.a.	Verilog
GHDL	n.a.	VHDL

Supported Operating Systems

hdlmake is supported in both 32 and 64 bits operating systems.

Operating System	Comments
Linux	tested on Ubuntu Precise/Trusty, CentOS 6/7
Windows	tested on Windows 7/8/8.1 by using Cygwin

Supported Python Version

Version	Comments
Python 2	Runs on 2.7.x
Python 3	To be done, not supported yet

Installing hdlmake

Linux deployment

hdlmake is a Python application and, in order to allow an agile development and customization, is not distributed as a packaged executable file, but as a set of Python source files. In this way, there is no need to build hdlmake, as the Python code gets interpreted on the fly. In order to run hdlmake as a shell command, the next process has to be followed.

As a prerequisite, you must have the following programs installed in your host machine:

• python: you need a compatible Python deployment
• git: you need git for both fetching the hdlmake code and accessing to remote HDL repositories.
• svn: svn will only be used when accessing to remote SVN HDL repositories.

Now, you need to fetch the code from the official hdlmake git repository, that can be found at the next link: http://www.ohwr.org/projects/hdl-make/repository

Once you have a valid hdlmake source tree, you need to create a launch script in /usr/bin or any other available location at shell $PATH. You can name the script as you prefer so, by doing this, multiple hdlmake versions can easily be used in the same machine. In any case, in this documentation we will consider that the name for this launch script is just hdlmake.

#!/usr/bin/env bash
python2.7 /path_to_hdlmake_sources/hdl-make/hdlmake/__main__.py $@

here:

• python2.7 is the executable of the Python deployment we want to use with hdlmake.
• path_to_hdlmake_sources is the absolute path in which the hdlmake source code has been fetched.
• hdl-make is the name of the folder created when you checked out the repo.
• hdlmake is the subfolder of hdl-make (this is not binary or a file, this is folder name).

Once the launch script has been created, the appropriated execution rights must be set:

chmod +x /usr/bin/hdlmake

Windows specific guidelines

Despite the fact that hdlmake was originally designed to be used in Linux environments, the new release of the tool has been modified to be easily used in both 32 and 64 bits Windows Operating Systems inside a Cygwin deployment. In this way, you must just follow the next steps to be able to run hdlmake.

First, install a valid Cygwin environment for your Windows machine. I order to access to the full set of features from hdlmake, you must choose at least the following packages when deploying Cygwin:

• python (choose the most updated 2.7 release)
• openssh
• git-svn
• git
• curl
• make

Once you have installed your Cygwin environment, you can just get into the Cygwin console and operate as if you were inside a Linux machine for both installing and working with hdlmake.

Environment ----------_

When working in Linux or Windows inside Cygwin, in order to work with hdlmake we must assure that the tools executables that are going to be used are accessibles in the shell $PATH. This is a requirement for both simulation and synthesis

..warning:: there is another way to define the specific tools as an environmental variable, but this is buggy and fails when executing some of the actions. The $PATH way is the most easy and stable way to go!

Learn by example

As a companion of hdlmake, we can find a folder containing some easy design examples that can serve us as both tests and design templates. This folder is named hdl-make/tests/``and is automatically downloaded when the ``hdlmake git repository is fetched.

Overview

Inside the tests folder, you'll find a project called counter. This project has been specifically designed to serve as an easy template/test for the following features:

• Testbench simulation
• Bitstream synthesis
• Verilog/VHDL support

The first level of the counter directory structure is the following:

user@host:~$ tree -d -L 1 counter/
counter/
|-- modules
|-- sim
|-- syn
|-- testbench
`-- top

where each folder has the following role:

• modules contains the code of the design, a very simple 8-bit counter.
• sim contain a set of top manifests targeted to simulation by using different tools.
• syn contain a set of top manifests targeted to synthesis by using different tools.
• testbench contains a testbench for the design, covering the 8-bit counter.
• top contains a top module wrapper attaching the counter design to the pushbuttons & LEDs of a real FPGA design.

For each simulation or synthesis that can be executed, we have both Verilog and VHDL source codes for the module, testbench and top. So in every of the previous folder, we will have as children a verilog and an vhdl folder (note that ghdl only supports VHDL and iverilog only supports Verilog).

The simplest hdlmake module

If we take a deeper look to the modules folder we find that we really have two different hdlmake modules, one describing the counter as Verilog and other as VHDL.

user@host:~$ tree counter/modules/
counter/modules/
`-- counter
    |-- verilog
    |   |-- counter.v
    |   `-- Manifest.py
    `-- vhdl
        |-- counter.vhd
        `-- Manifest.py

Each of the modules contains a single file, so in the VHDL case the associated Manifest.py is just:

files = [
    "counter.vhd",
]

While in the Verilog one the Manifest.py is:

files = [
    "counter.v",
]

A basic testbench

Now, if we focus on the testbench folder, we have that we have again two modules, targeted to cover both the VHDL and the Verilog based counter modules we have just seen.

user@host:~$ tree counter/testbench/
counter/testbench/
`-- counter_tb
    |-- verilog
    |   |-- counter_tb.v
    |   `-- Manifest.py
    `-- vhdl
        |-- counter_tb.vhd
        `-- Manifest.py

Each of the modules contains a single testbench file written in the appropriated language, but in order to define the real project structure, the Manifest.py must include a reference to the modules under test. Thus, in the case of VHDL, the Manifest.py is:

files = [
    "counter_tb.vhd",
]

modules = {
    "local" : [ "../../../modules/counter/vhdl" ],
}

While in Verilog the Manifest.py is:

files = [

"counter_tb.v",

]

modules = {

"local" : [ "../../../modules/counter/verilog" ],

}

Note that, in both cases, the children modules are local.

Running a simulation

Now, we have all that we need to run a simulation for our simple design. If we take a look to the sim folder contents, we see that there is one folder for each of the supported simulations tools:

user@host:~$ tree -d -L 1 counter/sim
counter/sim
|-- aldec
|-- ghdl
|-- isim
|-- iverilog
`-- modelsim

As an example, let's focus on the modelsim folder:

user@host:~$ tree counter/sim/modelsim/
counter/sim/modelsim/
|-- verilog
|   `-- Manifest.py
|-- vhdl
|   `-- Manifest.py
`-- vsim.do

We can see that there is a top Manifest.py for both Verilog and VHDL languages. In addition, we have a vsim.do file that contains Modelsim specific commands that are common for both HDL languages.

In the VHDL case, the top Manifest.py for Modelsim simulation is:

action = "simulation"
sim_tool = "modelsim"
top_module = "counter_tb"

sim_post_cmd = "vsim -do ../vsim.do -i counter_tb"

modules = {
    "local" : [ "../../../testbench/counter_tb/vhdl" ],
}

And in the Verilog case, the associated Manifest.py is:

action = "simulation"
sim_tool = "modelsim"
top_module = "counter_tb"

sim_post_cmd = "vsim -do ../vsim.do -i counter_tb"

modules = {
    "local" : [ "../../../testbench/counter_tb/verilog" ],
}

In both cases, we can see that the modules parameter points to the specific VHDL or Verilog testbench, while the other fields remain the same for both of the languages.

The following common top specific Manifest variables describes the simulation:

• action: indicates that we are going to perform a simulation.
• sim_tool: indicates that modelsim is going to be the simulation we are going to use.
• top_module: indicates the name of the top HDL entity/instance that is going to be simulated.
• sim_post_cmd: indicates a command that can be issued after the simulation process has finnished.

Now, if we want to launch the simulation, we must follow the next steps. First, get into the folder containing the top Manifest.py we want to execute and run hdlmake without arguments. e.g. for VHDL:

user@host:~$ cd counter/sim/modelsim/vhdl
user@host:~$ hdlmake

This generates a simulation Makefile that can be executed by issuing the well known make command. When doing this, the appropriated HDL files are compiled in order following the hierachy described in the modules/Manifest.py tree. Now, once the design is compiled, if we want to run an actual simulation we need to issue a specific Modelsim command:

user@host:~$ make
user@host:~$ vsim -do ../vsim.do -i counter_tb

But, because we have already defined a post simulation command into the Manifest.py, the generated Makefile allows us to combine the compilation and the test run in a single command:

user@host:~$ make sim_post_cmd

If everything goes well, a graphical viewer should appear showing the simulated waveform. Note that every simulation top Manifest.py in the sim folder includes a tool specific sim_post_command, so all the simulations in this example can be generated by using the same simple command sequence that has been exposed here.

Constraining a design for synthesis