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Gennum GN4124 core
Commit f6d26f73 authored by Tristan Gingold's avatar Tristan Gingold
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p2l_dma_master: more refactoring

parent 241e4a45
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Showing with 36 additions and 56 deletions
hdl/rtl/p2l_dma_master.vhd
View file @ f6d26f73
......@@ -193,21 +193,37 @@ begin
-- Errors to DMA controller
dma_ctrl_error_o <= dma_busy_error or completion_error;
------------------------------------------------------------------------------
-- PCIe read request
------------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- PCIe read request FSM
-----------------------------------------------------------------------------
-- Stores information for read request packet
-- Can be a P2L DMA transfer or catching the next item of a chained DMA
p_read_req : process (clk_i)
p_read_req_fsm : process (clk_i)
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') then
l2p_64b_address <= '0';
is_next_item <= '0';
l2p_last_packet <= '0';
if rst_n_i = '0' then
p2l_dma_current_state <= P2L_IDLE;
pdm_arb_req_o <= '0';
pdm_arb_valid_o <= '0';
pdm_arb_dframe_o <= '0';
dma_ctrl_done_t <= '0';
next_item_valid_o <= '0';
completion_error <= '0';
rx_error_t <= '0';
l2p_64b_address <= '0';
is_next_item <= '0';
l2p_last_packet <= '0';
else
case p2l_dma_current_state is
when P2L_IDLE =>
-- Clear status bits
dma_ctrl_done_t <= '0';
next_item_valid_o <= '0';
completion_error <= '0';
rx_error_t <= '0';
-- Start a read request when a P2L DMA is initated or when the DMA
-- controller asks for the next DMA info (in a chained DMA).
if dma_ctrl_start_p2l_i = '1' or dma_ctrl_start_next_i = '1' then
-- Stores DMA info locally
l2p_address_h <= dma_ctrl_host_addr_h_i;
......@@ -225,7 +241,12 @@ begin
else
l2p_64b_address <= '1';
end if;
-- request access to PCIe bus
pdm_arb_req_o <= '1';
-- prepare a packet, first the header
p2l_dma_current_state <= P2L_HEADER;
end if;
when P2L_HEADER =>
-- if DMA length is bigger than the max PCIe payload size,
-- we have to generate several read request
......@@ -237,55 +258,7 @@ begin
l2p_len_header <= l2p_len_cnt(9 downto 0);
l2p_last_packet <= '1';
end if;
when P2L_ADDR_L =>
-- Subtract the number of word requested to generate a new read request if needed
if l2p_last_packet = '0' then
l2p_len_cnt <= l2p_len_cnt - c_MAX_READ_REQ_SIZE;
else
l2p_len_cnt <= (others => '0');
end if;
when P2L_ADDR_H =>
null;
when P2L_WAIT_READ_COMPLETION =>
end case;
end if;
end if;
end process p_read_req;
-----------------------------------------------------------------------------
-- PCIe read request FSM
-----------------------------------------------------------------------------
p_read_req_fsm : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
p2l_dma_current_state <= P2L_IDLE;
pdm_arb_req_o <= '0';
pdm_arb_valid_o <= '0';
pdm_arb_dframe_o <= '0';
dma_ctrl_done_t <= '0';
next_item_valid_o <= '0';
completion_error <= '0';
rx_error_t <= '0';
else
case p2l_dma_current_state is
when P2L_IDLE =>
-- Clear status bits
dma_ctrl_done_t <= '0';
next_item_valid_o <= '0';
completion_error <= '0';
rx_error_t <= '0';
-- Start a read request when a P2L DMA is initated or when the DMA
-- controller asks for the next DMA info (in a chained DMA).
if dma_ctrl_start_p2l_i = '1' or dma_ctrl_start_next_i = '1' then
-- request access to PCIe bus
pdm_arb_req_o <= '1';
-- prepare a packet, first the header
p2l_dma_current_state <= P2L_HEADER;
end if;
when P2L_HEADER =>
if arb_pdm_gnt_i = '1' then
-- clear access request to the arbiter
-- access is granted until dframe is cleared
......@@ -323,6 +296,13 @@ begin
p2l_dma_current_state <= P2L_ADDR_L;
when P2L_ADDR_L =>
-- Subtract the number of word requested to generate a new read request if needed
if l2p_last_packet = '0' then
l2p_len_cnt <= l2p_len_cnt - c_MAX_READ_REQ_SIZE;
else
l2p_len_cnt <= (others => '0');
end if;
-- send host address 32 lowest bits
pdm_arb_data <= l2p_address_l;
-- clear dframe signal to indicate the end of packet
......
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