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Gennum GN4124 core
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Gennum GN4124 core
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f26b97a5
Commit
f26b97a5
authored
Jan 31, 2014
by
Matthieu Cattin
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Update README file with memory map.
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README
hdl/spec/syn/README
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hdl/spec/syn/README
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f26b97a5
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@@ -6,9 +6,23 @@ files section of the project:
http://www.ohwr.org/projects/gn4124-core/files
Procedure to generate the gateware binary:
$ cd <gn4124 core dir>/hdl/spec/syn/
$ hdlmake -f
$ hdlmake --ise-proj
$ hdlmake --make-ise
$ make
cd <gn4124 core dir>/hdl/spec/syn/
hdlmake -f
hdlmake --ise-proj
hdlmake --make-ise
make
\ No newline at end of file
Memory map:
0x00000 : GN4124 DMA configuration registers
-> See GN4124 doc for register mapping.
0x40000 : Status registers
0 : 0xDEADBABE
4 : 0xBEEFFACE
8 : 0x12345678
C : Bit 0 = P2L PLL lock status (1=pll locked)
0x80000 : Control regiters
0 : Not connected internally, can be used to perform r/w
4 : Not connected internally, can be used to perform r/w
8 : Not connected internally, can be used to perform r/w
C : Bits 0 and 1 connected to SPEC front-panel LEDs (1=LED ON)
\ No newline at end of file
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