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Gennum GN4124 core
Commit d0c2399b authored by Dimitris Lampridis's avatar Dimitris Lampridis Committed by Dimitris Lampridis
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hdl: DMA rewrite work-in-progress.

parent 386c2ae9
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general-cores @ 64f7e518
Subproject commit 284373b7ea1db559dd323634dd34a8dba1811c12 Subproject commit 64f7e518bab2bf0489077f4b9eb26e8cccbf1411
hdl/rtl/dma_controller.vhd
View file @ d0c2399b
...@@ -306,10 +306,10 @@ begin ...@@ -306,10 +306,10 @@ begin
dma_stat_reg <= c_DMA_STAT_ERROR; dma_stat_reg <= c_DMA_STAT_ERROR;
dma_ctrl_current_state <= DMA_IDLE; dma_ctrl_current_state <= DMA_IDLE;
else else
-- Start the DMA if the length is not 0
if dma_attrib_dir_reg = '0' then if dma_attrib_dir_reg = '0' then
-- L2P transfer (from target to PCIe) -- L2P transfer (from target to PCIe)
dma_ctrl_start_l2p_o <= '1'; dma_ctrl_start_l2p_o <= '1';
dma_ctrl_direction_o <= '0';
else else
-- P2L transfer (from PCIe to target) -- P2L transfer (from PCIe to target)
dma_ctrl_start_p2l_o <= '1'; dma_ctrl_start_p2l_o <= '1';
......
hdl/rtl/l2p_dma_master.vhd
View file @ d0c2399b
This diff is collapsed.
hdl/rtl/spartan6/gn4124_core.vhd
View file @ d0c2399b
...@@ -9,7 +9,7 @@ ...@@ -9,7 +9,7 @@
-- description: GN4124 core top level. Version for spartan6 FPGAs. -- description: GN4124 core top level. Version for spartan6 FPGAs.
-- --
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
-- Copyright CERN 2010-2019 -- Copyright CERN 2010-2020
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
-- Copyright and related rights are licensed under the Solderpad Hardware -- Copyright and related rights are licensed under the Solderpad Hardware
-- License, Version 2.0 (the "License"); you may not use this file except -- License, Version 2.0 (the "License"); you may not use this file except
...@@ -25,8 +25,10 @@ ...@@ -25,8 +25,10 @@
library IEEE; library IEEE;
use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all; use IEEE.NUMERIC_STD.all;
use work.gn4124_core_pkg.all; use work.gn4124_core_pkg.all;
use work.gencores_pkg.all; use work.gencores_pkg.all;
use work.wishbone_pkg.all;
library UNISIM; library UNISIM;
use UNISIM.vcomponents.all; use UNISIM.vcomponents.all;
...@@ -39,6 +41,11 @@ entity gn4124_core is ...@@ -39,6 +41,11 @@ entity gn4124_core is
generic ( generic (
-- If TRUE, enable the DMA interface -- If TRUE, enable the DMA interface
g_WITH_DMA : boolean := TRUE; g_WITH_DMA : boolean := TRUE;
-- if TRUE, use 200MHz PCI clock also for DMA transfers.
-- if FALSE, use whatever is provided by the user on dma_clk_i,
-- which is assumed to be asynchronous to the PCI clock and goes
-- through dual clock FIFOs.
g_DMA_USE_PCI_CLK : boolean := FALSE;
-- Tunable size and threshold for all async FIFOs. -- Tunable size and threshold for all async FIFOs.
-- If not sure, leave the defaults. -- If not sure, leave the defaults.
g_WBM_TO_WB_FIFO_SIZE : positive := 128; g_WBM_TO_WB_FIFO_SIZE : positive := 128;
...@@ -47,10 +54,7 @@ entity gn4124_core is ...@@ -47,10 +54,7 @@ entity gn4124_core is
g_WBM_FROM_WB_FIFO_FULL_THRES : positive := 110; g_WBM_FROM_WB_FIFO_FULL_THRES : positive := 110;
g_P2L_FIFO_SIZE : positive := 512; g_P2L_FIFO_SIZE : positive := 512;
g_P2L_FIFO_FULL_THRES : positive := 500; g_P2L_FIFO_FULL_THRES : positive := 500;
g_L2P_ADDR_FIFO_FULL_SIZE : positive := 1024; g_L2P_DATA_FIFO_SIZE : positive := 128;
g_L2P_ADDR_FIFO_FULL_THRES : positive := 700;
g_L2P_DATA_FIFO_FULL_SIZE : positive := 1024;
g_L2P_DATA_FIFO_FULL_THRES : positive := 700;
-- Wishbone ACK timeout (in wishbone clock cycles) -- Wishbone ACK timeout (in wishbone clock cycles)
g_ACK_TIMEOUT : positive := 100); g_ACK_TIMEOUT : positive := 100);
port ( port (
...@@ -59,6 +63,11 @@ entity gn4124_core is ...@@ -59,6 +63,11 @@ entity gn4124_core is
rst_n_a_i : in std_logic; -- Asynchronous reset from GN4124 rst_n_a_i : in std_logic; -- Asynchronous reset from GN4124
status_o : out std_logic_vector(31 downto 0); -- Core status output status_o : out std_logic_vector(31 downto 0); -- Core status output
---------------------------------------------------------
-- 200MHz PCI clock output and synchronous reset for applications
clk_200m_o : out std_logic;
rst_200m_n_o : out std_logic;
--------------------------------------------------------- ---------------------------------------------------------
-- P2L Direction -- P2L Direction
-- --
...@@ -170,6 +179,9 @@ architecture rtl of gn4124_core is ...@@ -170,6 +179,9 @@ architecture rtl of gn4124_core is
signal sys_rst_n : std_logic; signal sys_rst_n : std_logic;
signal arst_pll : std_logic; signal arst_pll : std_logic;
signal wb_dma_clk : std_logic;
signal wb_dma_rst_n : std_logic;
------------------------------------------------------------- -------------------------------------------------------------
-- P2L DataPath (from deserializer to packet decoder) -- P2L DataPath (from deserializer to packet decoder)
------------------------------------------------------------- -------------------------------------------------------------
...@@ -277,6 +289,19 @@ architecture rtl of gn4124_core is ...@@ -277,6 +289,19 @@ architecture rtl of gn4124_core is
signal dma_irq : std_logic; signal dma_irq : std_logic;
attribute keep of dma_ctrl_l2p_error : signal is "TRUE";
attribute keep of dma_ctrl_l2p_done : signal is "TRUE";
attribute keep of dma_ctrl_start_l2p : signal is "TRUE";
attribute keep of dma_ctrl_abort : signal is "TRUE";
attribute keep of ldm_arb_valid : signal is "TRUE";
attribute keep of ldm_arb_dframe : signal is "TRUE";
attribute keep of ldm_arb_data : signal is "TRUE";
attribute keep of ldm_arb_req : signal is "TRUE";
attribute keep of l2p_rdy : signal is "TRUE";
attribute keep of l_wr_rdy : signal is "TRUE";
attribute keep of tx_error : signal is "TRUE";
attribute keep of arb_ldm_gnt : signal is "TRUE";
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
-- CSR wishbone bus -- CSR wishbone bus
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
...@@ -285,14 +310,8 @@ architecture rtl of gn4124_core is ...@@ -285,14 +310,8 @@ architecture rtl of gn4124_core is
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
-- DMA wishbone bus -- DMA wishbone bus
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
signal l2p_dma_adr : std_logic_vector(31 downto 0); signal l2p_dma_in : t_wishbone_master_in;
signal l2p_dma_dat : std_logic_vector(31 downto 0); signal l2p_dma_out : t_wishbone_master_out;
signal l2p_dma_sel : std_logic_vector(3 downto 0);
signal l2p_dma_cyc : std_logic;
signal l2p_dma_stb : std_logic;
signal l2p_dma_we : std_logic;
signal l2p_dma_ack : std_logic;
signal l2p_dma_stall : std_logic;
signal p2l_dma_adr : std_logic_vector(31 downto 0); signal p2l_dma_adr : std_logic_vector(31 downto 0);
signal p2l_dma_dat : std_logic_vector(31 downto 0); signal p2l_dma_dat : std_logic_vector(31 downto 0);
...@@ -352,6 +371,9 @@ begin ...@@ -352,6 +371,9 @@ begin
clks_i(0) => sys_clk, clks_i(0) => sys_clk,
rst_n_o(0) => sys_rst_n); rst_n_o(0) => sys_rst_n);
clk_200m_o <= sys_clk;
rst_200m_n_o <= sys_rst_n;
-- Always active high reset for PLL and SERDES -- Always active high reset for PLL and SERDES
arst_pll <= not(rst_n_a_i); arst_pll <= not(rst_n_a_i);
...@@ -360,6 +382,19 @@ begin ...@@ -360,6 +382,19 @@ begin
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
irq_p_o <= irq_p_i; irq_p_o <= irq_p_i;
------------------------------------------------------------------------------
-- DMA WB clock and reset selection
------------------------------------------------------------------------------
gen_sync_wb_dma : if g_DMA_USE_PCI_CLK = TRUE generate
wb_dma_clk <= sys_clk;
wb_dma_rst_n <= sys_rst_n;
end generate gen_sync_wb_dma;
gen_async_wb_dma : if g_DMA_USE_PCI_CLK = FALSE generate
wb_dma_clk <= dma_clk_i;
wb_dma_rst_n <= dma_rst_n_i;
end generate gen_async_wb_dma;
--============================================================================ --============================================================================
-- P2L DataPath -- P2L DataPath
--============================================================================ --============================================================================
...@@ -583,11 +618,9 @@ begin ...@@ -583,11 +618,9 @@ begin
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
cmp_l2p_dma_master : entity work.l2p_dma_master cmp_l2p_dma_master : entity work.l2p_dma_master
generic map ( generic map (
g_ADDR_FIFO_FULL_SIZE => g_L2P_ADDR_FIFO_FULL_SIZE, g_DMA_USE_PCI_CLK => g_DMA_USE_PCI_CLK,
g_ADDR_FIFO_FULL_THRES => g_L2P_ADDR_FIFO_FULL_THRES, g_DATA_FIFO_SIZE => g_L2P_DATA_FIFO_SIZE,
g_DATA_FIFO_FULL_SIZE => g_L2P_DATA_FIFO_FULL_SIZE, g_BYTE_SWAP => TRUE)
g_DATA_FIFO_FULL_THRES => g_L2P_DATA_FIFO_FULL_THRES,
g_BYTE_SWAP => TRUE)
port map ( port map (
clk_i => sys_clk, clk_i => sys_clk,
rst_n_i => sys_rst_n, rst_n_i => sys_rst_n,
...@@ -606,30 +639,28 @@ begin ...@@ -606,30 +639,28 @@ begin
ldm_arb_dframe_o => ldm_arb_dframe, ldm_arb_dframe_o => ldm_arb_dframe,
ldm_arb_data_o => ldm_arb_data, ldm_arb_data_o => ldm_arb_data,
ldm_arb_req_o => ldm_arb_req, ldm_arb_req_o => ldm_arb_req,
arb_ldm_gnt_i => arb_ldm_gnt, ldm_arb_gnt_i => arb_ldm_gnt,
l2p_edb_o => l2p_edb, l2p_edb_o => l2p_edb,
l_wr_rdy_i => l_wr_rdy, l_wr_rdy_i => l_wr_rdy,
l2p_rdy_i => l2p_rdy, l2p_rdy_i => l2p_rdy,
tx_error_i => tx_error, tx_error_i => tx_error,
l2p_dma_rst_n_i => dma_rst_n_i, wb_dma_rst_n_i => wb_dma_rst_n,
l2p_dma_clk_i => dma_clk_i, wb_dma_clk_i => wb_dma_clk,
l2p_dma_adr_o => l2p_dma_adr, wb_dma_i => l2p_dma_in,
l2p_dma_dat_i => dma_dat_i, wb_dma_o => l2p_dma_out);
l2p_dma_dat_o => l2p_dma_dat,
l2p_dma_sel_o => l2p_dma_sel, l2p_dma_in.dat <= dma_dat_i;
l2p_dma_cyc_o => l2p_dma_cyc, l2p_dma_in.err <= dma_err_i;
l2p_dma_stb_o => l2p_dma_stb, l2p_dma_in.rty <= dma_rty_i;
l2p_dma_we_o => l2p_dma_we,
l2p_dma_ack_i => l2p_dma_ack,
l2p_dma_stall_i => l2p_dma_stall);
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
-- P2L DMA master -- P2L DMA master
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
cmp_p2l_dma_master : entity work.p2l_dma_master cmp_p2l_dma_master : entity work.p2l_dma_master
generic map ( generic map (
--g_DMA_USE_PCI_CLK => g_DMA_USE_PCI_CLK,
g_FIFO_SIZE => g_P2L_FIFO_SIZE, g_FIFO_SIZE => g_P2L_FIFO_SIZE,
g_FIFO_FULL_THRES => g_P2L_FIFO_FULL_THRES, g_FIFO_FULL_THRES => g_P2L_FIFO_FULL_THRES,
g_BYTE_SWAP => TRUE) g_BYTE_SWAP => TRUE)
...@@ -691,32 +722,31 @@ begin ...@@ -691,32 +722,31 @@ begin
); );
p_dma_wb_mux : process (dma_ack_i, dma_ctrl_direction, dma_stall_i, p_dma_wb_mux : process (dma_ack_i, dma_ctrl_direction, dma_stall_i,
l2p_dma_adr, l2p_dma_cyc, l2p_dma_dat, l2p_dma_sel, l2p_dma_out, p2l_dma_adr, p2l_dma_cyc, p2l_dma_dat,
l2p_dma_stb, l2p_dma_we, p2l_dma_adr, p2l_dma_cyc, p2l_dma_sel, p2l_dma_stb, p2l_dma_we)
p2l_dma_dat, p2l_dma_sel, p2l_dma_stb, p2l_dma_we)
begin begin
if (dma_ctrl_direction = '0') then if (dma_ctrl_direction = '0') then
dma_adr_o <= l2p_dma_adr; dma_adr_o <= l2p_dma_out.adr;
dma_dat_o <= l2p_dma_dat; dma_dat_o <= l2p_dma_out.dat;
dma_sel_o <= l2p_dma_sel; dma_sel_o <= l2p_dma_out.sel;
dma_cyc_o <= l2p_dma_cyc; dma_cyc_o <= l2p_dma_out.cyc;
dma_stb_o <= l2p_dma_stb; dma_stb_o <= l2p_dma_out.stb;
dma_we_o <= l2p_dma_we; dma_we_o <= l2p_dma_out.we;
l2p_dma_ack <= dma_ack_i; l2p_dma_in.ack <= dma_ack_i;
l2p_dma_stall <= dma_stall_i; l2p_dma_in.stall <= dma_stall_i;
p2l_dma_ack <= '0'; p2l_dma_ack <= '0';
p2l_dma_stall <= '0'; p2l_dma_stall <= '0';
else else
dma_adr_o <= p2l_dma_adr; dma_adr_o <= p2l_dma_adr;
dma_dat_o <= p2l_dma_dat; dma_dat_o <= p2l_dma_dat;
dma_sel_o <= p2l_dma_sel; dma_sel_o <= p2l_dma_sel;
dma_cyc_o <= p2l_dma_cyc; dma_cyc_o <= p2l_dma_cyc;
dma_stb_o <= p2l_dma_stb; dma_stb_o <= p2l_dma_stb;
dma_we_o <= p2l_dma_we; dma_we_o <= p2l_dma_we;
p2l_dma_ack <= dma_ack_i; p2l_dma_ack <= dma_ack_i;
p2l_dma_stall <= dma_stall_i; p2l_dma_stall <= dma_stall_i;
l2p_dma_ack <= '0'; l2p_dma_in.ack <= '0';
l2p_dma_stall <= '0'; l2p_dma_in.stall <= '0';
end if; end if;
end process p_dma_wb_mux; end process p_dma_wb_mux;
......
hdl/rtl/spartan6/gn4124_core_pkg.vhd
View file @ d0c2399b
...@@ -56,16 +56,14 @@ package gn4124_core_pkg is ...@@ -56,16 +56,14 @@ package gn4124_core_pkg is
component xwb_gn4124_core is component xwb_gn4124_core is
generic ( generic (
g_WITH_DMA : boolean := TRUE; g_WITH_DMA : boolean := TRUE;
g_DMA_USE_PCI_CLK : boolean := FALSE;
g_WBM_TO_WB_FIFO_SIZE : positive := 128; g_WBM_TO_WB_FIFO_SIZE : positive := 128;
g_WBM_TO_WB_FIFO_FULL_THRES : positive := 110; g_WBM_TO_WB_FIFO_FULL_THRES : positive := 110;
g_WBM_FROM_WB_FIFO_SIZE : positive := 128; g_WBM_FROM_WB_FIFO_SIZE : positive := 128;
g_WBM_FROM_WB_FIFO_FULL_THRES : positive := 110; g_WBM_FROM_WB_FIFO_FULL_THRES : positive := 110;
g_P2L_FIFO_SIZE : positive := 512; g_P2L_FIFO_SIZE : positive := 512;
g_P2L_FIFO_FULL_THRES : positive := 500; g_P2L_FIFO_FULL_THRES : positive := 500;
g_L2P_ADDR_FIFO_FULL_SIZE : positive := 1024; g_L2P_DATA_FIFO_SIZE : positive := 128;
g_L2P_ADDR_FIFO_FULL_THRES : positive := 700;
g_L2P_DATA_FIFO_FULL_SIZE : positive := 1024;
g_L2P_DATA_FIFO_FULL_THRES : positive := 700;
g_WB_MASTER_MODE : t_wishbone_interface_mode := PIPELINED; g_WB_MASTER_MODE : t_wishbone_interface_mode := PIPELINED;
g_WB_MASTER_GRANULARITY : t_wishbone_address_granularity := BYTE; g_WB_MASTER_GRANULARITY : t_wishbone_address_granularity := BYTE;
g_WB_DMA_CFG_MODE : t_wishbone_interface_mode := PIPELINED; g_WB_DMA_CFG_MODE : t_wishbone_interface_mode := PIPELINED;
...@@ -76,6 +74,8 @@ package gn4124_core_pkg is ...@@ -76,6 +74,8 @@ package gn4124_core_pkg is
port ( port (
rst_n_a_i : in std_logic; rst_n_a_i : in std_logic;
status_o : out std_logic_vector(31 downto 0); status_o : out std_logic_vector(31 downto 0);
clk_200m_o : out std_logic;
rst_200m_n_o : out std_logic;
p2l_clk_p_i : in std_logic; p2l_clk_p_i : in std_logic;
p2l_clk_n_i : in std_logic; p2l_clk_n_i : in std_logic;
p2l_data_i : in std_logic_vector(15 downto 0); p2l_data_i : in std_logic_vector(15 downto 0);
...@@ -117,16 +117,14 @@ package gn4124_core_pkg is ...@@ -117,16 +117,14 @@ package gn4124_core_pkg is
component gn4124_core component gn4124_core
generic ( generic (
g_WITH_DMA : boolean := TRUE; g_WITH_DMA : boolean := TRUE;
g_DMA_USE_PCI_CLK : boolean := FALSE;
g_WBM_TO_WB_FIFO_SIZE : positive := 128; g_WBM_TO_WB_FIFO_SIZE : positive := 128;
g_WBM_TO_WB_FIFO_FULL_THRES : positive := 110; g_WBM_TO_WB_FIFO_FULL_THRES : positive := 110;
g_WBM_FROM_WB_FIFO_SIZE : positive := 128; g_WBM_FROM_WB_FIFO_SIZE : positive := 128;
g_WBM_FROM_WB_FIFO_FULL_THRES : positive := 110; g_WBM_FROM_WB_FIFO_FULL_THRES : positive := 110;
g_P2L_FIFO_SIZE : positive := 512; g_P2L_FIFO_SIZE : positive := 512;
g_P2L_FIFO_FULL_THRES : positive := 500; g_P2L_FIFO_FULL_THRES : positive := 500;
g_L2P_ADDR_FIFO_FULL_SIZE : positive := 1024; g_L2P_DATA_FIFO_SIZE : positive := 128;
g_L2P_ADDR_FIFO_FULL_THRES : positive := 700;
g_L2P_DATA_FIFO_FULL_SIZE : positive := 1024;
g_L2P_DATA_FIFO_FULL_THRES : positive := 700;
g_ACK_TIMEOUT : positive := 100); g_ACK_TIMEOUT : positive := 100);
port ( port (
--------------------------------------------------------- ---------------------------------------------------------
...@@ -134,6 +132,11 @@ package gn4124_core_pkg is ...@@ -134,6 +132,11 @@ package gn4124_core_pkg is
rst_n_a_i : in std_logic; -- Asynchronous reset from GN4124 rst_n_a_i : in std_logic; -- Asynchronous reset from GN4124
status_o : out std_logic_vector(31 downto 0); -- Core status output status_o : out std_logic_vector(31 downto 0); -- Core status output
---------------------------------------------------------
-- 200MHz PCI clock output and synchronous reset for applications
clk_200m_o : out std_logic;
rst_200m_n_o : out std_logic;
--------------------------------------------------------- ---------------------------------------------------------
-- P2L Direction -- P2L Direction
-- --
......
hdl/rtl/spartan6/xwb_gn4124_core.vhd
View file @ d0c2399b
...@@ -11,7 +11,7 @@ ...@@ -11,7 +11,7 @@
-- Version for Spartan6 FPGAs. -- Version for Spartan6 FPGAs.
-- --
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
-- Copyright CERN 2018 -- Copyright CERN 2018 - 2020
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
-- Copyright and related rights are licensed under the Solderpad Hardware -- Copyright and related rights are licensed under the Solderpad Hardware
-- License, Version 2.0 (the "License"); you may not use this file except -- License, Version 2.0 (the "License"); you may not use this file except
...@@ -34,6 +34,11 @@ entity xwb_gn4124_core is ...@@ -34,6 +34,11 @@ entity xwb_gn4124_core is
generic ( generic (
-- If TRUE, enable the DMA interface -- If TRUE, enable the DMA interface
g_WITH_DMA : boolean := TRUE; g_WITH_DMA : boolean := TRUE;
-- if TRUE, use 200MHz PCI clock also for DMA transfers.
-- if FALSE, use whatever is provided by the user on dma_clk_i,
-- which is assumed to be asynchronous to the PCI clock and goes
-- through dual clock FIFOs.
g_DMA_USE_PCI_CLK : boolean := FALSE;
-- Tunable size and threshold for all async FIFOs. -- Tunable size and threshold for all async FIFOs.
-- If not sure, leave the defaults. -- If not sure, leave the defaults.
g_WBM_TO_WB_FIFO_SIZE : positive := 128; g_WBM_TO_WB_FIFO_SIZE : positive := 128;
...@@ -42,10 +47,7 @@ entity xwb_gn4124_core is ...@@ -42,10 +47,7 @@ entity xwb_gn4124_core is
g_WBM_FROM_WB_FIFO_FULL_THRES : positive := 110; g_WBM_FROM_WB_FIFO_FULL_THRES : positive := 110;
g_P2L_FIFO_SIZE : positive := 512; g_P2L_FIFO_SIZE : positive := 512;
g_P2L_FIFO_FULL_THRES : positive := 500; g_P2L_FIFO_FULL_THRES : positive := 500;
g_L2P_ADDR_FIFO_FULL_SIZE : positive := 1024; g_L2P_DATA_FIFO_SIZE : positive := 128;
g_L2P_ADDR_FIFO_FULL_THRES : positive := 700;
g_L2P_DATA_FIFO_FULL_SIZE : positive := 1024;
g_L2P_DATA_FIFO_FULL_THRES : positive := 700;
-- WB config for three WB interfaces -- WB config for three WB interfaces
g_WB_MASTER_MODE : t_wishbone_interface_mode := PIPELINED; g_WB_MASTER_MODE : t_wishbone_interface_mode := PIPELINED;
g_WB_MASTER_GRANULARITY : t_wishbone_address_granularity := BYTE; g_WB_MASTER_GRANULARITY : t_wishbone_address_granularity := BYTE;
...@@ -61,6 +63,11 @@ entity xwb_gn4124_core is ...@@ -61,6 +63,11 @@ entity xwb_gn4124_core is
rst_n_a_i : in std_logic; -- Asynchronous reset from GN4124 rst_n_a_i : in std_logic; -- Asynchronous reset from GN4124
status_o : out std_logic_vector(31 downto 0); -- Core status output status_o : out std_logic_vector(31 downto 0); -- Core status output
---------------------------------------------------------
-- 200MHz PCI clock output and synchronous reset for applications
clk_200m_o : out std_logic;
rst_200m_n_o : out std_logic;
--------------------------------------------------------- ---------------------------------------------------------
-- P2L Direction -- P2L Direction
-- --
...@@ -191,20 +198,20 @@ begin ...@@ -191,20 +198,20 @@ begin
cmp_wrapped_gn4124 : gn4124_core cmp_wrapped_gn4124 : gn4124_core
generic map ( generic map (
g_WITH_DMA => g_WITH_DMA, g_WITH_DMA => g_WITH_DMA,
g_DMA_USE_PCI_CLK => g_DMA_USE_PCI_CLK,
g_WBM_TO_WB_FIFO_SIZE => g_WBM_TO_WB_FIFO_SIZE, g_WBM_TO_WB_FIFO_SIZE => g_WBM_TO_WB_FIFO_SIZE,
g_WBM_TO_WB_FIFO_FULL_THRES => g_WBM_TO_WB_FIFO_FULL_THRES, g_WBM_TO_WB_FIFO_FULL_THRES => g_WBM_TO_WB_FIFO_FULL_THRES,
g_WBM_FROM_WB_FIFO_SIZE => g_WBM_FROM_WB_FIFO_SIZE, g_WBM_FROM_WB_FIFO_SIZE => g_WBM_FROM_WB_FIFO_SIZE,
g_WBM_FROM_WB_FIFO_FULL_THRES => g_WBM_FROM_WB_FIFO_FULL_THRES, g_WBM_FROM_WB_FIFO_FULL_THRES => g_WBM_FROM_WB_FIFO_FULL_THRES,
g_P2L_FIFO_SIZE => g_P2L_FIFO_SIZE, g_P2L_FIFO_SIZE => g_P2L_FIFO_SIZE,
g_P2L_FIFO_FULL_THRES => g_P2L_FIFO_FULL_THRES, g_P2L_FIFO_FULL_THRES => g_P2L_FIFO_FULL_THRES,
g_L2P_ADDR_FIFO_FULL_SIZE => g_L2P_ADDR_FIFO_FULL_SIZE, g_L2P_DATA_FIFO_SIZE => g_L2P_DATA_FIFO_SIZE,
g_L2P_ADDR_FIFO_FULL_THRES => g_L2P_ADDR_FIFO_FULL_THRES,
g_L2P_DATA_FIFO_FULL_SIZE => g_L2P_DATA_FIFO_FULL_SIZE,
g_L2P_DATA_FIFO_FULL_THRES => g_L2P_DATA_FIFO_FULL_THRES,
g_ACK_TIMEOUT => g_ACK_TIMEOUT) g_ACK_TIMEOUT => g_ACK_TIMEOUT)
port map ( port map (
rst_n_a_i => rst_n_a_i, rst_n_a_i => rst_n_a_i,
status_o => status_o, status_o => status_o,
clk_200m_o => clk_200m_o,
rst_200m_n_o => rst_200m_n_o,
p2l_clk_p_i => p2l_clk_p_i, p2l_clk_p_i => p2l_clk_p_i,
p2l_clk_n_i => p2l_clk_n_i, p2l_clk_n_i => p2l_clk_n_i,
p2l_data_i => p2l_data_i, p2l_data_i => p2l_data_i,
......
hdl/sim/example_tb/main.sv
View file @ d0c2399b
...@@ -36,6 +36,7 @@ import wishbone_pkg::*; ...@@ -36,6 +36,7 @@ import wishbone_pkg::*;
module main; module main;
reg clk_125m = 0; reg clk_125m = 0;
reg clk_62m5 = 0;
logic gn4124_irq; logic gn4124_irq;
...@@ -43,19 +44,35 @@ module main; ...@@ -43,19 +44,35 @@ module main;
t_wishbone_master_out wb_out, wb_dma_out, wb_mem_out; t_wishbone_master_out wb_out, wb_dma_out, wb_mem_out;
always #4ns clk_125m <= ~clk_125m; always #4ns clk_125m <= ~clk_125m;
always #23ns clk_62m5 <= ~clk_62m5;
logic rst_125m_n; logic rst_125m_n;
logic rst_62m5_n;
logic rst_gn4124_n;
logic clk_gn4124;
logic wb_dma_clk;
logic wb_dma_rst_n;
initial begin initial begin
rst_125m_n = 0; rst_125m_n = 0;
#80ns rst_125m_n = 1; rst_62m5_n = 0;
#80ns;
rst_125m_n = 1;
rst_62m5_n = 1;
end end
IGN4124PCIMaster i_gn4124 (); IGN4124PCIMaster i_gn4124 ();
xwb_gn4124_core xwb_gn4124_core #
(
.g_dma_use_pci_clk (0)
)
DUT ( DUT (
.rst_n_a_i (i_gn4124.rst_n), .rst_n_a_i (i_gn4124.rst_n),
.clk_200m_o (clk_gn4124),
.rst_200m_n_o (rst_gn4124_n),
.p2l_clk_p_i (i_gn4124.p2l_clk_p), .p2l_clk_p_i (i_gn4124.p2l_clk_p),
.p2l_clk_n_i (i_gn4124.p2l_clk_n), .p2l_clk_n_i (i_gn4124.p2l_clk_n),
.p2l_data_i (i_gn4124.p2l_data), .p2l_data_i (i_gn4124.p2l_data),
...@@ -88,12 +105,21 @@ module main; ...@@ -88,12 +105,21 @@ module main;
.wb_dma_cfg_rst_n_i (rst_125m_n), .wb_dma_cfg_rst_n_i (rst_125m_n),
.wb_dma_cfg_i (wb_out), .wb_dma_cfg_i (wb_out),
.wb_dma_cfg_o (wb_in), .wb_dma_cfg_o (wb_in),
.wb_dma_dat_clk_i (clk_125m), .wb_dma_dat_clk_i (wb_dma_clk),
.wb_dma_dat_rst_n_i (rst_125m_n), .wb_dma_dat_rst_n_i (wb_dma_rst_n),
.wb_dma_dat_i (wb_dma_in), .wb_dma_dat_i (wb_dma_in),
.wb_dma_dat_o (wb_dma_out) .wb_dma_dat_o (wb_dma_out)
); );
/* -----\/----- EXCLUDED -----\/-----
assign wb_dma_clk = clk_gn4124;
assign wb_dma_rst_n = rst_gn4124_n;
assign wb_dma_clk = clk_125m;
assign wb_dma_rst_n = rst_125m_n;
-----/\----- EXCLUDED -----/\----- */
assign wb_dma_clk = clk_62m5;
assign wb_dma_rst_n = rst_62m5_n;
xwb_dpram # xwb_dpram #
( (
.g_size (32), .g_size (32),
...@@ -104,8 +130,8 @@ module main; ...@@ -104,8 +130,8 @@ module main;
.g_slave2_granularity (1) .g_slave2_granularity (1)
) )
MEM ( MEM (
.rst_n_i (1'b1), .rst_n_i (wb_dma_rst_n),
.clk_sys_i (clk_125m), .clk_sys_i (wb_dma_clk),
.slave1_i (wb_dma_out), .slave1_i (wb_dma_out),
.slave1_o (wb_dma_in), .slave1_o (wb_dma_in),
.slave2_i (wb_mem_out), .slave2_i (wb_mem_out),
...@@ -153,7 +179,7 @@ module main; ...@@ -153,7 +179,7 @@ module main;
initial begin initial begin
automatic int ntest = 1; automatic int ntest = 1;
const int tests = 8; const int tests = 9;
uint32_t addr, val, expected; uint32_t addr, val, expected;
...@@ -185,6 +211,7 @@ module main; ...@@ -185,6 +211,7 @@ module main;
$write("PASS\n"); $write("PASS\n");
/* -----\/----- EXCLUDED -----\/-----
$write("Test %0d/%0d: 128B read over DMA, abort after first read: ", $write("Test %0d/%0d: 128B read over DMA, abort after first read: ",
ntest++, tests); ntest++, tests);
...@@ -196,7 +223,7 @@ module main; ...@@ -196,7 +223,7 @@ module main;
// Check values read from memory // Check values read from memory
@(posedge i_gn4124.l2p_valid); // skip header @(posedge i_gn4124.l2p_valid); // skip header
@(posedge i_gn4124.l2p_valid); repeat(2) @(posedge i_gn4124.l2p_clk_p);
expected = 32'h8000001f; expected = 32'h8000001f;
val = i_gn4124.l2p_data; val = i_gn4124.l2p_data;
...@@ -214,12 +241,13 @@ module main; ...@@ -214,12 +241,13 @@ module main;
repeat(2) @(posedge clk_125m); repeat(2) @(posedge clk_125m);
$write("PASS\n"); $write("PASS\n");
-----/\----- EXCLUDED -----/\----- */
$write("Test %0d/%0d: 2x128B chained reads over DMA: ", $write("Test %0d/%0d: 2x128B chained reads over DMA: ",
ntest++, tests); ntest++, tests);
// Setup DMA chain info in BFM memory // Setup DMA chain info in BFM memory
i_gn4124.host_mem_write('h20000, 'h00000000); // remote address i_gn4124.host_mem_write('h20000, 'h00001000); // remote address
i_gn4124.host_mem_write('h20004, 'h20000100); // hstartL i_gn4124.host_mem_write('h20004, 'h20000100); // hstartL
i_gn4124.host_mem_write('h20008, 'h00000000); // hstartH i_gn4124.host_mem_write('h20008, 'h00000000); // hstartH
i_gn4124.host_mem_write('h2000C, 'h80); // count i_gn4124.host_mem_write('h2000C, 'h80); // count
...@@ -241,22 +269,21 @@ module main; ...@@ -241,22 +269,21 @@ module main;
@(posedge dma_irq); @(posedge dma_irq);
check_irq_status; check_irq_status;
clear_irq;
for (addr = 'h00; addr < 'h20; addr += 1) for (addr = 'h00; addr < 'h20; addr += 1)
begin begin
expected = 32'h80000000 + 'h20 - addr - 1; expected = 32'h80000000 + 'h20 - (addr % 'h20) - 1;
mem_check(4 * addr, expected); mem_check(4 * addr, expected);
mem_check('h100 + 4 * addr, expected); mem_check('h100 + 4 * addr, expected);
end end
clear_irq;
repeat(4) @(posedge clk_125m); repeat(4) @(posedge clk_125m);
$write("PASS\n"); $write("PASS\n");
// --------------------------------- // ---------------------------------
$write("Test %0d/%0d: 128 reads over DMA: ", $write("Test %0d/%0d: 256B read over DMA: ",
ntest++, tests); ntest++, tests);
// Setup DMA // Setup DMA
...@@ -270,15 +297,14 @@ module main; ...@@ -270,15 +297,14 @@ module main;
@(posedge dma_irq); @(posedge dma_irq);
check_irq_status; check_irq_status;
clear_irq;
for (addr = 'h00; addr < 'h40; addr += 1) for (addr = 'h00; addr < 'h40; addr += 1)
begin begin
expected = 32'h80000000 + 'h20 - addr - 1; expected = 32'h80000000 + 'h20 - (addr % 'h20) - 1;
mem_check(4 * addr, expected); mem_check(4 * addr, expected);
end end
clear_irq;
repeat(4) @(posedge clk_125m); repeat(4) @(posedge clk_125m);
$write("PASS\n"); $write("PASS\n");
...@@ -286,11 +312,11 @@ module main; ...@@ -286,11 +312,11 @@ module main;
// Check all four byte swap settings // Check all four byte swap settings
// --------------------------------- // ---------------------------------
for (int i = 0; i < 4; i++) begin for (int i = 0; i < 4; i++) begin
$write("Test %0d/%0d: 64KB read over DMA (byte swap = %0d): ", $write("Test %0d/%0d: 16KB read over DMA (byte swap = %0d): ",
ntest++, tests, i); ntest++, tests, i);
// Restart // Restart
acc.write('h14, 'h10000); // count acc.write('h14, 'h4000); // count
acc.write('h20, 'h00); // attrib acc.write('h20, 'h00); // attrib
acc.write('h0c, 'h20000000 + i * 'h4000); // hstartL acc.write('h0c, 'h20000000 + i * 'h4000); // hstartL
acc.write('h10, 'h00000000); // hstartH acc.write('h10, 'h00000000); // hstartH
...@@ -300,7 +326,7 @@ module main; ...@@ -300,7 +326,7 @@ module main;
check_irq_status; check_irq_status;
for (addr = 'h00; addr < 'h4000; addr += 1) for (addr = 'h00; addr < 'h1000; addr += 1)
begin begin
expected = 32'h80000000 + 'h20 - (addr % 'h20) - 1; expected = 32'h80000000 + 'h20 - (addr % 'h20) - 1;
if (i == 1) if (i == 1)
...@@ -321,26 +347,26 @@ module main; ...@@ -321,26 +347,26 @@ module main;
#1us; #1us;
end end
$write("Test %0d/%0d: 256B read over DMA with 32bit host address overflow: ", $write("Test %0d/%0d: 8KB read over DMA with 32bit host address overflow: ",
ntest++, tests); ntest++, tests);
acc.write('h14, 'h100); // count acc.write('h14, 'h2000); // count
acc.write('h20, 'h00); // attrib acc.write('h20, 'h00); // attrib
acc.write('h0c, 'hffffff80); // hstartL acc.write('h0c, 'hfffff000); // hstartL
acc.write('h10, 'h00000000); // hstartH acc.write('h10, 'h00000000); // hstartH
acc.write('h00, 'h01); // start acc.write('h00, 'h01); // start
// Transfer will be split internally by L2P DMA master in two requests, the first // Transfer will be split internally by L2P DMA master in two requests, the first
// one with a 32-bit adress starting at ffff_ff80 and the next one with a 64-bit // one with a 32-bit adress starting at ffff_f000 and the next one with a 64-bit
// address starting at 1_0000_0000 // address starting at 1_0000_0000
@(posedge DUT.cmp_wrapped_gn4124.ldm_arb_dframe); @(posedge DUT.cmp_wrapped_gn4124.ldm_arb_dframe);
@(posedge DUT.cmp_wrapped_gn4124.sys_clk); @(posedge DUT.cmp_wrapped_gn4124.sys_clk);
val_check("Host address overflow header", 1, DUT.cmp_wrapped_gn4124.ldm_arb_data, 'h02ff0020); val_check("Host address overflow header", 1, DUT.cmp_wrapped_gn4124.ldm_arb_data, 'h02ff0000);
@(posedge DUT.cmp_wrapped_gn4124.sys_clk); @(posedge DUT.cmp_wrapped_gn4124.sys_clk);
val_check("Host address overflow address", 1, DUT.cmp_wrapped_gn4124.ldm_arb_data, 'hffffff80); val_check("Host address overflow address", 1, DUT.cmp_wrapped_gn4124.ldm_arb_data, 'hfffff000);
@(posedge DUT.cmp_wrapped_gn4124.ldm_arb_dframe); @(posedge DUT.cmp_wrapped_gn4124.ldm_arb_dframe);
@(posedge DUT.cmp_wrapped_gn4124.sys_clk); @(posedge DUT.cmp_wrapped_gn4124.sys_clk);
val_check("Host address overflow header", 2, DUT.cmp_wrapped_gn4124.ldm_arb_data, 'h03ff0020); val_check("Host address overflow header", 2, DUT.cmp_wrapped_gn4124.ldm_arb_data, 'h03ff0000);
@(posedge DUT.cmp_wrapped_gn4124.sys_clk); @(posedge DUT.cmp_wrapped_gn4124.sys_clk);
val_check("Host address overflow address high", 2, DUT.cmp_wrapped_gn4124.ldm_arb_data, 1); val_check("Host address overflow address high", 2, DUT.cmp_wrapped_gn4124.ldm_arb_data, 1);
@(posedge DUT.cmp_wrapped_gn4124.sys_clk); @(posedge DUT.cmp_wrapped_gn4124.sys_clk);
......
hdl/sim/example_tb/wave.do 0 → 100644
View file @ d0c2399b
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/wb_dma_clk_i
add wave -noupdate /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/wb_dma_current_state
add wave -noupdate /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/wb_dma_cnt_stb
add wave -noupdate -expand /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/wb_dma_o
add wave -noupdate /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/wb_dma_cnt_ack
add wave -noupdate -expand /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/wb_dma_i
add wave -noupdate /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/data_fifo_wr
add wave -noupdate /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/data_fifo_full
add wave -noupdate /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/data_fifo_din
add wave -noupdate -color Gold /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/clk_i
add wave -noupdate -color Gold /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/l2p_dma_current_state
add wave -noupdate -color Gold /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/ldm_arb_valid_o
add wave -noupdate -color Gold /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/ldm_arb_dframe_o
add wave -noupdate -color Gold /main/DUT/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/ldm_arb_data_o
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {537831000 ps} 0}
quietly wave cursor active 1
configure wave -namecolwidth 199
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ps
update
WaveRestoreZoom {0 ps} {737045400 ps}
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