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Gennum GN4124 core
Commit bebc523b authored by Tristan Gingold's avatar Tristan Gingold
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dma_controller.vhd: remove one state, clarify the code

parent 300080f9
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Showing with 15 additions and 20 deletions
hdl/rtl/dma_controller.vhd
View file @ bebc523b
......@@ -129,8 +129,7 @@ architecture arch of dma_controller is
signal dma_ctrl_byte_swap_reg : std_logic_vector(1 downto 0);
-- DMA controller FSM
type dma_ctrl_state_type is (DMA_IDLE, DMA_START_TRANSFER, DMA_TRANSFER,
DMA_START_CHAIN, DMA_CHAIN);
type dma_ctrl_state_type is (DMA_IDLE, DMA_START_TRANSFER, DMA_TRANSFER, DMA_CHAIN);
signal dma_ctrl_current_state : dma_ctrl_state_type;
-- status signals
......@@ -272,14 +271,14 @@ begin
dma_attrib_chain_reg <= '0';
dma_attrib_dir_reg <= '0';
else
-- Clear interrupt when idle status is read.
if dma_stat_irq_wr = '1' and dma_stat_wr = '1' then
dma_irq_reg <= '0';
end if;
case dma_ctrl_current_state is
when DMA_IDLE =>
-- Clear interrupt when idle status is read.
if dma_stat_irq_wr = '1' and dma_stat_wr = '1' then
dma_irq_reg <= '0';
end if;
if (dma_ctrl_wr and dma_ctrl_start) = '1' then
-- Capture parameters
-- All these inputs registers are synchronized on the start pulse.
......@@ -315,8 +314,8 @@ begin
dma_ctrl_start_p2l_o <= '1';
dma_ctrl_direction_o <= '1';
end if;
dma_ctrl_current_state <= DMA_TRANSFER;
dma_stat_reg <= c_DMA_STAT_BUSY;
dma_ctrl_current_state <= DMA_TRANSFER;
end if;
when DMA_TRANSFER =>
......@@ -326,8 +325,8 @@ begin
if (dma_ctrl_abort and dma_ctrl_wr) = '1' then
-- Transfer aborted
dma_stat_reg <= c_DMA_STAT_ABORT;
dma_ctrl_abort_o <= '1';
dma_stat_reg <= c_DMA_STAT_ABORT;
dma_ctrl_current_state <= DMA_IDLE;
elsif dma_ctrl_error_i = '1' then
-- An error occured
......@@ -338,31 +337,27 @@ begin
-- End of DMA transfer
if dma_attrib_chain_reg = '1' then
-- More transfers in chained DMA
dma_ctrl_current_state <= DMA_START_CHAIN;
dma_hstarth_reg <= dma_nexth_reg;
dma_hstartl_reg <= dma_nextl_reg;
dma_len_reg <= X"0000001C";
dma_ctrl_start_next_o <= '1';
dma_ctrl_current_state <= DMA_CHAIN;
else
-- Was the last transfer
dma_stat_reg <= c_DMA_STAT_IDLE;
dma_irq_reg <= '1';
dma_stat_reg <= c_DMA_STAT_IDLE;
dma_ctrl_current_state <= DMA_IDLE;
end if;
end if;
when DMA_START_CHAIN =>
-- Catch the next item in host memory
dma_ctrl_current_state <= DMA_CHAIN;
dma_hstarth_reg <= dma_nexth_reg;
dma_hstartl_reg <= dma_nextl_reg;
dma_len_reg <= X"0000001C";
dma_ctrl_start_next_o <= '1';
when DMA_CHAIN =>
-- Clear start next signal, to make it 1 tick pulse
dma_ctrl_start_next_o <= '0';
if (dma_ctrl_abort and dma_ctrl_wr) = '1' then
-- Transfer aborted
dma_stat_reg <= c_DMA_STAT_ABORT;
dma_ctrl_abort_o <= '1';
dma_stat_reg <= c_DMA_STAT_ABORT;
dma_ctrl_current_state <= DMA_IDLE;
elsif dma_ctrl_error_i = '1' then
-- An error occured
......
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