core: Add an ACK timeout on the csr wb bus.

Note: To avoid host hang in case of access to un-mapped address and user logic not asserting ERR signal.

core: Add an ACK timeout on the csr wb bus.
Note: To avoid host hang in case of access to un-mapped address and user logic not asserting ERR signal.
94d7d0b7 · Matthieu Cattin · 2d9730ce · 94d7d0b7 · 94d7d0b7 · 94d7d0b7
Commit 94d7d0b7 authored Jan 31, 2014 by Matthieu Cattin
Showing with 52 additions and 2 deletions

gn4124_core.vhd hdl/gn4124core/rtl/spartan6/gn4124_core.vhd +6 -0

gn4124_core_pkg.vhd hdl/gn4124core/rtl/spartan6/gn4124_core_pkg.vhd +6 -0

wbmaster32.vhd hdl/gn4124core/rtl/wbmaster32.vhd +40 -2

No files found.
--- a/hdl/gn4124core/rtl/spartan6/gn4124_core.vhd
+++ b/hdl/gn4124core/rtl/spartan6/gn4124_core.vhd
@@ -51,6 +51,9 @@ use UNISIM.vcomponents.all;
 -- Entity declaration for GN4124 core (gn4124_core)
 --==============================================================================
 entity gn4124_core is
+  generic (
+    g_ACK_TIMEOUT : positive := 100                    -- Wishbone ACK timeout (in wishbone clock cycles)
+    );
  port
    (
      ---------------------------------------------------------
@@ -491,6 +494,9 @@ begin
  -- Wishbone master
  -----------------------------------------------------------------------------
  cmp_wbmaster32 : wbmaster32
+    generic map(
+      g_ACK_TIMEOUT => g_ACK_TIMEOUT
+      )
    port map
    (
      ---------------------------------------------------------

--- a/hdl/gn4124core/rtl/spartan6/gn4124_core_pkg.vhd
+++ b/hdl/gn4124core/rtl/spartan6/gn4124_core_pkg.vhd
@@ -68,6 +68,9 @@ package gn4124_core_pkg is

 -----------------------------------------------------------------------------
  component gn4124_core
+    generic (
+      g_ACK_TIMEOUT : positive := 100                    -- Wishbone ACK timeout (in wishbone clock cycles)
+      );
    port
      (
        ---------------------------------------------------------
@@ -257,6 +260,9 @@ package gn4124_core_pkg is

 -----------------------------------------------------------------------------
  component wbmaster32
+    generic (
+      g_ACK_TIMEOUT : positive := 100    -- Wishbone ACK timeout (in wb_clk cycles)
+      );
    port
      (
        ---------------------------------------------------------

--- a/hdl/gn4124core/rtl/wbmaster32.vhd
+++ b/hdl/gn4124core/rtl/wbmaster32.vhd
@@ -48,6 +48,9 @@ use work.genram_pkg.all;


 entity wbmaster32 is
+  generic (
+    g_ACK_TIMEOUT : positive := 100     -- Wishbone ACK timeout (in wb_clk cycles)
+    );
  port
    (
      ---------------------------------------------------------
@@ -157,6 +160,9 @@ architecture behaviour of wbmaster32 is
  signal wb_sel_t   : std_logic_vector(3 downto 0);
  signal wb_stall_t : std_logic;

+  signal wb_ack_timeout_cnt : unsigned(log2_ceil(g_ACK_TIMEOUT)-1 downto 0);
+  signal wb_ack_timeout     : std_logic;
+
  -- L2P packet generator
  type   l2p_read_cpl_state_type is (L2P_IDLE, L2P_HEADER, L2P_DATA);
  signal l2p_read_cpl_current_state : l2p_read_cpl_state_type;
@@ -447,8 +453,11 @@ begin
            -- end of the bus cycle
            wb_cyc_t               <= '0';
            wishbone_current_state <= WB_IDLE;
-          elsif (wb_err_t = '1') then
-            -- e.g. when trying to access unmapped wishbone addresses, ERR is set
+          elsif (wb_err_t = '1') or (wb_ack_timeout = '1') then
+            -- e.g. When trying to access unmapped wishbone addresses,
+            -- the wb crossbar asserts ERR. If ERR is not asserted when
+            -- accessing un-mapped addresses, a timeout makes sure the
+            -- transaction terminates.
            if (wb_we_t = '0') then
              from_wb_fifo_din <= (others => '1');  -- dummy data as the transaction failed
              from_wb_fifo_wr  <= '1';
@@ -486,5 +495,34 @@ begin
  wb_stall_t <= wb_stall_i;
  wb_err_t   <= wb_err_i;

+  -- ACK timeout
+  p_wb_ack_timeout_cnt : process (wb_clk_i, rst_n_i)
+  begin
+    if rst_n_i = c_RST_ACTIVE then
+      wb_ack_timeout_cnt <= (others => '1');
+    elsif rising_edge(wb_clk_i) then
+      if wishbone_current_state = WB_WAIT_ACK then
+        if wb_ack_timeout_cnt /= 0 then
+          wb_ack_timeout_cnt <= wb_ack_timeout_cnt - 1;
+        end if;
+      else
+        wb_ack_timeout_cnt <= (others => '1');
+      end if;
+    end if;
+  end process p_wb_ack_timeout_cnt;
+
+  p_ack_timeout : process (wb_clk_i, rst_n_i)
+  begin
+    if rst_n_i = c_RST_ACTIVE then
+      wb_ack_timeout <= '0';
+    elsif rising_edge(wb_clk_i) then
+      if wb_ack_timeout_cnt = 0 then
+        wb_ack_timeout <= '1';
+      else
+        wb_ack_timeout <= '0';
+      end if;
+    end if;
+  end process p_ack_timeout;
+
 end behaviour;