Synchronise dma irq pulses to csr_wb clock.

6b29b77e · Matthieu Cattin · e2212978 · 6b29b77e
Commit 6b29b77e authored Nov 22, 2011 by Matthieu Cattin
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Manifest.py hdl/gn4124core/rtl/spartan6/Manifest.py +2 -1

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--- a/hdl/gn4124core/rtl/spartan6/Manifest.py
+++ b/hdl/gn4124core/rtl/spartan6/Manifest.py
@@ -5,4 +5,5 @@ files = ["gn4124_core.vhd",
         "serdes_1_to_n_clk_pll_s2_diff.vhd",
         "serdes_1_to_n_data_s2_se.vhd",
         "serdes_n_to_1_s2_diff.vhd",
-         "serdes_n_to_1_s2_se.vhd"]
+         "serdes_n_to_1_s2_se.vhd",
+         "pulse_sync_rtl.vhd"]