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Gennum GN4124 core
Commits
5d816c79
Commit
5d816c79
authored
Jan 29, 2019
by
Dimitris Lampridis
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sim: extend example testbench to also perform DMA reads from a pre-initialised memory
parent
edde8a7d
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4 changed files
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20 deletions
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-20
README.md
hdl/gn4124core/sim/example_tb/README.md
+7
-3
main.sv
hdl/gn4124core/sim/example_tb/main.sv
+65
-16
mem_init.bram
hdl/gn4124core/sim/example_tb/mem_init.bram
+32
-0
general-cores
hdl/ip_cores/general-cores
+1
-1
No files found.
hdl/gn4124core/sim/example_tb/README.md
View file @
5d816c79
Introduction
Introduction
============
============
This is a simple example testbench, to demonstrate how to use the SystemVerilog BFM of the GN4124 to perform simple accesses over wishbone.
This is a simple example testbench, to demonstrate how to use the SystemVerilog BFM of the GN4124 to
perform simple accesses over wishbone.
The testbench simply connects the wishbone master of the GN4124 to its own DMA configuration wishbone slave.
The testbench simply connects the wishbone master of the GN4124 to its own DMA configuration
wishbone slave and attaches a pre-initialised dummy RAM with a wishbone interface to the pipelined
DMA interface in order to perform a DMA read.
Dependencies
Dependencies
============
============
...
@@ -17,7 +20,8 @@ To run it, you will need Modelsim/Questa. It has been tested with Questa 10.5c o
...
@@ -17,7 +20,8 @@ To run it, you will need Modelsim/Questa. It has been tested with Questa 10.5c o
Build/Run Instrunctions
Build/Run Instrunctions
=======================
=======================
1.
If not already done, pull all dependencies using
`git submodule update --init`
from within the gn4124 repository.
1.
If not already done, pull all dependencies using
`git submodule update --init`
from within the
gn4124 repository.
2.
Run
`hdlmake`
from the example_tb directory.
2.
Run
`hdlmake`
from the example_tb directory.
3.
Run
`make`
on the hdlmake-generated Makefile.
3.
Run
`make`
on the hdlmake-generated Makefile.
4.
Run
`vsim -c -do run.do`
.
4.
Run
`vsim -c -do run.do`
.
...
...
hdl/gn4124core/sim/example_tb/main.sv
View file @
5d816c79
...
@@ -6,11 +6,13 @@
...
@@ -6,11 +6,13 @@
//
//
// unit name: main
// unit name: main
//
//
// description: This is a simple example testbench, to demonstrate how to use
// description: This is a simple example testbench, to demonstrate how to use
// the SystemVerilog BFM of the GN4124 to perform simple accesses over wishbone.
// the SystemVerilog BFM of the GN4124 to perform simple accesses over wishbone.
//
//
// The testbench simply connects the wishbone master of the GN4124 to its own
// The testbench simply connects the wishbone master of the GN4124 to its own
// DMA configuration wishbone slave.
// DMA configuration wishbone slave and attaches a pre-initialised dummy RAM
// with a wishbone interface to the pipelined DMA interface in order to perform
// a DMA read.
//
//
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Copyright CERN 2019
// Copyright CERN 2019
...
@@ -35,8 +37,10 @@ import wishbone_pkg::*;
...
@@ -35,8 +37,10 @@ import wishbone_pkg::*;
module
main
;
module
main
;
reg
clk_125m
=
0
;
reg
clk_125m
=
0
;
t_wishbone_master_in
wb_in
;
logic
gn4124_irq
;
t_wishbone_master_out
wb_out
;
t_wishbone_master_in
wb_in
,
wb_dma_in
,
wb_mem_in
;
t_wishbone_master_out
wb_out
,
wb_dma_out
,
wb_mem_out
;
always
#
4
ns
clk_125m
<=
~
clk_125m
;
always
#
4
ns
clk_125m
<=
~
clk_125m
;
...
@@ -67,7 +71,7 @@ module main;
...
@@ -67,7 +71,7 @@ module main;
.
tx_error_i
(
i_gn4124
.
tx_error
)
,
.
tx_error_i
(
i_gn4124
.
tx_error
)
,
.
dma_irq_o
()
,
.
dma_irq_o
()
,
.
irq_p_i
(
1'b0
)
,
.
irq_p_i
(
1'b0
)
,
.
irq_p_o
()
,
.
irq_p_o
(
gn4124_irq
)
,
.
status_o
()
,
.
status_o
()
,
.
wb_master_clk_i
(
clk_125m
)
,
.
wb_master_clk_i
(
clk_125m
)
,
.
wb_master_rst_n_i
(
1'b1
)
,
.
wb_master_rst_n_i
(
1'b1
)
,
...
@@ -77,29 +81,53 @@ module main;
...
@@ -77,29 +81,53 @@ module main;
.
wb_dma_cfg_rst_n_i
(
1'b1
)
,
.
wb_dma_cfg_rst_n_i
(
1'b1
)
,
.
wb_dma_cfg_i
(
wb_out
)
,
.
wb_dma_cfg_i
(
wb_out
)
,
.
wb_dma_cfg_o
(
wb_in
)
,
.
wb_dma_cfg_o
(
wb_in
)
,
.
wb_dma_dat_clk_i
(
1'b0
)
,
.
wb_dma_dat_clk_i
(
clk_125m
)
,
.
wb_dma_dat_rst_n_i
(
1'b1
)
,
.
wb_dma_dat_rst_n_i
(
1'b1
)
,
.
wb_dma_dat_i
()
,
.
wb_dma_dat_i
(
wb_dma_in
)
,
.
wb_dma_dat_o
()
.
wb_dma_dat_o
(
wb_dma_out
)
)
;
)
;
xwb_dpram
#
(
.
g_size
(
32
)
,
.
g_init_file
(
"mem_init.bram"
)
,
.
g_slave1_interface_mode
(
1
)
,
// 1 = PIPELINED
.
g_slave2_interface_mode
(
1
)
,
.
g_slave1_granularity
(
1
)
,
// 1 = WORD
.
g_slave2_granularity
(
1
)
)
MEM
(
.
rst_n_i
(
1'b1
)
,
.
clk_sys_i
(
clk_125m
)
,
.
slave1_i
(
wb_dma_out
)
,
.
slave1_o
(
wb_dma_in
)
,
.
slave2_i
(
wb_mem_out
)
,
.
slave2_o
(
wb_mem_in
)
)
;
CBusAccessor
acc
;
CBusAccessor
acc
;
task
reg_check
(
uint64_t
addr
,
expected
)
;
task
val_check
(
string
name
,
uint64_t
addr
,
val
,
expected
)
;
uint64_t
val
;
acc
.
read
(
addr
,
val
)
;
if
(
val
!=
expected
)
if
(
val
!=
expected
)
begin
begin
$
display
()
;
$
display
()
;
$
display
(
"Simulation FAILED"
)
;
$
display
(
"Simulation FAILED"
)
;
$
fatal
(
1
,
"
Read-back
error at address 0x%.2x. Expected 0x%.8x, got 0x%.8x"
,
$
fatal
(
1
,
"
%s
error at address 0x%.2x. Expected 0x%.8x, got 0x%.8x"
,
addr
,
expected
,
val
)
;
name
,
addr
,
expected
,
val
)
;
end
end
$
display
(
"%s at address 0x%.2x: 0x%.8x [OK]"
,
name
,
addr
,
val
)
;
endtask
// val_check
task
reg_check
(
uint64_t
addr
,
expected
)
;
uint64_t
val
;
acc
.
read
(
addr
,
val
)
;
val_check
(
"Register read-back"
,
addr
,
val
,
expected
)
;
endtask
// reg_check
endtask
// reg_check
initial
begin
initial
begin
uint64_t
addr
,
val
;
uint64_t
addr
,
val
,
expected
;
@
(
posedge
i_gn4124
.
ready
)
;
@
(
posedge
i_gn4124
.
ready
)
;
...
@@ -109,6 +137,7 @@ module main;
...
@@ -109,6 +137,7 @@ module main;
@
(
posedge
clk_125m
)
;
@
(
posedge
clk_125m
)
;
// Verify simple read/writes over wishbone
reg_check
(
'h0
,
'h0
)
;
reg_check
(
'h0
,
'h0
)
;
acc
.
write
(
'h10
,
'hffacce55
)
;
acc
.
write
(
'h10
,
'hffacce55
)
;
...
@@ -117,12 +146,32 @@ module main;
...
@@ -117,12 +146,32 @@ module main;
reg_check
(
'h10
,
'hffacce55
)
;
reg_check
(
'h10
,
'hffacce55
)
;
reg_check
(
'h20
,
'h1badcafe
)
;
reg_check
(
'h20
,
'h1badcafe
)
;
// Reset all DMA config registers
for
(
addr
=
'h00
;
addr
<=
'h20
;
addr
+=
4
)
for
(
addr
=
'h00
;
addr
<=
'h20
;
addr
+=
4
)
begin
begin
acc
.
read
(
addr
,
val
)
;
acc
.
write
(
addr
,
'h0
)
;
$
display
(
"0x%.2x: 0x%.8x"
,
addr
,
val
)
;
end
end
// Perform 32 reads over DMA
acc
.
write
(
'h14
,
'h80
)
;
acc
.
write
(
'h00
,
'h01
)
;
// Check values read from memory
@
(
posedge
i_gn4124
.
l2p_valid
)
;
// skip header
@
(
posedge
i_gn4124
.
l2p_valid
)
;
for
(
addr
=
'h20
;
addr
>
'h00
;
addr
-=
1
)
begin
expected
=
64'h80000000
+
addr
-
1
;
val
=
i_gn4124
.
l2p_data
;
@
(
posedge
i_gn4124
.
l2p_clk_n
)
;
val
|=
i_gn4124
.
l2p_data
<<
16
;
val_check
(
"DMA read-back"
,
'h20
-
addr
,
val
,
expected
)
;
@
(
posedge
i_gn4124
.
l2p_clk_p
)
;
end
#
1u
s
;
$
display
()
;
$
display
()
;
$
display
(
"Simulation PASSED"
)
;
$
display
(
"Simulation PASSED"
)
;
...
...
hdl/gn4124core/sim/example_tb/mem_init.bram
0 → 100644
View file @
5d816c79
10000000000000000000000000011111
10000000000000000000000000011110
10000000000000000000000000011101
10000000000000000000000000011100
10000000000000000000000000011011
10000000000000000000000000011010
10000000000000000000000000011001
10000000000000000000000000011000
10000000000000000000000000010111
10000000000000000000000000010110
10000000000000000000000000010101
10000000000000000000000000010100
10000000000000000000000000010011
10000000000000000000000000010010
10000000000000000000000000010001
10000000000000000000000000010000
10000000000000000000000000001111
10000000000000000000000000001110
10000000000000000000000000001101
10000000000000000000000000001100
10000000000000000000000000001011
10000000000000000000000000001010
10000000000000000000000000001001
10000000000000000000000000001000
10000000000000000000000000000111
10000000000000000000000000000110
10000000000000000000000000000101
10000000000000000000000000000100
10000000000000000000000000000011
10000000000000000000000000000010
10000000000000000000000000000001
10000000000000000000000000000000
general-cores
@
e4f3f8c8
Subproject commit
50acfac70eabd8a8dc67be1e6484d66a0dd760f3
Subproject commit
e4f3f8c874cfec8f162bfc0da9794e66e39b911b
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