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Gennum GN4124 core
Commit 11fc3280 authored by Matthieu Cattin's avatar Matthieu Cattin
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Add simulation folder to repo.

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hdl/spec/sim/Makefile 0 → 100644
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hdl/spec/sim/Manifest.py 0 → 100644
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action = "simulation"
target = "xilinx"
files = ["testbench/gn412x_bfm.vhd",
"testbench/cmd_router.vhd",
"testbench/textutil.vhd",
"testbench/util.vhd",
"testbench/tb_spec.vhd",
"testbench/cmd_router1.vhd"]
modules = { "local" : ["../rtl",
"testbench"]}
hdl/spec/sim/Test_Builder/cont_block_dma.c 0 → 100644
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//***********************************************************************************************
//***********************************************************************************************
//**
//** Name: cont_block_dma.c
//**
//** Description: DMA scenario for a 2MB contiguous block of memory.
//**
//**
//***********************************************************************************************
//***********************************************************************************************
//===============================================================================================
// This provides the framework for creating tests for the testbench as described in
// GN412x Simulation Test Bench User Guide
//===============================================================================================
#include "lib/maketest.c"
//===============================================================================================
// This provides the framework for creating microcode for the 3 or 4DW list type described in
// the application note: "Implementing Multi-channel DMA with the GN412x IP"
//===============================================================================================
#include "lib/vdma_service.c"
//===============================================================================================
// lambo.h contains the address map for the Lambo project
//===============================================================================================
#include "lambo.h"
//===============================================================================================
// Define the Memory Map
//===============================================================================================
#define BAR0_BASE 0xFF00000010000000ll
#define BAR1_BASE 0xFF000000A0000000ll
#define BFM_BAR0_BASE 0x87654321F0000000ll
#define BFM_BAR1_BASE 0xBB00000040000000ll
#define CHAN0_DESC_LIST_SIZE 3
#define L2P_CHAN0_SUB_DMA_LENGTH 0x1000
#define L2P_CHAN0_XFER_CTL 0x00010000
//===============================================================================================
// Define the SG List
//===============================================================================================
struct sg_entry_struct sg_list_chan0[] =
{
{ BFM_BAR0_BASE|0xFF1000C8, L2P_CHAN0_XFER_CTL | 0xF38, 1 },
{ BFM_BAR0_BASE|0xFF101000, L2P_CHAN0_XFER_CTL | (L2P_CHAN0_SUB_DMA_LENGTH & 0xFFF), 511 },
{ BFM_BAR0_BASE|0xFF300000, L2P_CHAN0_XFER_CTL | 0x0C8 | 0x80000000, 1 }, //Assert an interrupt
{ 0x0ll, 0, 0 }
};
//***********************************************************************************************
//**
//** vdma_main: This will insert the DMA microcode and data into the test script
//**
//** The last function call, vdma_process(), will cross reference all of the labels in the
//** source code so that you end up with the proper hexadecimal values that need to be written
//** to descriptor RAM.
//**
//***********************************************************************************************
void vdma_main()
{
vdma_org(0x0000); //This initializes the program address counter
data_address = 0x200; //This initializes the data space address counter
vdma_label("START");
vdma_nop(); //do nothing
//===============================================================================================
// START of the main program loop
//===============================================================================================
vdma_label("MAIN");
vdma_channel_service_4
(
"L2P_CHAN0", //label to be used for this specific channel
'l', //direction='l' for l2p or 'p' for p2l
0, //The event register bit to be used for interrupt generation
_EXT_COND_0, //External condition used for this channel
_EXT_COND_LO, //Set to either _EXT_COND_LO or _EXT_COND_HI
0, //set to non zero when the list will be updated dynamicaly
CHAN0_DESC_LIST_SIZE, //SYS_ADDR step size of list entries that have a repeat count
L2P_CHAN0_SUB_DMA_LENGTH, //Step size of list entries that have a repeat count
sg_list_chan0 //SG List itself
);
vdma_nop(); // This is not required (can be replaced with more channel servicing)
vdma_jmp(_ALWAYS, 0,"MAIN"); //loop forever
//===============================================================================================
// END of the main program loop
//===============================================================================================
//-----------------------------------------------------------------------------------------------
// Global Constants
//-----------------------------------------------------------------------------------------------
vdma_org(0x0100);
vdma_label("ZERO");
vdma_constant_n64(0); //The constant 0
vdma_label("MINUS1");
vdma_constant_n(0xFFFFFFFF); //The constant -1
vdma_label("THREE");
vdma_constant_n(3); //The constant 3
vdma_label("FOUR");
vdma_constant_n(4); //The constant 4
//===============================================================================================
// Must run vdma_process to resolve the cross-references and generate the microcode
//===============================================================================================
vdma_process(BAR0_BASE + 0x4000);
}
//***********************************************************************************************
//**
//** Main:
//**
//** Edit the program below to create your own test script.
//**
//***********************************************************************************************
main(argc,argv)
int argc;
char *argv[];
{
int offset=0, i;
//-----------------------------------------------------------------------------------------------
// Always call maketest_init at the beginning of a test program
//-----------------------------------------------------------------------------------------------
maketest_init(argc,argv);
//================================================================================================
//== START of user script
//================================================================================================
comment("-----------------------------------------------------------------------------");
comment("Generated from: simple.c - do not edit the vec file directly as it is not the source!");
comment("Short example of using the lambo TestBench");
comment("-----------------------------------------------------------------------------");
comment("Select the GN4124 Primary BFM");
model(0);
comment("Initialize the BFM to its default state");
init();
comment("\nDrive reset to the FPGA");
reset(16);
comment("\n");
comment("-----------------------------------------------------------------------------");
comment("Initialize the Primary GN412x BFM model");
comment("-----------------------------------------------------------------------------");
comment("These address ranges will generate traffic from the BFM to the FPGA");
comment("bar BAR ADDR SIZE VC TC S");
bar(0, BAR0_BASE, 0x20000000, 0, 7, 0);
bar(1, BAR1_BASE, 0x10000000, 1, 5, 0);
comment("\nThis allocates a RAM block inside the BFM for the FPGA to access");
comment("bfm_bar BAR ADDR SIZE");
bfm_bar(0, BFM_BAR0_BASE, 0x10000000);
bfm_bar(1, BFM_BAR1_BASE, 0x20000000);
comment("\nWait until the FPGA is un-reset and ready for traffic on the local bus");
wait(64);
comment("\n-------------------------------------------------------------------------------");
comment("DO some setup");
comment("-------------------------------------------------------------------------------");
comment("Lambo setup...");
rd(BAR0_BASE + DMA_SEQ_CSR_REG, 0xF, 0x00000000, 0xFFFFFFFF);
flush(0x100);
wr(BAR0_BASE + DMA_SEQ_DPTR_REG, 0xF, 0x0);
wr(BAR0_BASE + DMA_SEQ_EVENT_EN_REG, 0xF, 0x3);
wr(BAR0_BASE + DMA_SEQ_EVENT_CLR_REG, 0xF, 0xFFFFFFFF);
wr(BAR0_BASE + APP_CFG, 0xF, 0x6);
wr(BAR0_BASE + APP_CFG, 0xF, 0x0);
wr(BAR0_BASE + DMA_CFG, 0xF, 0x1F);
wr(BAR0_BASE + DMA_CFG, 0xF, 0x7);
wr(BAR0_BASE + APP_GEN_COUNT, 0xF, 0x0);
wr(BAR0_BASE + APP_RCV_COUNT, 0xF, 0x0);
wr(BAR0_BASE + APP_RCV_ERR_COUNT, 0xF, 0x0);
wr(BAR0_BASE + DMA_PAYLOAD_SIZE, 0xF, 0x8020);
comment("\n-------------------------------------------------------------------------------");
comment("Setup the DMA microcode");
comment("-------------------------------------------------------------------------------");
vdma_main();
comment("\nStart VDMA");
wr(BAR0_BASE + DMA_SEQ_CSR_REG, 0xF, 0x1);
comment("\n-------------------------------------------------------------------------------");
comment("Wait for an Interrupt for Channel 0");
comment("-------------------------------------------------------------------------------");
gpio_wait(8000, 0x0001, 0x0001);
comment("Clear the interrupt");
wr(BAR0_BASE + DMA_SEQ_EVENT_CLR_REG, 0xF, 0x00000001);
comment("\nRead VDMA idle status");
rd(BAR0_BASE + DMA_SEQ_CSR_REG, 0xF, 0x00000000, 0xFFFFFFFF);
flush(5000);
wait(16);
//================================================================================================
//== END of user script
//================================================================================================
fclose(outfp);
exit(0);
}
hdl/spec/sim/Test_Builder/lambo.h 0 → 100644
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#define DMA_STATUS_MASK 0x0000
#define DMA_CFG 0x0004
#define DMA_SEQ_EVENT_SET_REG 0x0008
#define DMA_SEQ_EVENT_CLR_REG 0x000C
#define DMA_SEQ_EVENT_REG 0x0010
#define DMA_SEQ_EVENT_EN_REG 0x0014
#define DMA_SEQ_ADDR_LOW_REG 0x0018
#define DMA_SEQ_ADDR_HI_REG 0x001C
#define DMA_SEQ_DPTR_REG 0x0020
#define DMA_SEQ_XFER_CTRL_REG 0x0024
#define DMA_SEQ_RA_REG 0x0028
#define DMA_SEQ_RB_REG 0x002C
#define DMA_SEQ_CSR_REG 0x0030
#define DMA_PAYLOAD_SIZE 0x0034
#define DMA_STATUS 0x0038
#define DMA_STATUS_RAW 0x003C
#define APP_STATUS_MASK 0x0050
#define APP_CFG 0x0054
#define APP_GEN_COUNT 0x0058
#define APP_RCV_COUNT 0x005C
#define APP_RCV_ERR_COUNT 0x0060
#define APP_STATUS 0x0064
#define APP_STATUS_RAW 0x0068
#define DMA_SEQ_DESC_RAM 0x4000
hdl/spec/sim/Test_Builder/lib/maketest.c 0 → 100644
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//---------------------------------------------------------------------------
/*
* Name: vdma_gen.c
*
* Description: Main Program for Generating VDMA Sequencer Code.
*
*/
#include "stdio.h"
#include "ctype.h"
#include "string.h"
#include "stdlib.h"
//#include "malloc.h"
#include "vdma_seqcode.h"
//#include "vdma_gen_struct.h"
#define VDMA_DRAM_SIZE 2048 // Size in DW of the descriptor RAM
#define MAX_LABELS 2048 // Maximum number of labels
#define MAX_COMMENT 200
#define MAX_LABEL_SIZE 32
struct
{
DWORD data;
char *label;
char comment[MAX_COMMENT+1];
} dram[VDMA_DRAM_SIZE+1];
struct
{
char *label; // label string
int address; // Address of the label
} vdma_labels[MAX_LABELS];
int label_compare(char *string1, char *string2)
{
if((string1 == NULL) || (string2 == NULL) || (*string1 == '\0') || (*string2 == '\0'))
return(0); /* no match */
else if(strlen(string1) != strlen(string2))
return(0); /* no match */
else
return(strcmp(string1, string2) == 0);
}
int program_address = 0;
int label_pointer = 0;
char last_label[100];
char out_filename[256];
FILE *outfp;
FILE *infp;
#include "model.c"
#include "vdma_seqcode_lib.c"
#define BAR0_ADDR_H ((DWORD)0xFF000000)
#define BAR0_ADDR_L ((DWORD)0x10000000)
//================================================================================================
//
// Do Some Initialization
//
//================================================================================================
maketest_init(argc,argv)
int argc;
char *argv[];
{
int i;
char *src, *dst;
// char filename[256];
src = argv[0];
dst = out_filename;
for(i=0; i<250; i++)
{
*dst = *src;
if(*src == '\0')
{
dst[0]='.';
dst[1]='h';
dst[2]='e';
dst[3]='x';
dst[4]='\0';
break;
}
if(*src == '.')
{
dst[1]='h';
dst[2]='e';
dst[3]='x';
dst[4]='\0';
break;
}
dst++;
src++;
}
/* Open the Hex Output File */
if((outfp = fopen(out_filename,"wb")) == NULL)
{
fprintf(stderr, "Couldn't open file %s for writing\n", out_filename);
exit(-2);
}
clearerr(outfp);
fprintf(stderr, "Output file %s is open...\n", out_filename);
/* initialize the label structure */
for(i = 0; i < MAX_LABELS; i++)
{
vdma_labels[i].label = NULL;
vdma_labels[i].address = -1;
}
/* initialize the descriptor RAM structure */
for(i = 0; i < VDMA_DRAM_SIZE; i++)
{
dram[i].label = NULL;
dram[i].data = 0;
dram[i].comment[0] = '\0';
}
program_address = 0;
label_pointer = 0;
last_label[0] = '\0';
fprintf(stderr, "Initialization complete\n");
comment("***********************************************************************************");
comment("*** Warning: this file is automatically generated. ***");
comment("***********************************************************************************");
comment("*** Do not edit this file directly as it is not the source! ***");
comment("***********************************************************************************");
}
vdma_process(U64 descriptor_base)
{
int i=0;
int lines=0;
int im;
int address;
fprintf(stderr, "Pass one complete:\n");
fprintf(stderr, " Processed %d labels\n", label_pointer);
fprintf(stderr, " Ended with program address=0x%04X\n", program_address);
//---------------------------------------------------------------------------------
// 2nd Pass: Now resolve label references
//---------------------------------------------------------------------------------
for(program_address = 0; program_address < VDMA_DRAM_SIZE; program_address++)
{
if((dram[program_address].label != NULL) && (dram[program_address].label[0] != '\0')) /* resolve the label */
{
//fprintf(stderr, "Resolving label %s at address=0x%04X\n", dram[program_address].label, program_address);
if(vdma_label_lookup(dram[program_address].label, &address))
{
dram[program_address].data |= address & 0xFFFF;
}
else
{
if((dram[program_address].label[0] == '0') && (tolower(dram[program_address].label[1]) == 'x')) // case of the label being a number
{
if(sscanf(&dram[program_address].label[2], "%x", &im) == 1)
dram[program_address].data |= im & 0xFFFF;
else
fprintf(stderr, "ERROR: could not resolve label %s. Appears to be a hex value?\n", dram[program_address].label);
}
else
fprintf(stderr, "ERROR: could not resolve label %s\n", dram[program_address].label);
}
i++;
}
//fprintf(stderr, "%d\n", program_address);
if(dram[program_address].label != NULL)
{
fprintf(outfp, "0x%04X\t0x%08lX\t%s\n", program_address, dram[program_address].data, dram[program_address].comment);
fprintf(stdout, "-- 0x%04X 0x%08lX %s\n", program_address, dram[program_address].data, dram[program_address].comment);
wr(descriptor_base + (program_address*4), 0xF, dram[program_address].data);
//fprintf(stdout, "wrb %08lX%08lX F %08lX\n", 0xFF000000, program_address, dram[program_address].data);
lines++;
}
}
fprintf(outfp, "// Label Listing:\n");
// Put the label table into the output file
for(i = 0; i < label_pointer; i++)
{
fprintf(outfp, "// 0x%04X : \"%s\"\n", vdma_labels[i].address, vdma_labels[i].label);
}
// label_pointer = 0;
fprintf(stderr, "Pass two complete:\n");
fprintf(stderr, " Substituted %d references in %d words of program and data space\n", i, lines);
fprintf(stderr, " Created output file \"%s\"\n", out_filename);
}
hdl/spec/sim/Test_Builder/lib/model.c 0 → 100644
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hdl/spec/sim/Test_Builder/lib/vdma_seqcode.h 0 → 100644
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//---------------------------------------------------------------------------
/*
* Name: vdma_seqcode.h
*
* Description: FlexDMA sequencer instruction macros.
*
*/
#ifndef _VDMA_SEQCODE_H_
#define _VDMA_SEQCODE_H_
//Warning message during compilation to indicate macros are used
#pragma message("***** VDMA_CODE_GEN_MACRO is defined *****")
#ifndef DWORD
#define DWORD unsigned long
#endif
/*************************************************
VDMA sequencer code Definitions
*************************************************/
#define _IM (0)
#define _RA (2)
#define _RB (3)
//Condition code for JMP instruction
#define _RA_EQZ (0x8)
#define _RA_NEQZ (0)
#define _RB_EQZ (0x9)
#define _RB_NEQZ (1)
#define _ALWAYS (0xA)
#define _NEVER (0x2)
#define _C_HI (0xB)
#define _C_LO (0x3)
#define _PDM_CMD_QUEUE_FULL_HI (0xC)
#define _PDM_CMD_QUEUE_FULL_LO (0x4)
#define _LDM_CMD_QUEUE_FULL_HI (0xD)
#define _LDM_CMD_QUEUE_FULL_LO (0x5)
#define _EXT_COND_HI (0xF)
#define _EXT_COND_LO (0x7)
//External condition select code for JMP instruction
#define _PDM_IDLE (32)
#define _LDM_IDLE (33)
#define _EXT_COND_0 (34)
#define _EXT_COND_1 (35)
#define _EXT_COND_2 (36)
#define _EXT_COND_3 (37)
#define _EXT_COND_4 (38)
#define _EXT_COND_5 (39)
#define _EXT_COND_6 (40)
#define _EXT_COND_7 (41)
#define _EXT_COND_8 (42)
#define _EXT_COND_9 (43)
#define _EXT_COND_10 (44)
#define _EXT_COND_11 (45)
#define _EXT_COND_12 (46)
#define _EXT_COND_13 (47)
#define _EXT_COND_14 (48)
#define _EXT_COND_15 (49)
// VDMA instructions
#define VDMA_NOP() \
((DWORD)0x0)
#define VDMA_LOAD_SYS_ADDR(R, ADDR) \
((DWORD)0x40000000 | \
((DWORD)(R & 0x3) << 24) | \
((DWORD)(ADDR & 0xFFFF)) \
)
#define VDMA_STORE_SYS_ADDR(R, ADDR) \
((DWORD)0x50000000 | \
((DWORD)(R & 0x3) << 24) | \
((DWORD)(ADDR & 0xFFFF)) \
)
#define VDMA_ADD_SYS_ADDR(DATA) \
((DWORD)0x60000000 | \
((DWORD)(DATA & 0xFFFF)) \
)
#define VDMA_ADD_SYS_ADDR_I(ADDR) \
((DWORD)0xE0000000 | \
((DWORD)(ADDR & 0xFFFF)) \
)
#define VDMA_LOAD_XFER_CTL(R, ADDR) \
((DWORD)0xF0000000 | \
((DWORD)(R & 0x3) << 24) | \
((DWORD)(ADDR & 0xFFFF)) \
)
#define VDMA_LOAD_RA(ADDR) \
((DWORD)0x20000000 | \
((DWORD)(ADDR & 0xFFFF)) \
)
#define VDMA_ADD_RA(ADDR) \
((DWORD)0x21000000 | \
((DWORD)(ADDR & 0xFFFF)) \
)
#define VDMA_LOAD_RB(ADDR) \
((DWORD)0x24000000 | \
((DWORD)(ADDR & 0xFFFF)) \
)
#define VDMA_ADD_RB(ADDR) \
((DWORD)0x25000000 | \
((DWORD)(ADDR & 0xFFFF)) \
)
#define VDMA_STORE_RA(ADDR) \
((DWORD)0xA2000000 | \
((DWORD)(ADDR & 0xFFFF)) \
)
#define VDMA_STORE_RB(ADDR) \
((DWORD)0xA3000000 | \
((DWORD)(ADDR & 0xFFFF)) \
)
#define VDMA_JMP(C, EXT_COND, ADDR) \
((DWORD)0x10000000 | \
(DWORD)((C & 0xF) << 24) | \
(DWORD) ((EXT_COND & 0xFF) << 16) | \
((DWORD)(ADDR & 0xFFFF)) \
)
#define VDMA_SIG_EVENT(S, A, EVENT_EN) \
((DWORD)0x80000000 | \
((DWORD)(S & 0x1) << 27) | \
((DWORD)(A & 0x1) << 26) | \
((DWORD)(EVENT_EN & 0xFFFF)) \
)
#define VDMA_WAIT_EVENT(EVENT_EN, EVENT_STATE) \
((DWORD)0x90000000 | \
((DWORD)((EVENT_EN & 0xFFF) << 12)) | \
((DWORD)(EVENT_STATE & 0xFFF)) \
)
#endif
hdl/spec/sim/Test_Builder/lib/vdma_seqcode_lib.c 0 → 100644
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hdl/spec/sim/Test_Builder/lib/vdma_service.c 0 → 100644
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hdl/spec/sim/Test_Builder/pfc_ddr_test.c 0 → 100644
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//***********************************************************************************************
//***********************************************************************************************
//**
//** Name: simple.c
//**
//** Description: This is an example test source code used to drive the Lambo TestBench.
//**
//***********************************************************************************************
//***********************************************************************************************
#include "lib/maketest.c"
#define BAR0_BASE 0xFF00000010000000ll
#define BAR1_BASE 0xFF000000A0000000ll
#define BFM_BAR0_BASE 0x8765432120000000ll
#define BFM_BAR1_BASE 0xBB00000040000000ll
//***********************************************************************************************
//**
//** Main:
//**
//** Edit the program below to create your own test script.
//**
//***********************************************************************************************
main(argc,argv)
int argc;
char *argv[];
{
//-----------------------------------------------------------------------------------------------
// Always call maketest_init at the beginning of a test program
//-----------------------------------------------------------------------------------------------
maketest_init(argc,argv);
//================================================================================================
//== START of user script
//================================================================================================
comment("-----------------------------------------------------------------------------");
comment("Generated from: simple.c - do not edit the vec file directly as it is not the source!");
comment("Short example of using the lambo TestBench");
comment("-----------------------------------------------------------------------------");
comment("Select the GN4124 Primary BFM");
model(0);
comment("Initialize the BFM to its default state");
init();
comment("\nDrive reset to the FPGA");
reset(16);
comment("\n");
comment("-----------------------------------------------------------------------------");
comment("Initialize the Primary GN412x BFM model");
comment("-----------------------------------------------------------------------------");
comment("These address ranges will generate traffic from the BFM to the FPGA");
comment("bar BAR ADDR SIZE VC TC S");
bar(0, BAR0_BASE, 0x08000000, 0, 7, 0);
bar(1, BAR1_BASE, 0x10000000, 1, 5, 0);
comment("\nThis allocates a RAM block inside the BFM for the FPGA to access");
comment("bfm_bar BAR ADDR SIZE");
bfm_bar(0, BFM_BAR0_BASE, 0x20000000);
bfm_bar(1, BFM_BAR1_BASE, 0x20000000);
comment("\nWait until the FPGA is un-reset and ready for traffic on the local bus");
wait(64);
comment("\n-----------------------------------------------------------------------------");
comment("Access the descriptor memory in the Lambo design");
comment("-----------------------------------------------------------------------------");
comment("the following three writes will go out in a single packet");
wrb(BAR0_BASE+0x4000, 0xF, 0x87654321);
wrb(BAR0_BASE+0x4004, 0xF, 0xFEEDFACE);
wr( BAR0_BASE+0x4008, 0xF, 0xDEADBEEF);
comment("\nNow read back what was just written");
comment("the following three reads will go out as a single request");
rdb(BAR0_BASE+0x4000, 0xF, 0x87654321, 0xFFFFFFFF);
rdb(BAR0_BASE+0x4004, 0xF, 0xFEEDFACE, 0xFFFFFFFF);
rd( BAR0_BASE+0x4008, 0xF, 0xDEADBEEF, 0xFFFFFFFF);
comment("\n");
flush(256);
comment("\n");
wait(16);
comment("\n");
sync();
//================================================================================================
//== END of user script
//================================================================================================
exit(0);
}
hdl/spec/sim/Test_Builder/sg_dma.c 0 → 100644
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hdl/spec/sim/Test_Builder/simple.c 0 → 100644
View file @ 11fc3280
//***********************************************************************************************
//***********************************************************************************************
//**
//** Name: simple.c
//**
//** Description: This is an example test source code used to drive the Lambo TestBench.
//**
//***********************************************************************************************
//***********************************************************************************************
#include "lib/maketest.c"
#define BAR0_BASE 0xFF00000010000000ll
#define BAR1_BASE 0xFF000000A0000000ll
#define BFM_BAR0_BASE 0x8765432120000000ll
#define BFM_BAR1_BASE 0xBB00000040000000ll
//***********************************************************************************************
//**
//** Main:
//**
//** Edit the program below to create your own test script.
//**
//***********************************************************************************************
main(argc,argv)
int argc;
char *argv[];
{
//-----------------------------------------------------------------------------------------------
// Always call maketest_init at the beginning of a test program
//-----------------------------------------------------------------------------------------------
maketest_init(argc,argv);
//================================================================================================
//== START of user script
//================================================================================================
comment("-----------------------------------------------------------------------------");
comment("Generated from: simple.c - do not edit the vec file directly as it is not the source!");
comment("Short example of using the lambo TestBench");
comment("-----------------------------------------------------------------------------");
comment("Select the GN4124 Primary BFM");
model(0);
comment("Initialize the BFM to its default state");
init();
comment("\nDrive reset to the FPGA");
reset(16);
comment("\n");
comment("-----------------------------------------------------------------------------");
comment("Initialize the Primary GN412x BFM model");
comment("-----------------------------------------------------------------------------");
comment("These address ranges will generate traffic from the BFM to the FPGA");
comment("bar BAR ADDR SIZE VC TC S");
bar(0, BAR0_BASE, 0x08000000, 0, 7, 0);
bar(1, BAR1_BASE, 0x10000000, 1, 5, 0);
comment("\nThis allocates a RAM block inside the BFM for the FPGA to access");
comment("bfm_bar BAR ADDR SIZE");
bfm_bar(0, BFM_BAR0_BASE, 0x20000000);
bfm_bar(1, BFM_BAR1_BASE, 0x20000000);
comment("\nWait until the FPGA is un-reset and ready for traffic on the local bus");
wait(64);
comment("\n-----------------------------------------------------------------------------");
comment("Access the descriptor memory in the Lambo design");
comment("-----------------------------------------------------------------------------");
comment("the following three writes will go out in a single packet");
wrb(BAR0_BASE+0x4000, 0xF, 0x87654321);
wrb(BAR0_BASE+0x4004, 0xF, 0xFEEDFACE);
wr( BAR0_BASE+0x4008, 0xF, 0xDEADBEEF);
comment("\nNow read back what was just written");
comment("the following three reads will go out as a single request");
rdb(BAR0_BASE+0x4000, 0xF, 0x87654321, 0xFFFFFFFF);
rdb(BAR0_BASE+0x4004, 0xF, 0xFEEDFACE, 0xFFFFFFFF);
rd( BAR0_BASE+0x4008, 0xF, 0xDEADBEEF, 0xFFFFFFFF);
comment("\n");
flush(256);
comment("\n");
wait(16);
comment("\n");
sync();
//================================================================================================
//== END of user script
//================================================================================================
exit(0);
}
hdl/spec/sim/Test_Builder/simple.vec 0 → 100644
View file @ 11fc3280
-------------------------------------------------------------------------------
-- Generated from: simple.c - do not edit the vec file directly as it is not the source!
-- Short example of using the lambo TestBench
-------------------------------------------------------------------------------
-- Select the GN4124 Primary BFM
model %d0
-- Initialize the BFM to its default state
init
-- Drive reset to the FPGA
reset %d16
-------------------------------------------------------------------------------
-- Initialize the Primary GN412x BFM model
-------------------------------------------------------------------------------
-- These address ranges will generate traffic from the BFM to the FPGA
-- bar BAR ADDR SIZE VC TC S
bar 0 FF00000010000000 08000000 0 7 0
bar 1 FF000000A0000000 10000000 1 5 0
-- This allocates a RAM block inside the BFM for the FPGA to access
-- bfm_bar BAR ADDR SIZE
bfm_bar 0 8765432120000000 20000000
bfm_bar 1 BB00000040000000 20000000
-- Wait until the FPGA is un-reset and ready for traffic on the local bus
wait %d64
-------------------------------------------------------------------------------
-- Access the descriptor memory in the Lambo design
-------------------------------------------------------------------------------
-- the following three writes will go out in a single packet
wrb FF00000010004000 F 87654321
wrb FF00000010004004 F FEEDFACE
wr FF00000010004008 F DEADBEEF
-- Now read back what was just written
-- the following three reads will go out as a single request
rdb FF00000010004000 F 87654321 FFFFFFFF
rdb FF00000010004004 F FEEDFACE FFFFFFFF
rd FF00000010004008 F DEADBEEF FFFFFFFF
flush %d256
wait %d16
sync
hdl/spec/sim/Test_Builder/simple_dma.c 0 → 100644
View file @ 11fc3280
//***********************************************************************************************
//***********************************************************************************************
//**
//** Name: simple_dma.c
//**
//** Description: This is an example test source code used to drive the Lambo TestBench.
//**
//**
//***********************************************************************************************
//***********************************************************************************************
#include "lib/maketest.c" //This inserts the Test_Builder C framework
#include "lambo.h" //This is for the project specific registers
//===============================================================================================
// Define the Memory Map for the Simulation
//===============================================================================================
#define BAR0_BASE 0xFF00000010000000ll //rd/wr here generate LB cycles
#define BAR1_BASE 0xFF000000A0000000ll
#define BFM_BAR0_BASE 0x8765432120000000ll //rd/wr here accesses internal BFM memory
#define BFM_BAR1_BASE 0xBB00000040000000ll
#define VDMA_DRAM_BASE (BAR0_BASE + 0x4000ll) //This is where the microcode will be written
//***********************************************************************************************
//**
//** VDMA Sequencer Microcode:
//**
//** The following microcode will get compiled and converted into a series of write cycles
//** so that the BFM will write the microcode into descriptor memory. The last function call
//** vdma_process() will cross reference all of the labels in the source code so that you
//** end up with the proper hexadecimal values that need to be written to descriptor RAM.
//**
//***********************************************************************************************
void vdma_main()
{
//===============================================================================================
// START of the main program loop
//===============================================================================================
// Example source code to be compiled into VDMA binarys or test bench script
vdma_org(0x0000);
vdma_label("MAIN");
vdma_nop();
vdma_label("DO_L2P0");
vdma_load_sys_addr(_IM,"L2P0_SYS_ADDR"); //Load system address from SG entry
vdma_load_xfer_ctl(_IM,"L2P0_XFER_CTL"); //Start DMA0
vdma_label("DO_L2P1");
vdma_load_sys_addr(_IM,"L2P1_SYS_ADDR"); //Load system address from SG entry
vdma_load_xfer_ctl(_IM,"L2P1_XFER_CTL"); //Start DMA1
vdma_label("WAIT4IDLE");
vdma_jmp(_EXT_COND_LO,_LDM_IDLE,"WAIT4IDLE"); //Loop until DMA idle
vdma_sig_event(0, 1, 0x0001);
vdma_label("FOREVER");
vdma_nop();
vdma_jmp(_ALWAYS, 0,"FOREVER"); //Loop forever
//===============================================================================================
// END of the main program loop
//===============================================================================================
//
//-----------------------------------------------------------------------------------------------
// Constants
//-----------------------------------------------------------------------------------------------
vdma_org(0x0100);
vdma_label("L2P0_SYS_ADDR");
vdma_constant_n64(BFM_BAR0_BASE+0x200); //L2P0 system address low/hi
vdma_label("L2P0_XFER_CTL");
vdma_constant_n(0x00010080); //L2P0 transfer control: 128B, STREAM_ID=1
vdma_label("L2P1_SYS_ADDR");
vdma_constant_n64(BFM_BAR1_BASE+0x200); //L2P1 system address low/hi
vdma_label("L2P1_XFER_CTL");
vdma_constant_n(0x00040080); //L2P1 transfer control: 128B, STREAM_ID=4
//===============================================================================================
// Must run vdma_process to resolve the cross-references and generate the memory writes
//===============================================================================================
vdma_process(VDMA_DRAM_BASE); // This actually printfs the data to the file
}
//***********************************************************************************************
//**
//** Main:
//**
//** Edit the program below to create your own test script.
//**
//***********************************************************************************************
main(argc,argv)
int argc;
char *argv[];
{
//-----------------------------------------------------------------------------------------------
// Always call maketest_init at the beginning of a test program
//-----------------------------------------------------------------------------------------------
maketest_init(argc,argv);
//================================================================================================
//== START of user script
//================================================================================================
comment("-----------------------------------------------------------------------------");
comment("Generated from: simple.c - do not edit the vec file directly as it is not the source!");
comment("Short example of using the lambo TestBench");
comment("-----------------------------------------------------------------------------");
comment("Select the GN4124 Primary BFM");
model(0);
comment("Initialize the BFM to its default state");
init();
comment("\nDrive reset to the FPGA");
reset(16);
comment("\n");
comment("-----------------------------------------------------------------------------");
comment("Initialize the Primary GN412x BFM model");
comment("-----------------------------------------------------------------------------");
comment("These address ranges will generate traffic from the BFM to the FPGA");
comment("bar BAR ADDR SIZE VC TC S");
bar(0, BAR0_BASE, 0x08000000, 0, 7, 0);
bar(1, BAR1_BASE, 0x10000000, 1, 5, 0);
comment("\nThis allocates a RAM block inside the BFM for the FPGA to access");
comment("bfm_bar BAR ADDR SIZE");
bfm_bar(0, BFM_BAR0_BASE, 0x20000000);
bfm_bar(1, BFM_BAR1_BASE, 0x20000000);
comment("\nWait until the FPGA is un-reset and ready for traffic on the local bus");
wait(64);
comment("\n-------------------------------------------------------------------------------");
comment("DO some setup");
comment("-------------------------------------------------------------------------------");
comment("Lambo setup...");
rd(BAR0_BASE + DMA_SEQ_CSR_REG, 0xF, 0x00000000, 0xFFFFFFFF);
flush(0x100);
wr(BAR0_BASE + DMA_SEQ_DPTR_REG, 0xF, 0x0);
wr(BAR0_BASE + DMA_SEQ_EVENT_EN_REG, 0xF, 0x1);
wr(BAR0_BASE + DMA_SEQ_EVENT_CLR_REG, 0xF, 0xFFFFFFFF);
wr(BAR0_BASE + APP_CFG, 0xF, 0x6);
wr(BAR0_BASE + APP_CFG, 0xF, 0x0);
wr(BAR0_BASE + DMA_CFG, 0xF, 0x1F);
wr(BAR0_BASE + DMA_CFG, 0xF, 0x7);
wr(BAR0_BASE + APP_GEN_COUNT, 0xF, 0x0);
wr(BAR0_BASE + APP_RCV_COUNT, 0xF, 0x0);
wr(BAR0_BASE + APP_RCV_ERR_COUNT, 0xF, 0x0);
wr(BAR0_BASE + DMA_PAYLOAD_SIZE, 0xF, 0x8020);
comment("\n-------------------------------------------------------------------------------");
comment("Setup the DMA microcode");
comment("-------------------------------------------------------------------------------");
vdma_main();
comment("\nStart VDMA");
wr(BAR0_BASE + DMA_SEQ_CSR_REG, 0xF, 0x1);
gpio_wait(300, 0x0001, 0x0001);
comment("\nRead VDMA idle status");
rd(BAR0_BASE + DMA_SEQ_CSR_REG, 0xF, 0x00000000, 0xFFFFFFFF);
flush(256);
wait(16);
//================================================================================================
//== END of user script
//================================================================================================
fclose(outfp);
exit(0);
}
hdl/spec/sim/Test_Builder/simple_dma.hex 0 → 100644
View file @ 11fc3280
0x0000 0x00000000 MAIN: vdma_nop()
0x0001 0x40000100 DO_L2P0: vdma_load_sys_addr(r=_IM, "L2P0_SYS_ADDR")
0x0002 0xF0000102 vdma_load_xfer_ctl(_IM, "L2P0_XFER_CTL")
0x0003 0x40000103 DO_L2P1: vdma_load_sys_addr(r=_IM, "L2P1_SYS_ADDR")
0x0004 0xF0000105 vdma_load_xfer_ctl(_IM, "L2P1_XFER_CTL")
0x0005 0x17210005 WAIT4IDLE: vdma_jmp(c=_EXT_COND_LO, ext_cond=_LDM_IDLE, "WAIT4IDLE")
0x0006 0x84000001 vdma_sig_event(s=0, a=1, event_en=0x0001)
0x0007 0x00000000 FOREVER: vdma_nop()
0x0008 0x1A000007 vdma_jmp(c=_ALWAYS, ext_cond=NA, "FOREVER")
0x0100 0x20000200 L2P0_SYS_ADDR: vdma_constant_n64(0x8765432120000200)
0x0101 0x87654321 // vdma_constant_n64 - upper data
0x0102 0x00010080 L2P0_XFER_CTL: vdma_constant_n(0x00010080)
0x0103 0x40000200 L2P1_SYS_ADDR: vdma_constant_n64(0xBB00000040000200)
0x0104 0xBB000000 // vdma_constant_n64 - upper data
0x0105 0x00040080 L2P1_XFER_CTL: vdma_constant_n(0x00040080)
// Label Listing:
// 0x0000 : "MAIN"
// 0x0001 : "DO_L2P0"
// 0x0003 : "DO_L2P1"
// 0x0005 : "WAIT4IDLE"
// 0x0007 : "FOREVER"
// 0x0100 : "L2P0_SYS_ADDR"
// 0x0102 : "L2P0_XFER_CTL"
// 0x0103 : "L2P1_SYS_ADDR"
// 0x0105 : "L2P1_XFER_CTL"
hdl/spec/sim/_Makefile 0 → 100644
View file @ 11fc3280
TESTBENCH = testbench
DDRMODEL = sim_models/2048Mb_ddr3
SPEC = ../rtl
GNCORE = ../../../../GN4124_core/hdl/gn4124core/rtl
GNCORE_IP = ../../../../GN4124_core/hdl/spec/ip_cores
DDRCORE = ../../../../ddr3_ctrl_core/hdl/rtl
DDRCORE_IP = ../../../../ddr3_ctrl_core/hdl/spec/ip_cores/ddr_ctrl_bank3/user_design/rtl
# These are the technology specific files
#GLBL = unisims
#FPGA = unisims
VHDL_LIB = testbench
MK = mk
# Change VCOM and VLOG for use with other simulation tools
VCOM = vcom
VLOG = vlog
TOUCH = echo "" > $@
spec : $(MK)/tb_spec.mk
bfm : $(MK)/tb_gn412x.mk
clean :
rm -f $(MK)/*.mk
vdel -lib work -all
vlib work
##################################################################################################
# SPEC Test Bench Project
##################################################################################################
$(MK)/tb_spec.mk : $(TESTBENCH)/tb_spec.vhd $(MK)/spec_ddr_test.mk $(MK)/gn412x_bfm.mk $(MK)/cmd_router.mk \
$(MK)/ddr3.mk
$(VCOM) $(TESTBENCH)/tb_spec.vhd
$(TOUCH)
##################################################################################################
# SPEC Project
##################################################################################################
$(MK)/spec_ddr_test.mk : $(SPEC)/spec_ddr_test.vhd $(MK)/gn4124_core.mk \
$(MK)/gpio_regs.mk $(MK)/ddr3_ctrl.mk
$(VCOM) $(SPEC)/spec_ddr_test.vhd
$(TOUCH)
$(MK)/gpio_regs.mk : $(SPEC)/gpio_regs.vhd
$(VCOM) $(SPEC)/gpio_regs.vhd
$(TOUCH)
# GN4124 core
$(MK)/gn4124_core.mk : $(GNCORE)/spartan6/gn4124_core.vhd $(MK)/gn4124_core_pkg.mk $(MK)/p2l_des.mk \
$(MK)/p2l_decode32.mk $(MK)/wbmaster32.mk $(MK)/l2p_arbiter.mk $(MK)/l2p_ser.mk \
$(MK)/dma_controller.mk $(MK)/l2p_dma_master.mk $(MK)/p2l_dma_master.mk \
$(MK)/serdes_1_to_n_clk_pll_s2_diff.mk
$(VCOM) $(GNCORE)/spartan6/gn4124_core.vhd
$(TOUCH)
$(MK)/gn4124_core_pkg.mk : $(GNCORE)/spartan6/gn4124_core_pkg.vhd
$(VCOM) $(GNCORE)/spartan6/gn4124_core_pkg.vhd
$(TOUCH)
$(MK)/p2l_des.mk : $(GNCORE)/spartan6/p2l_des.vhd $(MK)/serdes_1_to_n_data_s2_se.mk
$(VCOM) $(GNCORE)/spartan6/p2l_des.vhd
$(TOUCH)
$(MK)/p2l_decode32.mk : $(GNCORE)/p2l_decode32.vhd
$(VCOM) $(GNCORE)/p2l_decode32.vhd
$(TOUCH)
$(MK)/wbmaster32.mk : $(GNCORE)/wbmaster32.vhd $(MK)/fifo_32x512.mk $(MK)/fifo_64x512.mk
$(VCOM) $(GNCORE)/wbmaster32.vhd
$(TOUCH)
$(MK)/l2p_arbiter.mk : $(GNCORE)/l2p_arbiter.vhd
$(VCOM) $(GNCORE)/l2p_arbiter.vhd
$(TOUCH)
$(MK)/dma_controller.mk : $(GNCORE)/dma_controller.vhd $(MK)/dma_controller_wb_slave.mk
$(VCOM) $(GNCORE)/dma_controller.vhd
$(TOUCH)
$(MK)/l2p_dma_master.mk : $(GNCORE)/l2p_dma_master.vhd $(MK)/fifo_32x512.mk
$(VCOM) $(GNCORE)/l2p_dma_master.vhd
$(TOUCH)
$(MK)/p2l_dma_master.mk : $(GNCORE)/p2l_dma_master.vhd $(MK)/fifo_64x512.mk
$(VCOM) $(GNCORE)/p2l_dma_master.vhd
$(TOUCH)
$(MK)/dma_controller_wb_slave.mk : $(GNCORE)/dma_controller_wb_slave.vhd
$(VCOM) $(GNCORE)/dma_controller_wb_slave.vhd
$(TOUCH)
$(MK)/l2p_ser.mk : $(GNCORE)/spartan6/l2p_ser.vhd $(MK)/serdes_n_to_1_s2_se.mk \
$(MK)/serdes_n_to_1_s2_diff.mk
$(VCOM) $(GNCORE)/spartan6/l2p_ser.vhd
$(TOUCH)
$(MK)/serdes_1_to_n_clk_pll_s2_diff.mk : $(GNCORE)/spartan6/serdes_1_to_n_clk_pll_s2_diff.vhd
$(VCOM) $(GNCORE)/spartan6/serdes_1_to_n_clk_pll_s2_diff.vhd
$(TOUCH)
$(MK)/serdes_1_to_n_data_s2_se.mk : $(GNCORE)/spartan6/serdes_1_to_n_data_s2_se.vhd
$(VCOM) $(GNCORE)/spartan6/serdes_1_to_n_data_s2_se.vhd
$(TOUCH)
$(MK)/serdes_n_to_1_s2_se.mk : $(GNCORE)/spartan6/serdes_n_to_1_s2_se.vhd
$(VCOM) $(GNCORE)/spartan6/serdes_n_to_1_s2_se.vhd
$(TOUCH)
$(MK)/serdes_n_to_1_s2_diff.mk : $(GNCORE)/spartan6/serdes_n_to_1_s2_diff.vhd
$(VCOM) $(GNCORE)/spartan6/serdes_n_to_1_s2_diff.vhd
$(TOUCH)
$(MK)/fifo_32x512.mk : $(GNCORE_IP)/fifo_32x512.vhd
$(VCOM) $(GNCORE_IP)/fifo_32x512.vhd
$(TOUCH)
$(MK)/fifo_64x512.mk : $(GNCORE_IP)/fifo_64x512.vhd
$(VCOM) $(GNCORE_IP)/fifo_64x512.vhd
$(TOUCH)
# DDR3 core
$(MK)/ddr3_ctrl.mk : $(DDRCORE)/ddr3_ctrl.vhd $(MK)/ddr3_ctrl_wb.mk $(MK)/ddr3_ctrl_wrapper.mk
$(VCOM) $(DDRCORE)/ddr3_ctrl.vhd
$(TOUCH)
$(MK)/ddr3_ctrl_wb.mk : $(DDRCORE)/ddr3_ctrl_wb.vhd
$(VCOM) $(DDRCORE)/ddr3_ctrl_wb.vhd
$(TOUCH)
$(MK)/ddr3_ctrl_wrapper.mk : $(DDRCORE)/../spec/rtl/ddr3_ctrl_wrapper.vhd $(MK)/ddr_ctrl_bank3.mk
$(VCOM) $(DDRCORE)/../spec/rtl/ddr3_ctrl_wrapper.vhd
$(TOUCH)
$(MK)/ddr_ctrl_bank3.mk : $(DDRCORE_IP)/ddr_ctrl_bank3.vhd $(MK)/memc3_infrastructure.mk $(MK)/memc3_wrapper.mk
$(VCOM) $(DDRCORE_IP)/ddr_ctrl_bank3.vhd
$(TOUCH)
$(MK)/memc3_infrastructure.mk : $(DDRCORE_IP)/memc3_infrastructure.vhd
$(VCOM) $(DDRCORE_IP)/memc3_infrastructure.vhd
$(TOUCH)
$(MK)/memc3_wrapper.mk : $(DDRCORE_IP)/memc3_wrapper.vhd $(MK)/mcb_raw_wrapper.mk
$(VCOM) $(DDRCORE_IP)/memc3_wrapper.vhd
$(TOUCH)
$(MK)/mcb_raw_wrapper.mk : $(DDRCORE_IP)/mcb_raw_wrapper.vhd $(MK)/mcb_soft_calibration_top.mk
$(VCOM) $(DDRCORE_IP)/mcb_raw_wrapper.vhd
$(TOUCH)
$(MK)/mcb_soft_calibration_top.mk : $(DDRCORE_IP)/mcb_soft_calibration_top.vhd $(MK)/mcb_soft_calibration.mk
$(VCOM) $(DDRCORE_IP)/mcb_soft_calibration_top.vhd
$(TOUCH)
$(MK)/mcb_soft_calibration.mk : $(DDRCORE_IP)/mcb_soft_calibration.vhd $(MK)/iodrp_controller.mk \
$(MK)/iodrp_mcb_controller.mk
$(VCOM) $(DDRCORE_IP)/mcb_soft_calibration.vhd
$(TOUCH)
$(MK)/iodrp_controller.mk : $(DDRCORE_IP)/iodrp_controller.vhd
$(VCOM) $(DDRCORE_IP)/iodrp_controller.vhd
$(TOUCH)
$(MK)/iodrp_mcb_controller.mk : $(DDRCORE_IP)/iodrp_mcb_controller.vhd
$(VCOM) $(DDRCORE_IP)/iodrp_mcb_controller.vhd
$(TOUCH)
##################################################################################################
# Test Bench Project
##################################################################################################
$(MK)/tb_gn412x.mk : $(TESTBENCH)/tb_gn412x.vhd $(MK)/gn412x_bfm.mk $(MK)/cmd_router.mk
$(VCOM) $(TESTBENCH)/tb_gn412x.vhd
$(TOUCH)
$(MK)/gn412x_bfm.mk : $(TESTBENCH)/gn412x_bfm.vhd $(MK)/textutil.mk $(MK)/mem_model.mk
$(VCOM) $(TESTBENCH)/gn412x_bfm.vhd
$(TOUCH)
$(MK)/mem_model.mk : $(VHDL_LIB)/mem_model.vhd
$(VCOM) -87 $(VHDL_LIB)/mem_model.vhd
$(TOUCH)
$(MK)/textutil.mk : $(VHDL_LIB)/textutil.vhd $(MK)/util.mk
$(VCOM) $(VHDL_LIB)/textutil.vhd
$(TOUCH)
$(MK)/util.mk : $(VHDL_LIB)/util.vhd
$(VCOM) $(VHDL_LIB)/util.vhd
$(TOUCH)
$(MK)/cmd_router.mk : $(TESTBENCH)/cmd_router.vhd $(MK)/cmd_router1.mk $(MK)/textutil.mk
$(VCOM) $(TESTBENCH)/cmd_router.vhd
$(TOUCH)
$(MK)/cmd_router1.mk : $(TESTBENCH)/cmd_router1.vhd $(MK)/textutil.mk
$(VCOM) $(TESTBENCH)/cmd_router1.vhd
$(TOUCH)
# DDR3 model
$(MK)/ddr3.mk : $(DDRMODEL)/ddr3.v
$(VLOG) +incdir+$(DDRMODEL) +define+sg15E +define+x16 $(DDRMODEL)/ddr3.v
$(TOUCH)
hdl/spec/sim/cmd0.vec 0 → 100644
View file @ 11fc3280
-- ***********************************************************************************
-- *** Warning: this file is automatically generated. ***
-- ***********************************************************************************
-- *** Do not edit this file directly as it is not the source! ***
-- ***********************************************************************************
-------------------------------------------------------------------------------
-- Generated from: simple.c - do not edit the vec file directly as it is not the source!
-- Short example of using the lambo TestBench
-------------------------------------------------------------------------------
-- Select the GN4124 Primary BFM
model %d0
-- Initialize the BFM to its default state
init
-- Drive reset to the FPGA
reset %d16
-------------------------------------------------------------------------------
-- Initialize the Primary GN412x BFM model
-------------------------------------------------------------------------------
-- These address ranges will generate traffic from the BFM to the FPGA
-- bar BAR ADDR SIZE VC TC S
bar 0 FF00000000000000 08000000 0 7 0
--bar 1 FF000000A0000000 10000000 1 5 0
-- This allocates a RAM block inside the BFM for the FPGA to access
-- bfm_bar BAR ADDR SIZE
bfm_bar 0 0000000040000000 20000000
bfm_bar 1 0000000020000000 20000000
-- bfm_bar 0 BB00000040000000 20000000
-- bfm_bar 1 00000000123456f8 20000000
-- Wait until the FPGA is un-reset and ready for traffic on the local bus
wait %d64
-------------------------------------------------------------------------------
-- Access the descriptor memory in the Lambo design
-------------------------------------------------------------------------------
-- the following three writes will go out in a single packet
wr 0000000040000000 F C0FFEE82
wr 0000000040000004 F 00000001
wr 0000000040000008 F 00000002
wr 000000004000000C F 00000003
wr 0000000040000010 F 00000004
wr 0000000040000014 F 00000005
wr 0000000040000018 F 00000006
wr 000000004000001C F 00000007
wr 0000000040000020 F 00000008
wr 0000000040000024 F 00000009
wr 0000000040000028 F 0000000A
wr 000000004000002C F 0000000B
wr 0000000040000030 F 0000000C
wr 0000000040000034 F 0000000D
wr 0000000040000038 F 0000000E
wr 000000004000003C F 0000000F
wr 0000000040000040 F 00000010
wr 0000000040000044 F 00000011
wr 0000000040000048 F 00000012
wr 000000004000004C F 00000013
wr 0000000040000050 F 00000014
wr 0000000040000054 F 00000015
wr 0000000040000058 F 00000016
wr 000000004000005C F 00000017
wr 0000000040000060 F 00000018
wr 0000000040000064 F 00000019
wr 0000000040000068 F 0000001A
wr 000000004000006C F 0000001B
wr 0000000040000070 F 0000001C
wr 0000000040000074 F 0000001D
wr 0000000040000078 F 0000001E
wr 000000004000007C F 0000001F
wr 0000000040000080 F 00000020
wr 0000000040000084 F 00000021
wr 0000000040000088 F 00000022
wr 000000004000008C F 00000023
wr 0000000040000090 F 00000024
wr 0000000040000094 F 00000025
wr 0000000040000098 F 00000026
wr 000000004000009C F 00000027
wr 00000000400000A0 F 00000028
wr 00000000400000A4 F 00000029
wr 00000000400000A8 F 0000002A
wr 00000000400000AC F 0000002B
wr 00000000400000B0 F 0000002C
wr 00000000400000B4 F 0000002D
wr 00000000400000B8 F 0000002E
wr 00000000400000BC F 0000002F
wr 00000000400000C0 F 00000030
wr 0000000040000F00 F 00000F00
wr 0000000040000F04 F 00000F01
wr 0000000040000F08 F 00000F02
wr 0000000040000F0C F 00000F03
wr 0000000040000F10 F 00000F04
wr 0000000040000F14 F 00000F05
wr 0000000040000F18 F 00000F06
wr 0000000040000F1C F 00000F07
wr 0000000040000F20 F 00000F08
wr 0000000040000F24 F 00000F09
wr 0000000040000F28 F 00000F0A
wr 0000000040000F2C F 00000F0B
wr 0000000040000F30 F 00000F0C
wr 0000000040000F34 F 00000F0D
wr 0000000040000F38 F 00000F0E
wr 0000000040000F3C F 00000F0F
wr 0000000040000F40 F 00000F10
wr 0000000040000F44 F 00000F11
wr 0000000040000F48 F 00000F12
wr 0000000040000F4C F 00000F13
wr 0000000040000F50 F 00000F14
wr 0000000040000F54 F 00000F15
wr 0000000040000F58 F 00000F16
wr 0000000040000F5C F 00000F17
wr 0000000040000F60 F 00000F18
wr 0000000040000F64 F 00000F19
wr 0000000040000F68 F 00000F1A
wr 0000000040000F6C F 00000F1B
wr 0000000040000F70 F 00000F1C
wr 0000000040000F74 F 00000F1D
wr 0000000040000F78 F 00000F1E
wr 0000000040000F7C F 00000F1F
wr 0000000040000F80 F 00000F20
wr 0000000040000F84 F 00000F21
wr 0000000040000F88 F 00000F22
wr 0000000040000F8C F 00000F23
wr 0000000040000F90 F 00000F24
wr 0000000040000F94 F 00000F25
wr 0000000040000F98 F 00000F26
wr 0000000040000F9C F 00000F27
wr 0000000040000FA0 F 00000F28
wr 0000000040000FA4 F 00000F29
wr 0000000040000FA8 F 00000F2A
wr 0000000040000FAC F 00000F2B
wr 0000000040000FB0 F 00000F2C
wr 0000000040000FB4 F 00000F2D
wr 0000000040000FB8 F 00000F2E
wr 0000000040000FBC F 00000F2F
-- CSR wishbone test
rd FF00000000040000 F DEAD0000 FFFF0000
wr FF0000000008000C F 00000003
rd FF0000000008000C F 00000003 FFFFFFFF
wait %d640
-- DDR access trough CSR wishbone
--wr FF000000000C0004 F DEADC0DE
--wait %d300
--rd FF000000000C0004 F DEADC0DE FFFFFFFF
wait %d300
-- DDR access trough DMA wishbone
wr 0000000020000000 F 00000000
wr 0000000020000004 F 40000000
wr 0000000020000008 F 00000000
-- DMA length
wr 000000002000000C F 00000004
wr 0000000020000010 F 00000000
wr 0000000020000014 F 00000000
wr 0000000020000018 F 00000000
-- wrb FF00000010004004 F 00000000
wr FF00000000000008 F 00000000
wr FF0000000000000C F 40000000
wr FF00000000000010 F 00000000
-- DMA length
wr FF00000000000014 F 00000004
wr FF00000000000018 F 20000000
wr FF0000000000001C F 00000000
wr FF00000000000020 F 00000003
wr FF00000000000000 F 00000001
-- Now read back what was just written
-- the following three reads will go out as a single request
--rdb FF00000010004004 F FEEDFACE FFFFFFFF
--rdb FF00000010004008 F DBDBDBDB FFFFFFFF
--rd FF00000010004008 F DEADBEEF FFFFFFFF
--wrb FF0000001000401C F 00000000
--wrb FF00000010004024 F 00000000
--wr FF00000010004000 F 00000001
--rdb FF00000010004000 F 00000002 FFFFFFFF
--rdb FF00000010004004 F 00000000 FFFFFFFF
--rdb FF00000010004008 F 5A5A5A5A FFFFFFFF
--rdb FF0000001000400C F 12345678 FFFFFFFF
--rdb FF00000010004010 F 00000000 FFFFFFFF
--rdb FF00000010004014 F 00000010 FFFFFFFF
--rdb FF00000010004018 F 00000000 FFFFFFFF
--rdb FF0000001000401C F 00000000 FFFFFFFF
--rd FF00000010004020 F 00000000 FFFFFFFF
wait %d160
--wr FF00000010004000 F 00000001
--rd FF0000001000400C F DEADBEEF FFFFFFFF
--rd FF00000010004008 F ABABABAB FFFFFFFF
wait %d
flush %d256
wait %d16
sync
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m255
K3
13
cModel Technology
Z0 d/home/mcattin/projects/GN4124_core/hdl_trunk/spec/sim
Exilinx_dummy_sim
w1311674401
Z1 d/home/mcattin/projects/GN4124_core/hdl_trunk/spec/sim
8../../gn4124core/ip_cores/general-cores/modules/genrams/xilinx/sim_stub/dummy.vhd
F../../gn4124core/ip_cores/general-cores/modules/genrams/xilinx/sim_stub/dummy.vhd
l0
L1
VKd8^[`j@TZDeV[[hfDI:J0
!s100 nF<;LZ6J0iDiIE_]ATjaA3
Z2 OE;C;6.6e_1;45
32
o-quiet -work fifo_generator_v6_1
Z3 tExplicit 1
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vsim -novopt -t 1ps tb_spec
log -r /*
do wave.do
view wave
view transcript
run 15000 ns
##run 25057 ns
##force -freeze sim:/tb_lambo/l2p_rdy 0 0 -cancel {80 ns}
##run 1 us
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files = ["mem_model.vhd"]
vcom_opt = "-87"
hdl/spec/sim/testbench/cmd_router.vhd 0 → 100644
View file @ 11fc3280
library IEEE;
use IEEE.std_logic_1164.all;
use std.textio.all;
--library std_developerskit;
--use std_developerskit.std_iopak.all;
use work.util.all;
use work.textutil.all;
--==========================================================================--
--
-- *MODULE << cmd_router >>
--
-- *Description : This module routes commands to all command driven modules
-- in the simulation. It instanciates N_FILES instances of
-- cmd_router1 and agregates the outputs to control N_BFM BFMs.
--
-- *History: M. Alford (originaly created 1993 with subsequent updates)
--
--==========================================================================--
--==========================================================================--
-- Operation
--
-- This module opens a text file and passes commands to individual vhdl models.
--
--==========================================================================--
entity cmd_router is
generic( N_BFM : integer := 8;
N_FILES : integer := 3;
FIFO_DEPTH : integer := 16;
STRING_MAX : integer := 256
);
port( CMD : out string(1 to STRING_MAX);
CMD_REQ : out bit_vector(N_BFM-1 downto 0);
CMD_ACK : in bit_vector(N_BFM-1 downto 0);
CMD_ERR : in bit_vector(N_BFM-1 downto 0);
CMD_CLOCK_EN : out boolean
);
end cmd_router;
architecture MODEL of cmd_router is
component cmd_router1
generic( N_BFM : integer := 8;
FIFO_DEPTH : integer := 8;
STRING_MAX : integer := 256;
FILENAME : string :="cmdfile.vec"
);
port( CMD : out STRING(1 to STRING_MAX);
CMD_REQ : out bit_vector(N_BFM-1 downto 0);
CMD_ACK : in bit_vector(N_BFM-1 downto 0);
CMD_ERR : in bit_vector(N_BFM-1 downto 0);
CMD_CLOCK_EN : out boolean;
CMD_DONE_IN : in boolean;
CMD_DONE_OUT : out boolean
);
end component; -- cmd_router1
type FILE_ARRAY is array (natural range <>) of string(1 to 8);
type CMD_ARRAY is array (natural range <>) of string(CMD'range);
type CMD_REQ_ARRAY is array (natural range <>) of bit_vector(N_BFM-1 downto 0);
type integer_vector is array (natural range <>) of integer;
type boolean_vector is array (natural range <>) of boolean;
constant MAX_FILES : integer := 10;
constant FILENAMES : FILE_ARRAY(0 to MAX_FILES-1) := ( "cmd0.vec", "cmd1.vec",
"cmd2.vec", "cmd3.vec",
"cmd4.vec", "cmd5.vec",
"cmd6.vec", "cmd7.vec",
"cmd8.vec", "cmd9.vec" );
signal CMDo : CMD_ARRAY(N_FILES-1 downto 0);
signal REQ : bit_vector(CMD_REQ'range);
signal CMD_REQo : CMD_REQ_ARRAY(N_FILES-1 downto 0);
signal CMD_ACKi : CMD_REQ_ARRAY(N_FILES-1 downto 0);
signal CMD_ACK_MASK : CMD_REQ_ARRAY(N_FILES-1 downto 0); -- 1 bit_vector per file to mask CMD_ACK
signal CMD_CLOCK_ENo : boolean_vector(N_FILES-1 downto 0);
signal CMD_ALL_DONE : boolean;
signal CMD_DONE_OUT : boolean_vector(N_FILES-1 downto 0);
function or_reduce(ARG: bit_vector) return bit is
variable result: bit;
begin
result := '0';
for i in ARG'range loop
result := result or ARG(i);
end loop;
return result;
end;
function or_reduce(ARG: boolean_vector) return boolean is
variable result: boolean;
begin
result := FALSE;
for i in ARG'range loop
result := result or ARG(i);
end loop;
return result;
end;
function and_reduce(ARG: boolean_vector) return boolean is
variable result: boolean;
begin
result := TRUE;
for i in ARG'range loop
result := result and ARG(i);
end loop;
return result;
end;
begin
-----------------------------------------------------------------------------
-- Instanciate 1 cmd_router1 per file to be processed
-----------------------------------------------------------------------------
G1 : for i in 0 to N_FILES-1 generate
U1 : cmd_router1
generic map
( N_BFM => N_BFM,
FIFO_DEPTH => FIFO_DEPTH,
STRING_MAX => STRING_MAX,
FILENAME => FILENAMES(i)
)
port map
( CMD => CMDo(i),
CMD_REQ => CMD_REQo(i),
CMD_ACK => CMD_ACKi(i),
CMD_ERR => CMD_ERR,
CMD_CLOCK_EN => CMD_CLOCK_ENo(i),
CMD_DONE_IN => CMD_ALL_DONE,
CMD_DONE_OUT => CMD_DONE_OUT(i)
);
end generate;
-----------------------------------------------------------------------------
-- Multiplex the commands from the cmd_router1 modules
-----------------------------------------------------------------------------
process
variable vDONE : boolean;
begin
CMD <= (others => '0');
wait on CMD_REQo;
vDONE := FALSE;
while(not vDONE) loop
vDONE := TRUE;
for i in 0 to N_FILES-1 loop -- Loop on each file
if(or_reduce(CMD_REQo(i)) = '1') then -- this file wants to do a command
vDONE := FALSE;
--
-- if the ACK is already on from another cmd_router1
--
while(or_reduce(CMD_REQo(i) and CMD_ACK) = '1') loop
wait on CMD_ACK;
end loop;
--
-- Do the request
--
CMD <= CMDo(i);
REQ <= CMD_REQo(i);
--
-- Wait for the ACK
--
wait until(CMD_ACK'event and (or_reduce(CMD_ACK and REQ) = '1'));
--
-- send the ack to the proper file
--
for j in 0 to N_FILES-1 loop
if(i = j) then -- enable this one
CMD_ACK_MASK(j) <= CMD_ACK_MASK(j) or REQ;
else
CMD_ACK_MASK(j) <= CMD_ACK_MASK(j) and not REQ;
end if;
end loop;
--
-- Wait for the request to de-assert
--
while(or_reduce(CMD_REQo(i) and REQ) = '1') loop
wait on CMD_REQo;
end loop;
REQ <= (others => '0');
end if;
end loop;
end loop;
end process;
process(CMD_ACK, CMD_ACK_MASK)
begin
for i in 0 to N_FILES-1 loop -- Loop on each file
CMD_ACKi(i) <= CMD_ACK and CMD_ACK_MASK(i);
end loop;
end process;
CMD_REQ <= REQ;
CMD_ALL_DONE <= and_reduce(CMD_DONE_OUT);
CMD_CLOCK_EN <= CMD_CLOCK_ENo(0);
end MODEL;
hdl/spec/sim/testbench/cmd_router1.vhd 0 → 100644
View file @ 11fc3280
library IEEE;
use IEEE.std_logic_1164.all;
use std.textio.all;
--library std_developerskit;
--use std_developerskit.std_iopak.all;
use work.util.all;
use work.textutil.all;
--==========================================================================--
--
-- *MODULE << model1 >>
--
-- *Description : This module routes commands to all command driven modules
-- in the simulation.
--
-- *History: M. Alford (originaly created 1993 with subsequent updates)
--
--==========================================================================--
--==========================================================================--
-- Operation
--
-- This module opens a text file and passes commands to individual vhdl models.
--
--==========================================================================--
entity cmd_router1 is
generic( N_BFM : integer := 8;
FIFO_DEPTH : integer := 8;
STRING_MAX : integer := 256;
FILENAME : string :="cmdfile.vec"
);
port( CMD : out STRING(1 to STRING_MAX);
CMD_REQ : out bit_vector(N_BFM-1 downto 0);
CMD_ACK : in bit_vector(N_BFM-1 downto 0);
CMD_ERR : in bit_vector(N_BFM-1 downto 0);
CMD_CLOCK_EN : out boolean;
CMD_DONE_IN : in boolean;
CMD_DONE_OUT : out boolean
);
end cmd_router1;
architecture MODEL of cmd_router1 is
type STRING_ARRAY is array (FIFO_DEPTH-1 downto 0) of STRING(1 to STRING_MAX);
type FD_ARRAY is array (N_BFM-1 downto 0) of STRING_ARRAY;
type integer_vector is array (natural range <>) of integer;
signal FD : FD_ARRAY;
signal ERR_CNT : integer;
signal PUSH_PTR : integer_vector(N_BFM-1 downto 0);
signal POP_PTR : integer_vector(N_BFM-1 downto 0);
signal SET_CHAN : std_ulogic;
signal POP_INIT : std_ulogic;
signal CMD_REQo : bit_vector(CMD_REQ'range);
signal LINE_NUM : integer;
begin
PUSH_PROCESS : process
file FOUT : text open write_mode is "usc.lst";
file stim_file : text open read_mode is FILENAME;
file out_file : text open write_mode is "STD_OUTPUT";
-------- For VHDL-87
-- file stim_file : text is in FILENAME;
-- file out_file : text is out "STD_OUTPUT";
variable input_line : line;
variable output_line : line;
variable tmp_lout : line;
variable command : string(1 to 8);
variable tmp_str : string(1 to STRING_MAX);
variable input_str : string(1 to STRING_MAX);
variable i : integer;
variable CHANNEL : integer;
variable S_PTR : integer;
variable vLINE_NUM : integer;
variable vPUSH_PTR : integer_vector(N_BFM-1 downto 0);
variable DONE : boolean;
variable EOS : integer;
variable ERR : integer;
begin
-----------------------------------------------------------------------------
-- Main Loop
-----------------------------------------------------------------------------
vLINE_NUM := 0;
PUSH_PTR <= (others => 0);
vPUSH_PTR := (others => 0);
CHANNEL := 0;
CMD_CLOCK_EN <= TRUE;
SET_CHAN <= '0';
CMD_DONE_OUT <= FALSE;
if(POP_INIT /= '1') then
wait until(POP_INIT'event and (POP_INIT = '1'));
end if;
ST_LOOP: while not endfile(stim_file) loop
readline(stim_file, input_line);
S_PTR := 1;
vLINE_NUM := vLINE_NUM + 1;
LINE_NUM <= vLINE_NUM;
-- Copy the line
input_str := (others => ' ');
input_str(1 to 6) := To_Strn(vLINE_NUM, 6);
input_str(7 to 8) := string'(": ");
input_str(9 to input_line'length+8) := string'(input_line.all);
while(input_str(S_PTR) /= ':') loop
S_PTR := S_PTR + 1;
end loop;
S_PTR := S_PTR + 1;
sget_token(input_str, S_PTR, command);
SET_CHAN <= '1';
for j in STRING_MAX downto 1 loop
if(input_str(j) /= ' ') then
EOS := j;
exit;
end if;
end loop;
---------------------------
-- "model" command ?
---------------------------
if(command(1 to 5) = "model") then
sget_int(input_str, S_PTR, i);
write(tmp_lout, FILENAME);
write(tmp_lout, input_str(1 to EOS));
writeline(out_file, tmp_lout);
if((i >= N_BFM) or (i < 0)) then
CHANNEL := N_BFM-1;
write(tmp_lout, string'("ERROR: Invalid Channel "));
write(tmp_lout, i);
writeline(out_file, tmp_lout);
else
CHANNEL := i;
end if;
---------------------------
-- "sync" command ?
---------------------------
elsif(command(1 to 4) = "sync") then
loop
DONE := TRUE;
for i in PUSH_PTR'reverse_range loop
if((vPUSH_PTR(i) /= POP_PTR(i)) or (CMD_ACK(i) /= '0')) then
DONE := FALSE;
end if;
end loop;
if(DONE) then
exit;
end if;
wait on POP_PTR, CMD_ACK;
end loop;
write(tmp_lout, FILENAME);
write(tmp_lout, input_str(1 to EOS));
writeline(out_file, tmp_lout);
---------------------------
-- "gsync" and "ckoff" command ?
---------------------------
elsif((command(1 to 5) = "gsync") or (command(1 to 5) = "ckoff")) then
write(tmp_lout, FILENAME);
write(tmp_lout, string'(": entering the gsync command"));
writeline(out_file, tmp_lout);
loop
DONE := TRUE;
for i in PUSH_PTR'reverse_range loop
if((vPUSH_PTR(i) /= POP_PTR(i)) or (CMD_ACK(i) /= '0')) then
DONE := FALSE;
end if;
end loop;
if(DONE) then
exit;
end if;
wait on POP_PTR, CMD_ACK;
end loop;
CMD_DONE_OUT <= TRUE;
-- wait for the external CMD_DONE_IN to be done
while (not CMD_DONE_IN) loop
wait on CMD_DONE_IN;
end loop;
CMD_DONE_OUT <= FALSE;
write(tmp_lout, FILENAME);
write(tmp_lout, input_str(1 to EOS));
writeline(out_file, tmp_lout);
if (command(1 to 5) = "ckoff") then
CMD_CLOCK_EN <= FALSE;
end if;
write(tmp_lout, FILENAME);
write(tmp_lout, string'(": gsync command is DONE"));
writeline(out_file, tmp_lout);
--------------------
-- ckon
--------------------
elsif (command(1 to 4) = "ckon") then
CMD_CLOCK_EN <= TRUE;
write(tmp_lout, FILENAME);
write(tmp_lout, input_str(1 to EOS));
writeline(out_file, tmp_lout);
---------------------------
-- put the line in the FIFO
---------------------------
else
FD(CHANNEL)(vPUSH_PTR(CHANNEL)) <= input_str;
vPUSH_PTR(CHANNEL) := vPUSH_PTR(CHANNEL) + 1;
if(vPUSH_PTR(CHANNEL) >= FIFO_DEPTH) then
vPUSH_PTR(CHANNEL) := 0;
end if;
if(vPUSH_PTR(CHANNEL) = POP_PTR(CHANNEL)) then -- The FIFO is full
wait until(POP_PTR'event and (vPUSH_PTR(CHANNEL) /= POP_PTR(CHANNEL)));
end if;
PUSH_PTR(CHANNEL) <= vPUSH_PTR(CHANNEL);
end if;
end loop;
loop
DONE := TRUE;
for i in POP_PTR'reverse_range loop
if((POP_PTR(i) /= vPUSH_PTR(i)) or (CMD_ACK(i) = '1')) then -- FIFO channel not empty
DONE := FALSE;
end if;
end loop;
if(DONE) then
exit;
end if;
wait on CMD_ACK, POP_PTR;
end loop;
CMD_DONE_OUT <= TRUE;
write(output_line, string'("******************************* Test Finished *******************************"));
writeline(out_file, output_line);
write(output_line, string'("* Total Errors for "));
write(output_line, FILENAME);
write(output_line, string'(": "));
write(output_line, err_cnt);
writeline(out_file, output_line);
write(output_line, string'("*****************************************************************************"));
writeline(out_file, output_line);
file_close(stim_file); -- Close File
loop
wait for 100000 us;
end loop;
end process;
-----------------------------------------------------------------------------
-- POP Process
-----------------------------------------------------------------------------
POP_PROCESS : process
variable vPOP_PTR : integer_vector(POP_PTR'range);
variable DONE : boolean;
file out_file : text open write_mode is "STD_OUTPUT";
-------- For VHDL-87
-- file out_file : text is out "STD_OUTPUT";
variable tmp_lout : line;
variable CHAR_PTR : integer;
variable EOS : integer;
begin
CHAR_PTR := 1;
ERR_CNT <= 0;
POP_PTR <= (others => 0);
vPOP_PTR := (others => 0);
CMD_REQo <= (others => '0');
POP_INIT <= '1';
if(SET_CHAN /= '1') then
wait until(SET_CHAN'event and (SET_CHAN = '1'));
end if;
loop
DONE := FALSE;
loop
DONE := TRUE;
for i in POP_PTR'reverse_range loop
if((vPOP_PTR(i) /= PUSH_PTR(i)) and (CMD_ACK(i) = '0')) then -- FIFO channel not empty
CMD <= FD(i)(vPOP_PTR(i));
CMD_REQo(i) <= '1';
for j in STRING_MAX downto 1 loop
if(FD(i)(vPOP_PTR(i))(j) /= ' ') then
EOS := j;
exit;
end if;
end loop;
write(tmp_lout, FILENAME);
write(tmp_lout, FD(i)(vPOP_PTR(i))(1 to EOS));
writeline(out_file, tmp_lout);
if(CMD_ACK(i) /= '1') then
wait until(CMD_ACK'event and (CMD_ACK(i) = '1'));
end if;
CMD_REQo(i) <= '0';
DONE := FALSE;
vPOP_PTR(i) := vPOP_PTR(i) + 1;
if(vPOP_PTR(i) >= FIFO_DEPTH) then
vPOP_PTR(i) := 0;
end if;
POP_PTR(i) <= vPOP_PTR(i);
end if;
end loop;
if(DONE) then
exit;
end if;
end loop;
wait on PUSH_PTR, CMD_ACK;
end loop;
end process;
CMD_REQ <= CMD_REQo;
end MODEL;
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-------------------------------------------------------------------------------
-- simple.vec
-- Short example of using the lambo TestBench
-------------------------------------------------------------------------------
-- Select the GN4124 Primary BFM
model 0
-- Initialize the BFM to its default state
init
-- Drive reset to the FPGA
reset 10
-------------------------------------------------------------------------------
-- Initialize the Primary GN412x BFM model
-------------------------------------------------------------------------------
-- These address ranges will generate traffic from the Primary to the Secondary BFM
-- bar BAR ADDR SIZE VC TC S
bar 0 FF00000010000000 08000000 0 7 0
bar 1 FF000000A0000000 10000000 1 5 0
-- This allocates a RAM block inside the BFM for the FPGA to access
-- bfm_bar BAR ADDR SIZE
bfm_bar 0 8765432120000000 20000000
bfm_bar 1 BB00000040000000 20000000
-- Wait until the FPGA is un-reset and ready for traffic on the local bus
wait 40
-------------------------------------------------------------------------------
-- Access the descriptor memory in the Lambo design
-------------------------------------------------------------------------------
-- the following three writes will go out in a single packet
wrb FF00000010004000 F 87654321
wrb FF00000010004004 F FEEDFACE
wr FF00000010004008 F DEADBEEF
-- Now read back what was just written
-- the following three reads will go out as a single request
rdb FF00000010004000 F 87654321 FFFFFFFF
rdb FF00000010004004 F FEEDFACE FFFFFFFF
rd FF00000010004008 F DEADBEEF FFFFFFFF
flush 100
wait 10
sync
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