Skip to content
GitLab
Explore
Sign in
Primary navigation
Search or go to…
Project
G
Gennum GN4124 core
Manage
Activity
Members
Labels
Plan
Issues
0
Issue boards
Milestones
Wiki
Code
Merge requests
0
Repository
Branches
Commits
Tags
Repository graph
Compare revisions
Deploy
Releases
Monitor
Incidents
Service Desk
Analyze
Value stream analytics
Contributor analytics
Repository analytics
Model experiments
Help
Help
Support
GitLab documentation
Compare GitLab plans
Community forum
Contribute to GitLab
Provide feedback
Keyboard shortcuts
?
Snippets
Groups
Projects
Projects
Gennum GN4124 core
Graph
4221b11247d18cb59bc0addb68b56b6827d539d5
Select Git revision
Branches
3
ltgt_add_axi4_slave
ltgt_wb_dma_wr_turnarround_bugfix
master
default
protected
Tags
12
v3.1.2
protected
v3.1.1
protected
v3.1.0
protected
v3.0.1
protected
v3.0.0
protected
btrain-v1.2
btrain-v2.5
v2.0
protected
v2.0.0
protected
v1.0
protected
v1.0.0
protected
revision-beta
15 results
You can move around the graph by using the arrow keys.
Begin with the selected commit
Created with Raphaël 2.2.0
14
Feb
29
Jan
2
Oct
1
23
Sep
7
Dec
20
Nov
15
27
Oct
24
Jul
29
Jun
3
Nov
28
May
29
Apr
13
Nov
9
5
4
3
29
Oct
12
9
29
Sep
27
Jul
24
4
Sep
3
30
Aug
29
28
23
8
7
6
5
1
17
Jul
16
20
May
6
30
Apr
26
12
14
Mar
13
Feb
30
Jan
29
28
23
29
Nov
26
Oct
17
Sep
30
Aug
13
Jun
8
26
Mar
20
19
14
Dec
22
Aug
27
Apr
12
31
May
18
Mar
16
Sep
1
Jul
30
Jun
23
19
May
16
Mar
5
Sep
10
Jun
3
Apr
20
Mar
31
Jan
1
Mar
19
Nov
5
Oct
6
Feb
6
Jan
6
Dec
5
22
Nov
12
Aug
9
3
2
29
Jul
26
25
11
8
7
29
Jun
13
Apr
24
Mar
24
Feb
3
2
31
Jan
28
11
10
Dec
8
29
Nov
26
19
17
12
11
8
5
4
3
29
Oct
27
25
21
20
19
7
6
5
1
30
Sep
29
27
24
23
21
20
8
7
6
3
2
1
31
Aug
26
13
12
29
Jul
27
20
13
7
6
28
Jun
21
3
2
1
28
May
27
21
4
29
Apr
Define two separate functions for SRAM_Initialize
master
master
Reneame the address_trans functions
Rewrite the word default to default_val
Update .ohwr.yaml
Update .ohwr.yaml
Update .ohwr.yaml
add a component to insert a axi pipeline stage under control of a generic.
ltgt_add_axi4_s…
ltgt_add_axi4_slave
Merge branch '5-release-v3-1-2' into 'master'
update changelog
v3.1.2
v3.1.2
Merge branch '4-simplify-l2p_dma_master-fifo-reset-logic' into 'master'
hdl: simplify l2p_dma_master fifo reset logic
Merge branch '3-timing-issues-related-to-l2p_arbiter-outputs' into 'master'
hdl: relax timing for l2p_arbiter outputs
Merge branch 'release-v311' into 'master'
Fix component, create release
v3.1.1
v3.1.1
Add AXI4 slave RTL and testbench
bugfix WB_DMA wr->RD wishbone bus turnarrounf bug.
ltgt_wb_dma_wr_…
ltgt_wb_dma_wr_turnarround_bugfix
Add testcase for DMA R2W anw W2R bus turnarrounds.
Relax timing pressure on dma_ctrl_direction
Add missing CHANGELOG point
v3.1.0
v3.1.0
Add CHANGELOG entry for 3.1.0
sim: modify testbench to test long p2l dma transfers.
p2l_dma_master: allow transfer longer than 4096 bytes.
p2l_dma_master: more refactoring
p2l_dma_master: refactoring
gn412x_bfm: add labels to processes.
gn412x_bfm: remove unused code.
gn412x_bfm: work arounds for issues in questa sim.
gn412x_bfm: remove unused signals/variables.
l2p_dma_master: add a comment
l2p_dma_master.vhd: do not cross 4KB page boundary
l2p_dma_master: simplify the FSM
Add a comment
l2p_dma_master: minor simplification.
dma_controller.vhd: remove one state, clarify the code
p2l_dma_master: refactoring.
p2l_dma_master: fix incorrect handling of stall signal.
Merge tag 'v3.0.1' into proposed_master
Merge branch 'release/3.0.1'
v3.0.1
v3.0.1
bld: update changelog