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Gennum GN4124 core
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Gennum GN4124 core
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eef550ec1e227704af35739ff2168e80eda70d75
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3
master
default
protected
ltgt_add_axi4_slave
ltgt_wb_dma_wr_turnarround_bugfix
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12
v3.1.2
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v3.1.1
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v3.1.0
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v3.0.1
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v3.0.0
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btrain-v1.2
btrain-v2.5
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revision-beta
15 results
gn4124-core
hdl
sim
example_tb
run.do
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authors
Andreas Bergmann
bergya
Dimitris Lampridis
dlampridis
Erik van der Bij
erikvanderbij
Grzegorz Daniluk
greg.d
Javier D. Garcia-Lasheras
garcialasheras
Javier Serrano
serrano
Juan David González Cobas
dcobas
Maciej Lipinski
lipinskimm
Michel Arruat
arruat
Phil Clarke
phil_cl
Timon Heim
theim
Tomasz Wlostowski
twlostow
Tristan Gingold
tgingold
Vasco Guita
vasco.guita
14 authors
Aug 08, 2019
[hdl] update and expand example testbench
· 3159ffcd
Dimitris Lampridis
authored
5 years ago
3159ffcd
Aug 06, 2019
[hdl] sanitise folder structure
· 352c0db5
Dimitris Lampridis
authored
5 years ago
352c0db5
Apr 26, 2019
sim: add a reset signal to the testbench, makes simulators happier
· 89701fe0
Dimitris Lampridis
authored
5 years ago
89701fe0
Jan 23, 2019
hdl: introduce example_tb testbench to demonstrate basic use of GN4124 BFM
· 254c6ef9
Dimitris Lampridis
authored
6 years ago
254c6ef9