Following up on 6c4dca2c, this commit fixes one issue related to resets and performs
further reset and clock-domain crossing (CDC) cleanup.

Important changes include:

1. Make sure that all dual async fifos are reset on both sides. This solves an issue
   with soft resets causing the host PC to hang.

2. Remove c_RST_ACTIVE constant to make the code simpler.

3. Remove reset from many signals (in particular from wide, data signals) that do not
   need to be reset. This helps with meeting timing wrt reset distribution.

4. Remove synchronizers from p2l deserializers, the SERDES outputs are already synced
   to the FPGA clock.

Important changes include:

1. Clear separation of resets per clock domain (with the exception
   of the wbgen-generated dma controller registers).

2. Conversion of all processes to use synchronous resets when the
   reset is synced with the clock of the process.

3. Use of standard synchronizers from general-cores when crossing
   clock-domains.

Due to the change in processes to use sync resets, a lot of code
has changed indentation. To this end, it might be useful to perform
a case insensitive diff when studying the changes of this commit.

Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

Fake merge (using 'ours' strategy) to make sure that commit 2710742b stays, since it is used by a BTrain-over-WR release.

The commit itself is already rebased onto proposed_master as 9b9625bb.

sim: SV BFM assignment to port does not need MODPORT, greatly reduces number of warnings in Modelsim

rtl/wbmaster32: fix a nasty freeze when accesses are very tightly spaced: CIDs should be also FIFOed!