Bugfix of random freezes, when having back pressure

hdl/gn4124core/rtl/p2l_dma_master.vhd

@@ -42,8 +42,7 @@ library IEEE;
 use IEEE.STD_LOGIC_1164.all;
 use IEEE.NUMERIC_STD.all;
 use work.gn4124_core_pkg.all;
-use work.genram_pkg.all;
-
+use work.common_pkg.all;
 
 entity p2l_dma_master is
   generic (
@@ -128,8 +127,7 @@ end p2l_dma_master;
 
 
 architecture behaviour of p2l_dma_master is
-
-
+    
   -----------------------------------------------------------------------------
   -- Constants declaration
   -----------------------------------------------------------------------------
@@ -182,6 +180,7 @@ architecture behaviour of p2l_dma_master is
   signal wb_ack_cnt    : unsigned(31 downto 0);
   signal p2l_dma_cyc_t : std_logic;
   signal p2l_dma_stb_t : std_logic;
+  signal p2l_dma_stall_d : std_logic_vector(1 downto 0);
 
   -- P2L DMA read request FSM
   type   p2l_dma_state_type is (P2L_IDLE, P2L_HEADER, P2L_ADDR_H, P2L_ADDR_L, P2L_WAIT_READ_COMPLETION);
@@ -403,6 +402,8 @@ begin
     elsif rising_edge(clk_i) then
       rx_error_o      <= rx_error_t;
       dma_ctrl_done_o <= dma_ctrl_done_t;
+      p2l_dma_stall_d(0) <= p2l_dma_stall_i;
+      p2l_dma_stall_d(1) <= p2l_dma_stall_d(0);
     end if;
   end process p_ctrl_pipe;
 
@@ -593,7 +594,7 @@ begin
       -- cyc signal management
       if (to_wb_fifo_valid = '1') then
         p2l_dma_cyc_t <= '1';
-      elsif (wb_ack_cnt = wb_write_cnt-1 and p2l_dma_ack_i = '1') then
+      elsif (wb_ack_cnt >= wb_write_cnt and p2l_dma_stall_d(1) = '0') then
         -- last ack received -> end of the transaction
         p2l_dma_cyc_t <= '0';
       end if;
@@ -627,6 +628,7 @@ begin
       end if;
     end if;
   end process p_wb_ack_cnt;
+      
 
 end behaviour;